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LTC222CN Linear Technology LTC222 - Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches; Package: PDIP; Pins: 16; Temperature Range: 0°C to 70°C
LTC221CS Linear Technology LTC221 - Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC222CS Linear Technology LTC222 - Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC221CS#TR Linear Technology LTC221 - Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC222CS#TR Linear Technology LTC222 - Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C
LTC221CN#PBF Linear Technology LTC221 - Micropower, Low Charge Injection, Quad CMOS Analog Switches with Data Latches; Package: PDIP; Pins: 16; Temperature Range: 0°C to 70°C

8212 latch Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
intel 8212

Abstract: D 8212 intel 8212 latch 8212 microprocessor 8212 processor 8212 Micro Processor Intel 8008 8212 8bit P8212 8212 INTEL
Text: State Outputs ■Outputs Sink 15 mA The 8212 input/output port consists of an 8-bit latch with 3 , Latch Here the 8212 is used as the status latch for an 8080A microcomputer system. The input to the 8212 latch is directly from the8080A data bus. Timing shows that when the SYNC signal is true, which is , LATCH D> °0 8212 CLR ds2 md DS, =r¡3 ■INTA • WÖ ■STACK ■HLTA ■OUT . Ml â , inter 8212 8-BIT INPUT/OUTPUT PORT ■Fully Parallel 8-Bit Data Register and Buffer â


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PDF AFN-00731 intel 8212 D 8212 intel 8212 latch 8212 microprocessor 8212 processor 8212 Micro Processor Intel 8008 8212 8bit P8212 8212 INTEL
IC 8212

Abstract: f 8212 F8212 SR flip flop IC 8212 latch sr flip flop processor 8212 ic LC 8712 8212 8bit 0O731C
Text: LATCH SETS SR FLIP FLOP (NO EFFECT ON OUTPUT BUFFER) 2-56 AFN-00731C 8212 ABSOLUTE MAXIMUM , Input Port 2-59 8212 808A Status Latch Here the 8212 Is used as the status latch fo r an 8080A m icro com p uter system. The inpu t to the 8212 latch is d ire c tly fro m the 8080A data bus. T im , latched in to the 8212 . Note: The m ode signal is tied h igh so that the ou tput on the latch is active , ¡n te f 8212 8-BIT INPUT/OUTPUT PORT Fully Parallel 8-Bit Data Register and Buffer Service


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PDF AFN-00731C APN-00731C 00731C IC 8212 f 8212 F8212 SR flip flop IC 8212 latch sr flip flop processor 8212 ic LC 8712 8212 8bit 0O731C
8085 microprocessor realtime application

Abstract: 8085 microprocessor realtime application any one fabrication of 8085 microprocessor 8085 microprocessor four channel data acquisition system "BCD Switch" 8212 latch interfacing of ram with 8085 8085 clock circuit 8085 microprocessor applications processor 8212
Text: . A data latch is required to avoid losing the data when the three-state bus drivers return to their high-impedance state. The-rising edge of STAT strobes the data into the 8212 latch and, after some propagation , CLR STG DO I Oil 002 012 8212 007 017 i8 018 OS? td DBO OBI CLK A0758I DB6 _ STAT 0B7 _ , available to latch the data internally, and becomes necessary when the AD7581 is used in 8085 systems and , would cause unnecessary transients at the memory latch . The decoder requires a read-strobe signal, which


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PDF the8085and6800. AD7581 8085 microprocessor realtime application 8085 microprocessor realtime application any one fabrication of 8085 microprocessor 8085 microprocessor four channel data acquisition system "BCD Switch" 8212 latch interfacing of ram with 8085 8085 clock circuit 8085 microprocessor applications processor 8212
block and pin diagram of 8257

Abstract: IC 8212 internal block diagram DMA Controller 8257 intel 8257 dma 8257 DIWA 200 ic 8257 block diagram intel 8212 intel 8257 interrupt controller 8257
Text: the DMA address registers) to the 8212 latch via the data bus. These address bits will be transferred , ) device which, when coupled with a single Intel® 8212 I/O port device, provides a complete four-channel , memory address to the 8212 I/O port via the data bus (the 8212 places these address bits on lines A8-A15 , memory address into the 8212 device from the data bus. (AEN) Address Enable: This output is used to , \ DATA BUS \ DRQO DACK 0 8257 AND 8212 DRO 1 DACK t DIRQ 2 DACK 2 DflQ 3 DACK 3 SYSTEM RAM


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PDF MCS-85Â T9-50 Tcy-50 2Tcy-50 AFN-01840B block and pin diagram of 8257 IC 8212 internal block diagram DMA Controller 8257 intel 8257 dma 8257 DIWA 200 ic 8257 block diagram intel 8212 intel 8257 interrupt controller 8257
AR8161

Abstract: ARM DII 0238 KEYBOARD CONTROLLER 8049 intel 8049 microcomputer intel AP-54 b342 transistor b175 transistor MCS6200 8049 microcontroller APPLICATION INTEL 8049 IC
Text: an 8212 latch . The latch is interfaced to the BUS PORT on the 8049 and is enabled whenever the WR pin , 8049 to the outside world one 8212 latch was used. This latch was connected to the BUS PORT and is , this configuration, the 8212 was used to hold the data until read by the 8049. The connection of the 8212 to the 8049 is shown in Figure 3.4 and the parallel port timing diagram is shown in Figure 3.5. The 8212 parallel port was connected to the LINE PRINTER OUTPUT of an INTELLEC MICROCOM PUTER


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PDF AP-91 AFN-01364A-01 AR8161 ARM DII 0238 KEYBOARD CONTROLLER 8049 intel 8049 microcomputer intel AP-54 b342 transistor b175 transistor MCS6200 8049 microcontroller APPLICATION INTEL 8049 IC
block and pin diagram of 8257

Abstract: IC 8212 internal block diagram ic 8257 block diagram i8257 DMA Controller 8257 d8257 bu 808 af intel 8257 interrupt controller 8257 E8257C
Text: w ith a single Intel® 1 8212 I/O po rt device, provides a com plete four-channel DM A co n tro lle r , eight bits of the m em ory address to the 8212 I/O port via the data bus (the 8212 places these address , ignifica nt eig h t-b its of the m em ory address (from one o f the DM A address registersi to the 8212 latch via the data bus. These address bits w ill be transferred at the beginning o f the DMA cycle: the , em ory address into the 8212 device from the data bus. (AEN) Address Enable This ou tput is used to


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PDF MCS-85® pli257 block and pin diagram of 8257 IC 8212 internal block diagram ic 8257 block diagram i8257 DMA Controller 8257 d8257 bu 808 af intel 8257 interrupt controller 8257 E8257C
B331 transistor

Abstract: transistor b331 Transistor B28D A 42 B331 transistor A 92 B331 transistor A 42 B331 transistor B324 KT 117A 851B52 intel 8049 microcomputer
Text: and can tolerate much higher levels of current. The print head drivers are connected to an 8212 latch . The latch is interfaced to the BUS PORT on the 8049 and is enabled whenever the WR pin and the BIT 4 , 1 21 2 19 3 17 4 15 5 10 6 8 7 6 a> ■C* DOe DO? Die Dl? DOe DOs 8212 Die nis DO4 DO3 DU Dli DO2 DO1 DI2 Dh DO1 DSi INT D11 ÜU2 Di' noi ÍI11 noi ni4 DOs 8212 Die noe Die DO , LINEFEED DRIVER 1 OPTO-TRIAC MOTOR DRIVER * THE 8212 AND THE 2716 WOULD NOT BE NEEDED IF AN 8049 WAS


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PDF AP-91 AP-27 AP-54) B331 transistor transistor b331 Transistor B28D A 42 B331 transistor A 92 B331 transistor A 42 B331 transistor B324 KT 117A 851B52 intel 8049 microcomputer
microprocessor 8212 block diagram

Abstract: F 8212 8212 microprocessor 8212 8212 functional block diagram 51406 8212 latch
Text: part of American Microsemi's 8080 support family.The 8212 can be used to implement latches, gat ed , system can be implemented with this device. The MCB8212/MCD8212 includes an 8-bit latch with output , -Bit data latch and buffer Service request flip-flop for generation and control of interrupts 0.25 mA input load current Outputs sink 15 mA Asynchronous latch clear 3.65V output for direct interface to , 3.65 -1 5 4.0 4.0 -7 5 20 8212 MCD8212 90 90 145 130 V V V V mA (¿A mA mA VF = 0.45V VF = 0.45V


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PDF MCB8212 MCB8212/MCD8212 MCB8212 24-pin TL/F/6624-11 MCD8212orMCBB212 microprocessor 8212 block diagram F 8212 8212 microprocessor 8212 8212 functional block diagram 51406 8212 latch
IC 8212

Abstract: f 8212 dac8212 dac-8212 PMI processor 8212 DAC8212FV IC 8212 internal pin diagram IC 8212 control word register microprocessor 8212 DAC8212HP
Text: structure versatility of the DAC- 8212 . Data loading into its 12-bit wide data latch is simplified by the use , entire 12-bit word is then loaded into the DAC- 8212 's data latch on the next write cycle. An alternate , in Die Form DUAL 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTER DAC - 8212 WR and CS lines , FUNCTIONAL DIAGRAM ft GENERAL DESCRIPTION The DAC- 8212 combines two identical 12-bit, multiplying , and track ing over the full operating temperature range. The DAC- 8212 consists of two thin-film R


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PDF 12-Btt 12-Blt 12-BIT DAC-8212 IC 8212 f 8212 dac8212 dac-8212 PMI processor 8212 DAC8212FV IC 8212 internal pin diagram IC 8212 control word register microprocessor 8212 DAC8212HP
8085 hardware timing diagram manual

Abstract: 8085 opcode sheet free 8085 opcode sheet MC6840 opcode sheet 8085 8085 pin 8085 MICROCOMPUTER SYSTEMS USERS MANUAL MEK6800D2 M6840 memory interfacing to mp 8085
Text: , as shown in Figure 2-6. This approach uses the 8212 latch to separate the address and data lines for , 'LS 00 AO A1 8212 A2 8 BIT ¿o LATCH ^ A4 A5 A6 A7 'LS 04 ss04 O IRQ RESET D0—D7 R/W RSO RS1 RS2 , .3-2 3.4 COUNTER LATCH 3.5 EXAMPLE COUNTER 3.5.1 Writing to a Timer Latch , : IN RXXX (READ INSTRUCTION) OUT WXXX (WRITE INSTRUCTION) Further, when writing to a timer latch or


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PDF MC6840UM MC6840 8085 hardware timing diagram manual 8085 opcode sheet free 8085 opcode sheet opcode sheet 8085 8085 pin 8085 MICROCOMPUTER SYSTEMS USERS MANUAL MEK6800D2 M6840 memory interfacing to mp 8085
f 8212

Abstract: No abstract text available
Text: ented w ith the Am8212. The Am 8212 in p u t/o u tp u t p o rt consists o f an 8- latch w ith 3-state o , D 8212 P8212 A M 8 21 2 X C Am8212 M D (Mode) F U N C T IO N A L D E S C R IPTIO N (Cont'd , source o f the clock in p u t (C) to the data latch . Data Latch The 8 flip -flo p s th a t make up the data latch are o f a " D " type design. The o u tp u t (Q) o f the flip -flo p w ill fo llo w the , f clock (C) to the data latch is fro m the device selection logic (D 5 i • DS2 ). The d ata


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PDF Am8212 Am8212 f 8212
8355 8755 intel microprocessor block diagram

Abstract: MCS-48 8755 intel microprocessor block diagram intel 8755 USART 8251 expanded block diagram MCS48 instruction set The Expanded MCS-48 System MCS-48 Manual mcs48 internal architecture of 8251 USART
Text: the eight bit address out on the bus and strobes it into the 8212 latch with the ALE (Address Latch , shown. The additional component required is the 8212 eight bit latch . This latch is loaded, when ever a , appropriate latch . The latches are loaded by the write pulse (WR) whenever the proper address is presented to , lower four addresses (A 3 -A0 ) are stored in a latch which addresses the multiplexer. The coincidence , F 3 14 I/O U N C O M M IT T E D D l5 d i4 8212 do D1 p 17 p 16 h s p 14 p 13


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PDF 98-413B MCS-48TM NL-10Q6 8355 8755 intel microprocessor block diagram MCS-48 8755 intel microprocessor block diagram intel 8755 USART 8251 expanded block diagram MCS48 instruction set The Expanded MCS-48 System MCS-48 Manual mcs48 internal architecture of 8251 USART
IC 8212

Abstract: 8212D p3212 U 3212 M 3212 Buffer P8212 D8212 M8212
Text: A m 3 2 1 2 · A m 8212 . The mode signal is tied high so that the output on the latch is active and , consists of an 8- latch w ith 3-state output buffers along w ith control and device selection logic, w hich , A M To p V ie w " i d m d · 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 Am 3212 Am 8212 19 , Latch M D (Mode) The 8 flip-flops that make up the data latch are of a " D " type design. The output , w ill occur when the clock (C ) returns low. The data latch is cleared by an asynchronous reset


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PDF Am3212 Am8212 Am9080A Am3212 IC 8212 8212D p3212 U 3212 M 3212 Buffer P8212 D8212 M8212
POWER MODULE SVI 3101 D

Abstract: bc power module svi 3101 d SVI 3206 SVI 3101 POWER MODULE SVI 3101 temperature digital display JUMO Lan M UAA 1004 DP INTERFACING OUTPUT DISPLAYS 8212 tda 8210 TDA 9394
Text: RAM Refresh Controller New Product Announcement.5-99 I/O 8212 8-Bit I/O Port Functional Description.5-101 System Applications oi the 8212 .5-103 Data Sheet , array and the address latch or the incrementer/ decrements circuit. The address tatch receives data from , incrementer/ decrementar circuit. The incrementer/décrémenter circuit receives data from the address latch , -bit latch that, in turn, drives the data bus output buffers. The output buffers are switched off during


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PDF
intel 8212

Abstract: No abstract text available
Text: Signetics 54F432 Latch Multi-Mode Buffered Latch , INV (3-State) Military Logic Products , 8212 except that 54F432 has inverting outputs DESCRIPTION The 54F432 has 8 data latches with 3 , equivalent to the Intel 8212 except that the 54F432 has inverting outputs. ORDERING INFORMATION , 291 853-1225 F01393 Signetics Military Logic Products Product Specification Latch , Specification Latch 54F432 FUNCTIONAL DESCRIPTION This high-performance eight-bit parallel ex pandable


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PDF 54F432 300mil-wlde 54F432 500ns intel 8212
nec 8212

Abstract: cept lpd d D8257 PD8257 DMA Controller 8257 8212 nec HPD8257C-5 Schematic diagram of DRO NEC PD8257 8212 functional block diagram
Text: to be strobed to an external latch via ADDSTB. RESET Clears the command, status, request, and , internal operations and data transfer rate. AEN (Address Enable) This signal allows the external latch , into an external latch . HLDA (Hold Acknowledge) Indicates that the CPU has relinquished control of , 8212 I/O port device, it provides a complete four-channel DMA con troller for use in 8080A/8085A based , word is generated with the aid of an 8212 in the following manner: (a) The ^PD8257 outputs the least


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PDF uPD8257 fiPD8257 PD8257 pPD8257 nec 8212 cept lpd d D8257 DMA Controller 8257 8212 nec HPD8257C-5 Schematic diagram of DRO NEC PD8257 8212 functional block diagram
IC LA 4127

Abstract: la 4127 P3212 8212D
Text: Am3212/Am8212 F U N C T IO N A L D E S C R IP T IO N (C ont'd) Data Latch The 8 flip -flo p s th a t m ake up th e data latch are o f a " D " typ e design. The o u tp u t (Q) o f th e flip - f lo p w ill , occur w hen the c lo c k (C) re tu rn s lo w . The d ata latch is cleared b y an asynch ro n o us reset , enables th e b u ffe r to tra n s m it th e data fro m th e o u tp u ts o f th e data latch (Q) or , e th e source o f th e c lo c k in p u t (C) to th e data latch . When M D is high ( o u tp u t m ode


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PDF Am3212 Am8212 LIC-436 IC LA 4127 la 4127 P3212 8212D
Multiplying Data Converters

Abstract: AD9713B Four Double Buffered 12-bit DACs 8212 16pin model dac08 DAC312
Text: AD9713B DAC-312 (MDAC) AD7537 (Dual) AD7547 (Dual) DAC-8248 (Dual) DAC- 8212 (Dual, MDAC) DAC-8221 (Dual , Comments 8-Bit High Speed Multiplying DAC CMOS, Low Cost, 8-Bit Multiplying DAC with Latch Ultrahigh Speed , -Bit DAC, Single or Dual Supply CMOS, Improved AD7545 Bipolar Output, Double Buffered Latch CMOS, Byte Load , -8221 DAC-8248 AD7537 AD7547 DAC- 8212 Res Bits 8 8 8 12 12 12 12 12 Settling Time (is typ 0.18 0.19


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PDF 12-Bit AD7243 14-Bit AD7840 DAC-01 AD558 AD7224 AD7225 AD7226 AD7228A Multiplying Data Converters AD9713B Four Double Buffered 12-bit DACs 8212 16pin model dac08 DAC312
F432

Abstract: No abstract text available
Text: 432 54F/74F432 Connection Diagrams Multi-Mode Buffered Latch With 3-State Outputs Description The 'F432 is an 8-bit latch with 3-state output buffers and control and device selection logic , also operate in a fu lly transparent mode. The 'F432 is the functional equivalent of the Intel 8212 , 0.5/0.375 75/15 (12.5) 0.5/0.375 0.5/0.375 0.5/0.375 25/12.5 0.5/0.375 Data Inputs Latch , , the eight data latch inputs are enabled when the strobe is HIGH regardless of device selection. If


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PDF 54F/74F432 54F/74F F432
intel 8212

Abstract: No abstract text available
Text: 412 54F/74F412 Multi-Mode Buffered Latch W ith 3-State Outputs Description The 'F412 is an 8-bit latch with 3-state output buffers. Also included is a status flip-flop for providing device-busy or , of the Intel 8212 . · · · · 3-State Outputs Status Flip-flop for Interrupt Commands Asynchronous or , -d 7 CLR STB ÎRT M §1>S2 Latch Outputs Data Inputs Clear Strobe Interrupt Mode Control Input Select , . Latch transparency is selected by the mode control (M), select (S1 and Sj), and the strobe (STB) inputs


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PDF 54F/74F412 24-Pln 54F/74F intel 8212
intel 8212

Abstract: D 8212 intel
Text: 412 54F/74F412 Multi-Mode Buffered Latch With 3-State Outputs Description The 'F412 is an 8-bit latch with 3-state output buffers. Also included is a status flip-flop for providing device-busy or , of the Intel 8212 . • 3-State Outputs • Status Flip-flop for Interrupt Commands â , Description 54F/74F(U.L.) HIGH/LOW O0-O7 Latch Outputs 75/15 (12.5) d0-d7 Data Inputs 0.5/0.375 CLR Clear , enable, G, input is HIGH and the outputs are enabled. Latch transparency is selected by the mode control


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PDF 54F/74F412 24-Pin 54F/74F intel 8212 D 8212 intel
2008 - optically clear adhesive

Abstract: F 8212 8211 D1003-92 Gardner 8870 8212 D-3654
Text: Technical Data November, 2008 3MTM Optically Clear Adhesives 8211 · 8212 · 8213 · 8215 , and others requiring an optically clear bond. 3MTM Optically Clear Adhesives 8211 / 8212 / 8213 / 8215 3M OCA 8211, 8212 , 8213 and 8215 are for use in general purpose applications including display touch , Carrier: Approximate Thickness: Release Liner Acrylic None 3MTM Optically Clear Adhesive 8212 8213 Acrylic , Optically Clear Adhesives 8211 · 8212 · 8213 · 8215 Typical Physical Properties and Performance


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PDF 1-1W-10, optically clear adhesive F 8212 8211 D1003-92 Gardner 8870 8212 D-3654
2010 - TCS 9708

Abstract: RT 8214 optically clear adhesive D1003-92 8214 8212 ASTM-D3330 f 8212
Text: Technical Data January, 2010 3MTM Optically Clear Adhesives 8211 · 8212 · 8213 · 8214 · 8215 , and others requiring an optically clear bond. 3MTM Optically Clear Adhesives 8211 / 8212 / 8213 / 8214 / 8215 3M OCA 8211, 8212 , 8213, 8214 and 8215 are for use in general purpose applications including , Type: Adhesive Carrier: Approximate Thickness: Release Liner Acrylic None 8212 Acrylic None 3MTM , Liner 3 3MTM Optically Clear Adhesives 8211 · 8212 · 8213 · 8214 · 8215 Typical Physical


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PDF 225-3S-06 TCS 9708 RT 8214 optically clear adhesive D1003-92 8214 8212 ASTM-D3330 f 8212
intel 8212

Abstract: 8212 latch 74F432 8212 D 8212 intel F432
Text: 432 54F/74F432 Connection Diagrams Multi-Mode Buffered Latch With 3-State Outputs Description The 'F432 is ari 8-bit latch with 3-state output buffers and control and device selection logic , also operate in a fully transparent mode. The 'F432 is the functional equivalent of the Intel 8212 , 54F/74F(U.L.) HIGH/LOW d0-d7 Data Inputs 0.5/0.375 o0-o7 Latch Outputs 75/15 (12.5) Si,S2 Select , enable, G, input is HIGH and the outputs are enabled. Latch transparency is selected by the mode control


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PDF 54F/74F432 24-Pin 54F/74F intel 8212 8212 latch 74F432 8212 D 8212 intel F432
ID8085A

Abstract: ID8085 3212 Buffer
Text: Temperature Range: -40°C to +85°C The 18212 input/output port consists of an 8-bit latch with 3 , : The specifications for the 3212 are identical with those for the 8212 . DEVICE SELECTION e> OSl-oJ , > L) I, - m>D'8- [TT>crR- -T°) ^ (NT DATA LATCH I O Q CH E 'ACTIVE LOW lOWi I / .


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PDF ID8085A afn-00856b ID8085 3212 Buffer
Supplyframe Tracking Pixel