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Part Manufacturer Description Datasheet Download Buy Part
BQ2031SN-A5TRG4 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0
BQ2031SN-A5 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0
BQ2031SN-A5G4 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0
BQ2031SN-A5TR Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-SOIC 0 to 0
TCA5013ZAHR Texas Instruments Smart Card Interface IC for 1 User Card + 3 SAMs 48-NFBGA -40 to 85
BQ2031PN-A5 Texas Instruments Switch-mode Lead-Acid Battery Charger with User-Selectable Charge Algorithms 16-PDIP 0 to 0

80c196KB users Datasheets Context Search

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1996 - MCS-96 Macro Assembler Users guide

Abstract: MCS-96 Users guide 80C196KB 80C196KB instruction set 74164 counter MCS-96 development intel asm-96 122350 270646 80c196KB users
Text: Assembler Users Guide listed in the bibliography contains additional information on 80C196KB assembly , AP-466 APPLICATION NOTE Using the 80C196KB ROBIN SHEER EMD APPLICATIONS November 1991 , or call 1-800-879-4683 COPYRIGHT INTEL CORPORATION 1996 Using the 80C196KB CONTENTS PAGE , 41 41 Figure 7-3 Figure 7-4 PAGE 80C196KB Block Diagram Block Diagram of the Register , Register Descriptions Instruction Format The Program Status Word Register 80C196KB Interrupt Sources


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PDF AP-466 80C196KB 80C196KB 16-Bit AP-248 MCS-96 iC-96 MCS-96 Macro Assembler Users guide MCS-96 Users guide 80C196KB instruction set 74164 counter MCS-96 development intel asm-96 122350 270646 80c196KB users
1996 - 80C196KB

Abstract: MCS-96 Macro Assembler Users guide AN80C196KB 87C196kc users guide MCS-51 Macro Assembler Users Guide mcs 96 programming intel 80c196kb INSTRUCTION SET 80C196KB Programmers Manual 80c196KB instruction set 80c196KB users
Text: 80C196KB User's Guide November 1990 Order Number 270651-003 Information in this document , 60056-7641 or call 1-800-879-4683 COPYRIGHT INTEL CORPORATION 1996 80C196KB USER'S GUIDE CONTENTS , 3 3 Program Status Word 3 4 Instruction Set 3 5 80C196KB Instruction Set Additions and , 31 31 32 53 53 54 58 80C196KB USER'S GUIDE CONTENTS 12 0 I O PORTS 12 1 Input Ports , 92 93 94 80C196KB USER'S GUIDE The 80C196KB family is a CHMOS branch of the MCS -96 family


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PDF 80C196KB 87C196KB 87C196KB 80C196KB MCS-96 Macro Assembler Users guide AN80C196KB 87C196kc users guide MCS-51 Macro Assembler Users Guide mcs 96 programming intel 80c196kb INSTRUCTION SET 80C196KB Programmers Manual 80c196KB instruction set 80c196KB users
1995 - 8XC196KC Users manual

Abstract: 8XC196KC/KD complete users manual 80C196KB 80c196KB users MCS-96 ApBUILDER mcs 96 programming 272238 C196 EI 96 magnetic
Text: AD_TIME is omitted because we will be using the 80C196KB -compatible mode for simplicity. Bits 0-4 are , , please see pages C-11 and C-12 of the 8XC196KC/KD Users Manual. IOC2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 , bit 3 holds a 1 then AD_TIME is used, otherwise the 80C196KB compatible mode is used. The 80C196KB , 80C196KB compatible mode. Bit 4 controls the clock prescaler. If bit 4 holds a 1 then a conversion using the 80C196KB compatible mode will take 89.5 state times*. If a 0 is loaded into bit 4 the conversion


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PDF 8XC196KC/KD 8XC196KC/KD 80c196kd 8XC196KC Users manual 8XC196KC/KD complete users manual 80C196KB 80c196KB users MCS-96 ApBUILDER mcs 96 programming 272238 C196 EI 96 magnetic
1996 - heds 5310

Abstract: PID control rc servo pid for line following robot 80C196KB AN80C196KB robot arm circuit diagram and code using assembly language ENCODER OPTICAL 5310 ac motor speed control circuit diagram "dc servo motor" PITTMAN encoder
Text: AP-428 APPLICATION NOTE Distributed Motor Control Using the 80C196KB TIM SCHAFER MICHAEL CHEVALIER 80C196KB APPLICATIONS December 1993 Order Number 270701-001 Information in this , 1996 DISTRIBUTED MOTOR CONTROL USING THE 80C196KB CONTENTS PAGE 1 0 INTRODUCTION 1 , back to a central controller The 80C196KB high performance microcontroller provides a low cost solution for handling these required control tasks The 80C196KB microcontroller is a highly integrated and


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PDF AP-428 80C196KB 80C196KB heds 5310 PID control rc servo pid for line following robot AN80C196KB robot arm circuit diagram and code using assembly language ENCODER OPTICAL 5310 ac motor speed control circuit diagram "dc servo motor" PITTMAN encoder
80c196KB instruction set

Abstract: 8096 microcontroller 80C196KB
Text: : 270679-004 AUTOMOTIVE 80C196KB /83C196KB PRODUCT DESIGNATION PRODUCT FAMILY CHMOS TECHNOLOGY PROGRAM , using the new interrupts and registers) AUTOMOTIVE 80C196KB /83C196KB IDLPD CM PL BMOV , PREILDBfilDIM Diff AUTOMOTIVE 80C196KB /83C196KB PLCC and CERQUAO 9 8 7 6 5 4 3 2 1 68 67 66 , Hfl2bl7b OOfiblHfl 575 ■ITL2 6-47 AUTOMOTIVE 80C196KB /83C196KB PIN DESCRIPTIONS Name and , AUTOMOTIVE 80C196KB /83C196KB PIN DESCRIPTIONS (Continued) Symbol Name and Function RD Read


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PDF 80C196 KB/83C196 16-BIT 16-Bit 10-Bit 8XC196KB 80c196KB instruction set 8096 microcontroller 80C196KB
R87c196

Abstract: No abstract text available
Text: – IPKUyiüfflOMÄKy T - 4 9 - l% jÇ > 87C196KB/83C196KB/ 80C196KB 16-BIT HIGH PERFORMANCE CHMOS , 80C196KB — ROMIess m 8 Kbytes of On-Chip EPROM Full Duplex Serial Port ■232 Byte Register , -Bit or 16-Bit Buswidth The 80C196KB 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller family. The 80C196KB is compatible with the 8Q96BH and uses a true superset of , Powerdown Mode. The 80C196KB has a 232-byte register file and an optional 8 Kbyte of on-chip ROM or EPROM


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PDF 40Sbl 87C196KB/83C196KB/80C196KB 16-BIT 87C196KB 83C196KB 80C196KB Sources/16 R87c196
8096 microcontroller

Abstract: temperature controller using 8096 80C196KA 16 bit 8096 microcontroller interrupt mc1791 8096 microcontroller block diagram 8096 microcontroller serial ports 16 bit 8096 microcontroller architecture 8096 pin diagram NB3C
Text: \ _/ 270679-5 HOLD/HLDA Timings Symbol Description Min Max Units Notes Thvch HOLD Setup 80C196KB , thalaz HLDA Low to Address Float 80C196KB 83C196KB 15 20 ns Thalbz HLDA Low to BHE, INST, RD, WR Float , Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following problems. 1. The HSI unit has two , incorrect. TechBit (MC1791). (B-step only.) DIFFERENCES BETWEEN THE 80C196KA AND THE 80C196KB The 8XC196KB , 80C196KB instead of low as on the 80C196KA. 2. The DJNZW instruction is not guaranteed to work on the


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PDF 8XC196KB 16-BIT 10-Bit 8/16-Bit 8096 microcontroller temperature controller using 8096 80C196KA 16 bit 8096 microcontroller interrupt mc1791 8096 microcontroller block diagram 8096 microcontroller serial ports 16 bit 8096 microcontroller architecture 8096 pin diagram NB3C
1996 - 16 bit 8096 microcontroller architecture

Abstract: 8096 microcontroller architecture 8096 MICROCONTROLLER ADDRESSING MODES 8096 microcontroller 80C196KB 16 bit 8096 microcontroller interrupt 8096 microcontroller block diagram 8096 hsi hso unit 8096 microcontroller features 8096 microcontroller TIMER
Text: Buswidth Timing 270679 ­ 5 HOLD HLDA Timings Symbol THVCH Description HOLD Setup 80C196KB , Float 80C196KB 83C196KB 15 20 ns THALBZ HLDA Low to BHE INST RD WR Float ns TCLHAH , Multiplexer Break-Before-Make Guaranteed 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following , the stack pointer (SP) work differently on the 80C196KB than on the 8096BH On the 8096BH the address is calculated based on the un-updated version of the stack pointer The 80C196KB uses the updated


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PDF 8XC196KB 16-BIT 16-Bit 10-Bit 16 bit 8096 microcontroller architecture 8096 microcontroller architecture 8096 MICROCONTROLLER ADDRESSING MODES 8096 microcontroller 80C196KB 16 bit 8096 microcontroller interrupt 8096 microcontroller block diagram 8096 hsi hso unit 8096 microcontroller features 8096 microcontroller TIMER
8096 microcontroller

Abstract: 8096 microcontroller architecture 8096
Text: \ _ r HOLD/HLDA Timings Symbol T hvch Description HOLD Setup 80C196KB 83C196KB CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float 80C196KB 83C196KB HLDA Low to BHE, INST, RD , . 4. Multiplexer Break-Before-Make Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the , 80C196KB than on the 8096BH. On the 8096BH, the address is calculated based on the un-updated version of the stack pointer. The 80C196KB uses the updated version. The offset for POP[SP] and POP nn[SP


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PDF 8XC196KB 16-BIT 10-Bit 8096 microcontroller 8096 microcontroller architecture 8096
83C196KB12

Abstract: 80C196KB12 N80C196KB 80C196KB-12 S3C196KB 80C196KB10 270918 qsc60
Text: S3C196KB - 8 Kbytes of Factory Mask-Programmed ROM 80C196KB - ROMIess 8 Kbytes of On-Chip ROM Available , MHz and 12 MHz Available Extended Burn-In Available The 80C196KB 16-bit microcontroller is a high performance member of the MCS® 96 microcontroller family. The 80C196KB is compatible with the 8096BH and uses , placed into Idle or Powerdown Mode. The 80C196KB has a 232-byte register file and an optional 8 Kbyte of on-chip ROM. Bit, byte, word and some 32-bit operations are available on the 80C196KB . With a 12 MHz


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PDF 80C196KB10/83C196KB10/80C196KB12/83C196 S3C196KB 80C196KB Sources/16 16-Bit 10-Bit 83C196KB12 80C196KB12 N80C196KB 80C196KB-12 80C196KB10 270918 qsc60
Not Available

Abstract: No abstract text available
Text: /HLDA Timings Symbol T hvch Description HOLD Setup 80C196KB 83C196KB Min Max Units 1 , BREQ Low -1 5 15 ns T halaz HLDA Low to Address Float 80C196KB 83C196KB 15 20 , ; 333 ns @ 6 MHz. 4. Multiplexer Break-Before-Make Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following problems. 1. The HSI unit has two errata; one dealing with res­ olution and , incorrect. TechBIt (MC1791). (B-step only.) DIFFERENCES BETWEEN THE 80C196KA AND THE 80C196KB The


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PDF 8XC196KB 16-BIT 10-Bit 16-Bit 16-Bi1
n80c196kb

Abstract: 80C196KB instruction set
Text: 83C196KB — 8 Kbytes of Factory Mask-Programmed ROM 80C196KB — ROMIess ■8 Kbytes of On-Chip ROM , 80C196KB 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller family. The 80C196KB is compatible with the 8096BH and uses a true superset of the 8096BH instructions. Intel’s , power requirements, the processor can be placed into Idle or Powerdown Mode. The 80C196KB has a 232 , available on the 80C196KB . With a 12 MHz oscillator a 16-bit addition takes 0.66 (is, and the instruction


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PDF 80C196KB10 196KB10 196KB12 196KB12 83C196KB 80C196KB 16-Bit Sources/16 n80c196kb 80C196KB instruction set
8096 microcontroller

Abstract: p46ad 8096 serial peripheral in 8096 p31ad P45AD
Text: 270679-5 HOLD/HLDA Timings Symbol T hvch Inscription HOLD Setup 80C196KB 83C196KB CLKOUT Low to HLDA Low CLKOUT Low to B EEQ Low HLDA Low to Address Float 80C196KB 83C196KB HLDA Low to BH E, INST, RD , Break-Before-Make Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following problems. 1. The HSI , the stack pointer (SP) work differently on the 80C196KB than on the 8096BH. On the 8096BH, the address is calculated based on the un-updated version of the stack pointer. The 80C196KB uses the updated


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PDF 8XC196KB 16-BIT 10-Bit 8/16-Blt 16-Blt 8096 microcontroller p46ad 8096 serial peripheral in 8096 p31ad P45AD
16 bit 8096 microcontroller interrupt

Abstract: 8096 microcontroller 8096 MICROCONTROLLER ADDRESSING MODES
Text: Symbol Thvch Description HOLD Setup 80C196KB 83C196KB CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float 80C196KB 83C196KB HLDA Low to BHE, INST, RD, WR Float CLKOUT Low to HLDA High , Break-Before-Make Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following problems. 1. The HSI , ) work differently on the 80C196KB than on the 8096BH. On the 8096BH, the address is calculated based on the un-updated version of the stack pointer. The 80C196KB uses the updated version. The offset for POP


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PDF 8XC196KB 16-BIT 10-Bit 16 bit 8096 microcontroller interrupt 8096 microcontroller 8096 MICROCONTROLLER ADDRESSING MODES
8096 microcontroller

Abstract: 8096 MICROCONTROLLER ADDRESSING MODES QSC family 80C196KA intel 8096 instruction set addressing modes mc1791
Text: -\ _ / - HOLD/HIDÂ Timings Symbol T hvch Description HOLD Setup 80C196KB 83C196KB CLKOUT Low to HLDA Low CLKOUT Low to BRFÜ Low HLDA Low to Address Float 80C196KB 83C196KB HLDA Low to BHE, INST , Break-Before-Make Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following problems. 1. The HSi , and indirect operations relative to the stack pointer (SP) work differently on the 80C196KB than on , pointer. The 80C196KB uses the updated version. The offset for POP[SP] and POP nn[SP] instructions may


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PDF 8XC196KB 16-BIT 10-Bit 8/16-Blt 16-Blt 8096 microcontroller 8096 MICROCONTROLLER ADDRESSING MODES QSC family 80C196KA intel 8096 instruction set addressing modes mc1791
2004 - 8096 microcontroller

Abstract: 8096 MICROCONTROLLER ADDRESSING MODES 270679 MC1791 serial peripheral in 8096
Text: /HLDA Timings Symbol THVCH HOLD Setup 80C196KB 83C196KB CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float 80C196KB 83C196KB HLDA Low to BHE, INST, RD, WR Float CLKOUT Low to HLDA High , Break-Before-Make Guaranteed. 80C196KB FUNCTIONAL DEVIATIONS The 80C196KB has the following problems. 1. The , differently on the 80C196KB than on the 8096BH. On the 8096BH, the address is calculated based on the un-updated version of the stack pointer. The 80C196KB uses the updated version. The offset for POP SP and POP


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PDF 8XC196KB 16-BIT 10-Bit 8/16-Bit 8096 microcontroller 8096 MICROCONTROLLER ADDRESSING MODES 270679 MC1791 serial peripheral in 8096
27-0780-00

Abstract: No abstract text available
Text: Mask-Program m ed ROM 80C196KB — ROMIess ■8 Kbytes of On-Chip ROM Available Full Duplex Serial Port , -Bit Buswidth Extended Burn-In Available ■Extended Tem perature Available The 80C196KB 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller family. The 80C196KB is compatible , processor can be placed into Idle or Powerdown Mode. The 80C196KB has a 232-byte register file and an optional 8 Kbyte of on-chip ROM. Bit, byte, word and some 32-bit operations are available on the 80C196KB


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PDF C196KB10/83C196KB10/80C196KB12/83C196KB12 83C196KB 80C196KB 16-Bit 10-Bit 196KB 83C196KB/80C196KB 27-0780-00
80C196KB

Abstract: 80C196KC 8XC196KC instruction set a0041 A0039-A0 80196KB 8XC196KB 2002H 8XC196KC/KD 80C196KC Users Guide
Text: accuracy. The sample and convert times either default to a predefined 80C196KB -compatible mode or are specified in the ADJTIME register. Clearing the AD_TIME_ENA bit (IOC2.3) enables an 80C196KB -compatible conversion. In the 80C196KB -compatible mode, the AD_FAST bit (IOC2.4) controls the sample and convert times. The 80C196KB slow mode uses 15 state times for the sample time and a total of 158 state times for the entire conversion. The 80C196KB fast mode uses eight state times for the sample time and a total of 91


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PDF A0139-C0 10-bit A0085-A0 80C196KB 80C196KC 8XC196KC instruction set a0041 A0039-A0 80196KB 8XC196KB 2002H 8XC196KC/KD 80C196KC Users Guide
272120

Abstract: No abstract text available
Text: programmable) and a high performance member of (he MCS®-96 microcontroller family. The 80C196KB has the same peripheral set as the 8096BH; furthermore, the 80C196KB has a true superset of the 8096BH instructions. Intel , document, the device will be referred to as 80C196KB . Bit, byte, word and some 32-bit operations are available on the 80C196KB . With a 16 MHz oscillator a 16-bit addition takes 0.50 fis, and the instruction , 80C196KB also refer to the 80C196KB16, 83C196KB16, 83C196KB16, 87C196KB and 87C196KB16 unless otherwise


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PDF 8XC196KB/8XC196KB16 Sources/16 16-Bit 15-Bit 8XC196KB 80C196KB 8096BH; 8096BH 272120
1996 - 80c196kb16

Abstract: 80c196kb12 80C198 83C196KB12 80C196kd user guide 80C196KB 80c196KB users 80C198-16 87C196KB16 8XC196KB
Text: Embedded Microcontrollers 270646 80C196KB User's Guide 270651 8XC196KB/KC/KD Programming , 8EC196KB B-3 P645 80C196KB QDF or S-Spec number N/A End of lifed 87C196KB A-2 P624 , Production 12 80C196KB16 End of lifed E 12,16 80C196KB 87C196KBS B,D 16 , 80C196KB 12 80C196KB16 16 83C196KB,Rn 12,16 83C196KB16,Rn 16 Note: The change , in the following chart: Top Side Marking Stepping Change Indicator 80C196KB , 83C196KB


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PDF 8XC196KB 8XC196KB 80C196KB 80c196kb16 80c196kb12 80C198 83C196KB12 80C196kd user guide 80c196KB users 80C198-16 87C196KB16
Not Available

Abstract: No abstract text available
Text: 80C196KB10/83C196KB10/80C196KB12/83C196KB12 PACKAGING The 80C196KB is available in a 68 , tied low for the 80C196KB ROMIess device. ALE/ADV Address Latch Enable or Address Valid output , shared with other functions in the 80C196KB . Ports 3 and 4 8-bit bidirectional I/O ports with open , must meet these specifications to work with the 80C196KB : Ta VYV t llyv T ylyh Min Max , fall times = 10 ns, Fosc = 10/12 MHz The 80C196KB will meet these specifications: Symbol FXTAL


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PDF C196KB10/83C196KB10/80C196KB12/83C196KB12 80C196KB 68-pin 80-pin OrdKB/80C196KB 4fl2bl75
1996 - 80C196KB

Abstract: MC0893 80C196KB16 87C196KB16 83C196KB intel packaging handbook 240800 INTEL Packaging Handbook 8XC196KB 8XC196KB16 P629
Text: varieties ROMless ( 80C196KB ) 8K ROM (83C196KB) and 8K OTP (One Time Programmable 87C196KB) The 8XC196KB is , on the 80C196KB With a 16 MHz oscillator a 16-bit addition takes 0 50 ms and the instruction times , The 8XC196KB16 has a maximum guaranteed frequency of 16 MHz All references to the 80C196KB also refer , PALE PMODE n and PROG The ROMless ( 80C196KB ) doesn't use any of the programming pins 4 8XC196KB , n and PROG The ROMless ( 80C196KB ) doesn't use any of the programming pins 5 8XC196KB


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PDF 8XC196KB 8XC196KB16 16-Bit 10-Bit 80C196KB MC0893 80C196KB16 87C196KB16 83C196KB intel packaging handbook 240800 INTEL Packaging Handbook 8XC196KB16 P629
1997 - psd301 programming

Abstract: intel 80C196kb psd3xx 8254 intel microprocessor block diagram PSD301 8250 uart intel 80C196KB Intel UART 8250 CS10 68HC11
Text: 80C196KB INTERNAL RESOURCE ­ 16 - 18K PSD3XX ­ Application Note 014 Application Examples (Cont , states for the slower resources. For this example, we will use an Intel 80C196KB microcontroller running , . The circuit used to implement this function is illustrated in Figure 8. The 80C196KB is directly , active high, so ALE is inverted using PAD B and sent out through Port C. Though the 80C196KB can be , clock must be inverted since the 80C196KB uses the falling edge of the clock to sample the READY input


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PDF PSD301 psd301 programming intel 80C196kb psd3xx 8254 intel microprocessor block diagram 8250 uart intel 80C196KB Intel UART 8250 CS10 68HC11
Not Available

Abstract: No abstract text available
Text: available in three different memory varieties: ROMIess ( 80C196KB ), 8K ROM (83C196KB) and 8K OTP (One Time , . Bit, byte, word and some 32-bit operations are available on the 80C196KB . With a 16 MHz oscillator a , ­ teed frequency of 16 MHz. All references to the 80C196KB also refer to the 80C196KB16; 83C196KB, Rxxx , only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMIess ( 80C196KB ) doesn’t use any of , : AINC, PALE, PMODE.n, and PROG. The ROMIess ( 80C196KB ) doesn’t use any of the programming pins. P


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PDF 8XC196KB/8XC196KB16 16-Bit Sources/16 10-Bit
1996 - MCS-96

Abstract: 80c196kb16 83C196KB 80C198 196-KB 270651-003 mcs96 intel Intel 80c196KB errata intel DOC 87C196KB
Text: Documents/Related Documents Title 80C196KB User's Guide 8XC196KB Advanced 16-bit CHMOS Microcontroller , S-spec number 80C196KB QDF or S-spec number MHz Change Indicator (3) Status N/A End of , ) 83C196KBS C-1 87C196KBS C-1 83C196KBS C-1 MHz 80C198 83C198,Rn P629.0 80C196KB 80C196KB16 83C196KB,Rn 16 12,16 12 16 12,16 87C198 P629.0 87C196KB 87C196KB16 80C198 83C198,Rn 80C196KB , conjunction with the 80C196KB User's Guide (270651-003). Vcc Vcc (1) D1 (2) R D2 4.7 k


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PDF 8XC196KB 8XC196KB \specupdt\source\mcs96\196kb\auto\272970 80C196KB MCS-96 80c196kb16 83C196KB 80C198 196-KB 270651-003 mcs96 intel Intel 80c196KB errata intel DOC 87C196KB
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