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A80960CA-33 Intel Corporation Bristol Electronics 10 - -
A80960CA25 Intel Corporation ComS.I.T. 11 - -
A80960CA33 Intel Corporation Bristol Electronics 26 - -
KU80960CA16 Intel Corporation ComS.I.T. 25 - -
KU80960CA16 Intel Corporation Chip One Exchange 29 - -
KU80960CA25 Intel Corporation Rochester Electronics 969 $54.48 $44.27
KU80960CA25 Intel Corporation Bristol Electronics 200 - -
TA80960CA25 Intel Corporation Rochester Electronics 109 $327.60 $266.18
VA80960CA16 Intel Corporation Rochester Electronics 4,634 $156.87 $127.46
VA80960CA25 Intel Corporation Rochester Electronics 3,544 $209.96 $170.59

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80960CA datasheet (5)

Part Manufacturer Description Type PDF
80960CA-16 Intel 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR Original PDF
80960CA-16 Intel Processor, 32-Bit HIGH-PERFORMANCE EMBEDDED PROCESSOR Original PDF
80960CA-25 Intel 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR Original PDF
80960CA-25 Intel Processor, 32-Bit HIGH-PERFORMANCE EMBEDDED PROCESSOR Original PDF
80960CA-33 Intel 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR Original PDF

80960CA Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - VA80960CA25

Abstract: 80960CA i960 Cx Instruction Set Quick Reference a2610 A20A 80960CF intel DOC 80960CA-33 i960 Cx Processor Instruction Set Quick Reference VA80960CA-25
Text: D-Stepping KU 80960CA -25 KU 80960CA -16 SV914 SV913 SW033 SW032 D2 D2 A 80960CA-33 A 80960CA-25 A 80960CA-16 TA 80960CA-16 SV908 SV907 SV906 SW031 SW030 SW029 SW147 D2 D2 D2 , application to workaround this errata for the 80960CA. Intel will also provide switches for the development , 80960CA /CF SPECIFICATION UPDATE Release Date: June, 1997 Order Number: 272875-002 The 80960CA /CF may contain design defects or errors known as errata which may cause the 80960CA /CF to deviate


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PDF 80960CA/CF 80960CA/CF VA80960CA25 80960CA i960 Cx Instruction Set Quick Reference a2610 A20A 80960CF intel DOC 80960CA-33 i960 Cx Processor Instruction Set Quick Reference VA80960CA-25
Not Available

Abstract: No abstract text available
Text: a quick, global view of software and hardware design considerations for the 80960CA. For further , tech­ nical information and examples for designing em­ bedded systems using the 80960CA. — The , the low latency and high throughput interrupt service featured by the 80960CA. The interrupt latency , (Figure 3-1) refers to the resources which are available for executing code on the 80960CA. The , with on-chip peripherals. These SFR’s are an architectural extension specific to the 80960CA. The


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PDF 80960CA 32-Bit 80960CA 80960CAâ 00000000H 000003FFH.
Not Available

Abstract: No abstract text available
Text: 80960CA-25 , -16 2.5 Instruction Set Summary Table 1 summarizes the 80960CA instruction set by logical , valid output SPECIAL ENVIRONMENT 80960CA-25 , -16 ■m e 1® Table 3 . 80960CA Pin Descriptionâ , 80960CA-25 , -16 in te i Table 4 . 80960CA Pin Description— Processor Control Signals Name Type , 4ñ2bl?5 GlbRBfil SQb ■SPECIAL ENVIRONMENT 80960CA-25 , -16 Table 4 . 80960CA Pin Descriptionâ , lblBÔ S 442 2-13 SPECIAL ENVIRONMENT 80960CA-25 , -16 Table 5 . 80960CA Pin Descriptionâ


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PDF 80960CA-25, 32-BIT 64-bit 4ft2bl75
Not Available

Abstract: No abstract text available
Text: SPECIAL ENVIRONMENT 80960CA-25 , -16 2.5 Instruction Set Summary Table 1 summarizes the 80960CA , SPECIAL ENVIRONMENT 80960CA-25 , -16 irrtel Table 3 . 80960CA Pin Description— External , ENVIRONMENT 80960CA-25 , -16 Table 3 . 80960CA Pin Description—External Bus Signals (Continued) Name , ENVIRONMENT 80960CA-25 , -16 the component (i.e., pins facing down). Figure 3 shows the complete 80960CA , ENVIRONMENT 80960CA-25 , -16 Table 7 . 80960CA PGA Pinout—In Pin Order Pin Signal Pin Signal


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PDF 80960CA-25, 32-BIT 64-bit
1998 - i960 Cx Instruction Set Quick Reference

Abstract: i960 Cx Processor Instruction Set Quick Reference 80960CA de sw033 SV908 SW147 A20A 80960CF-40 80960CF 80960CA-33
Text: x 80960CA -25 SV914 SW033 D2 x 80960CA -16 SV913 SW032 D2 x 80960CA-33 SV908 SW031 D2 x 80960CA-25 SV907 SW030 D2 x 80960CA-16 SV906 SW029 D2 x 80960CA-16 SW147 x80960CA-16 1 NOTES: 1. x80960CA16,S W147 will no longer be offered , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , document are now indicated with an "x". 80960CA /CF Processor Specification Update 5 Preface


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PDF 80960Cx 80960CA/CF i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference 80960CA de sw033 SV908 SW147 A20A 80960CF-40 80960CF 80960CA-33
1993 - 80960CA-33

Abstract: ALI 3105 80960CA 80960CA-25 FCX-03
Text: Four-Channel DMA Controller F_CX001A Figure 1. 80960CA Block Diagram 1 80960CA-33 , -25, -16 2.1 , while the processor is in the ONCE mode. 4 80960CA-33 , -25, -16 Table 3. 80960CA Pin , . 80960CA-33 , -25, -16 Table 3. 80960CA Pin Description - External Bus Signals (Sheet 3 of 3) Type , structures from non-supervisor requests. 7 80960CA-33 , -25, -16 Table 4. 80960CA Pin Description - , installed processor transparent in the board. 8 80960CA-33 , -25, -16 Table 4. 80960CA Pin


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PDF 80960CA-33, 32-BIT 64-bit 80960CA 80960CA and18 80960CA-33 ALI 3105 80960CA-25 FCX-03
1996 - 80960CA

Abstract: No abstract text available
Text: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060 FLASH EPROM READ ( 80960CA ), 1 WORD [PRD , 200ns PCI9060 FLASH EPROM WRITE ( 80960CA ), 1 WORD [PWR_960.TD] (07/12/94) STATE A 3 2 , STATE 100ns 200ns 300ns PCI9060 STATIC RAM READ ( 80960CA ), 4 WORDS, WITH WAIT STATES [SRDW , STATIC RAM READ ( 80960CA ), 4 WORDS, NO WAIT STATES [SRD_960.TD] (07/18/94) A D D D D A , RAM WRITE ( 80960CA ), 4 WORDS, WITH WAIT STATES [SWRW_960.TD] (07/18/94) A 1 D 1 1 D


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PDF 100ns 150ns 200ns PCI9060 80960CA) PCLK1-33 80960CA
1998 - va80960ca25

Abstract: va80960 de sw033 80960CA 80960CF 80960CF-40 A20A
Text: SW032 D2 A 80960CA-33 SV908 SW031 D2 A 80960CA-25 SV907 SW030 D2 A 80960CA-16 SV906 SW029 D2 SW147 VA80960CA-161 TA 80960CA-16 NOTE: 1. TA80960CA16,S W147 , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , document. It contains all identified errata published prior to this date. 80960CA /CF Processor , 80960CA 32-Bit High-Performance Embedded Processor datasheet 270727 80960CF-40, -33, -25, -16 32


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PDF 80960Cx 80960CA/CF va80960ca25 va80960 de sw033 80960CA 80960CF 80960CF-40 A20A
1996 - VA80960CA-16

Abstract: VA80960CA25 80960CA VA80960CA16 va80960 272875 A20A 80960CF Multi-Channel DMA Controller i960 Cx Instruction Set Quick Reference
Text: SW032 D2 A 80960CA-33 SV908 SW031 D2 A 80960CA-25 SV907 SW030 D2 A 80960CA-16 SV906 SW029 D2 SW147 VA80960CA-16* TA 80960CA-16 * TA80960CA16,S W147 will no , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , 80960CA /CF SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272875-001 The 80960CA , 80960CA /CF's behavior to deviate from published specifications are documented in this specification


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PDF 80960CA/CF 80960CA/CF VA80960CA-16 VA80960CA25 80960CA VA80960CA16 va80960 272875 A20A 80960CF Multi-Channel DMA Controller i960 Cx Instruction Set Quick Reference
cl-001

Abstract: 85C508 Intel 85C508 80960CA 27960CX intel PLD
Text: interface to the 80960CA's bus. It operates in pipelined or non-pipelined modes. Internally, the 27960CX is , example illustrates 8-, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs offer a simple , is required. With the 80960CA's maximum valid address delay of 14 ns at 33 MHz, 9 ns remains for 55 , Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function â


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PDF 27960CX 80960CA 80960CA 111-E 27960CX cl-001 85C508 Intel 85C508 intel PLD
Not Available

Abstract: No abstract text available
Text: Wfwl HEW LETT m PACKARD LrJk H P E2432A Intel 80960CA /CF Preprocessor Interface For use with HP logic analyzers The HP E2432A preprocessor interface for the Intel 80960CA /CF is a mechani­ cal and electrical interface between the Intel 80960CA /CF and various HP logic analyzers for , : Intel 80960CA /CF, 40-MHz, 168-pin PGA Capabilities: •The 80960CA /CF microproces­ sor can operate , can be used to measure the duration of these transactions. •The 80960CA bus is configurable in 16


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PDF E2432A 80960CA/CF E2432A 80960CA/CF ca-9430 Ltd3-29-21 5091-5665E
intel PLD

Abstract: No abstract text available
Text: the 80960CA's bus. It operates in pipe lined or non-pipelined modes. Internally, the 27960CX Is , to the 80960CA. The designs offer a simple "no-glue" interface. A non-buffered 27960CX system , minimum CS setup time of 7 ns (tsvCH) at 33 MHz is required. With the 80960CA's maximum valid ad; dress , Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Perform ance Clock to Data Out - Zero Wait State Data to Data Burst - Up to 33 MHz 80960CA Perform ance Asynch Microcontroller Reset


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PDF Sbl75 27960CX 80960CA 27960CX 01G1335 G1G1333 intel PLD
29023

Abstract: VXXXX 5204 eprom
Text: no-glue, synchronous burst interface to the 80960CA's bus. It operates in pipe lined or non-pipelined , 27960CX This example illustrates 8-, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs , setup time of 5 ns ( t s v C H ) at 33 MHz is 290236-8 required. With the 80960CA's maximum valid , Access No Glue Interface to 80960CA High Performance Clock to Data Out - Zero Wait State Data to Data Burst - Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function - Returns to Known


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PDF 27960CX 80960CA 27960CX 29023 VXXXX 5204 eprom
1993 - MCC68k

Abstract: mvme167 intel 1302 ROM amd 29030 80386 intel microprocessor qt960 SRAM 6114 29030 80960 KB 25 IDT 3081E
Text: 80960SA-16 80960SB-16 80960KA-25 80960KB-25 80960CA-33 80960CF-33 Figure 4. Intel i960 CPU , 1.00 0.54 0.00 80960SA-16 80960SB-16 80960KA-25 80960KB-25 80960CA-33 80960CF-33 , .11 Intel 80960CA vs. IDT R3051E, R3052E , . 15 Table 16. Intel 80960CA Default Optimization . 16 Table 17. Intel 80960CA Maximum Optimization


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PDF C5-233 i860TM EC680401 MCC68k mvme167 intel 1302 ROM amd 29030 80386 intel microprocessor qt960 SRAM 6114 29030 80960 KB 25 IDT 3081E
Not Available

Abstract: No abstract text available
Text: Figure 1. 80960CA Block Diagram 4fl2bl7S D l b b S n 573 1-157 80960CA-33 , -25, -16 2.1 , 80960CA-33 , -25,-16 2.5 Instruction Set Summ ary Table 1 summarizes the 80960CA instruction set by , 80960CA-33 , -25,-16 intei Table 3. 80960CA Pin Description — External Bus Signals Name A31:2 , 80960CA-33 , -25, -16 Table 3. 80960CA Pin Description — External Bus Signals (Continued) Name Type , agents. ■4fl5Lil?5 OlbL.524 R3G ■80960CA-33 , -25, -16 Table 3. 80960CA Pin Description


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PDF 80960CA-33, 32-BIT 64-bit 80960CA 80960CA and18
1998 - VA80960CA25

Abstract: i960 Cx Instruction Set Quick Reference SV914 80960CA 80960CF 80960CF-40 A20A 272875
Text: SW032 D2 A 80960CA-33 SV908 SW031 D2 A 80960CA-25 SV907 SW030 D2 A 80960CA-16 SV906 SW029 D2 SW147 VA80960CA-161 TA 80960CA-16 NOTE: 1. TA80960CA16,S W147 , prevent this code sequence in their application to workaround this errata for the 80960CA. Intel will , identified errata published prior to this date. 80960CA /CF Processor Specification Update 1 Preface , was not previously published. Affected Documents/Related Documents Title Order # 80960CA 32


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PDF 80960Cx 272220-002i 80960CA/CF VA80960CA25 i960 Cx Instruction Set Quick Reference SV914 80960CA 80960CF 80960CF-40 A20A 272875
1996 - 80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Text: Supply Voltage Parameter 80960CA-25 80960CA-16 4 50 4 50 5 50 5 50 V V fCLK2x Input Clock Frequency (2-x Mode) 80960CA-25 80960CA-16 0 0 50 32 MHz MHz fCLK1x Input Clock Frequency (1-x Mode) 80960CA-25 80960CA-16 8 8 25 16 MHz MHz TC Case , Table 11 Operating Conditions ( 80960CA-25 -16) Table 12 DC Characteristics Table 13 80960CA AC , 8 SPECIAL ENVIRONMENT 80960CA-25 -16 Table 3 80960CA Pin Description External Bus Signals


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PDF 80960CA-25 32-BIT 64-bit 128-bit 80960CA Non-Pipelined Single-Cycle processor 80960CA-16 270710
27960CX

Abstract: 80960CA 85C508 N27960CX 3A353
Text: , synchronous burst interface to the 80960CA's bus. It operates in pipelined or non-pipelined modes. Internally , -, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs offer a simple "no-glue" interface , is required. With the 80960CA's maximum valid address delay of 14 ns at 33 MHz, 9 ns remains for 55 V , Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out — Zero Wait State Data to Data Burst — Up to 33 MHz 80960CA Performance Asynch Microcontroller Reset Function — Returns to


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PDF 27960CX 80960CA 80960CA 27960CX 85C508 N27960CX 3A353
NRED 61

Abstract: HT21X
Text: . 80960CA Die Photo 3-167 October 1992 Order N um ber 270727-005 80960CA-33 , -25, -16 32-Bit High , CONTROLLER INTERRUPT Figure 2 . 80960CA Block Diagram 3-170 80960CA-33 , -25, -16 2.1. T h e , : Instructions marked by (*) are 80960CA extensions to the 80960 instruction set. 3-172 80960CA-33 , -25 , used. Figure 3. Example Pin Description Entry 3-173 80960CA-33 , -25, -16 Table 2 . 80960CA Pin , . The NXda wail states cannot be extended. 3-174 80960CA-33 , -25, -16 Table 2 . 80960CA Pin


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PDF 80960CA-33, 32-BIT 64-bit NRED 61 HT21X
270710

Abstract: CX041A
Text: ( ) R( - ) 4 80960CA-33 , -25, -16 Table 3. 80960CA Pin Description - External Bus Signals , effectively make an installed processor transparent in the board. 80960CA-33 , -25, -16 Table 4. 80960CA , . 10 80960CA-33 , -25, -16 3.3 3.3.1 80960CA Mechanical Data 80960CA PGA Pinout Tables 6 , Up) 14 80960CA-33 , -25, -16 3.3.2 80960CA PQFP Pinout See Section 4.0, ELECTRICAL , ^ 80960CA-33 , -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock


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PDF 80960CA-33, 32-BIT 64-bit 128-bit 80960C 270710 CX041A
29023

Abstract: No abstract text available
Text: the 80960CA's bus. It operates in pipe lined or non-pipelined modes. Internally, the 27960CX is , illustrates 8-, 16- and 32-bit wide burst access EPROM interfaces to the 80960CA. The de signs offer a simple " no-glue" interface to the 80960CA's bus. A non-buffered 27960CX burst EPROM system or ganized as , operation is required. With the 80960CA's maximum valid ad; dress delay of 18 ns at 33 MHz, 7 ns remains for , Synchronous 4 Byte Data Burst Access No Glue Interface to 80960CA High Performance Clock to Data Out Time -


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PDF 27960CX 80960CA 29023
Not Available

Abstract: No abstract text available
Text: 2 . 80960CA Block Diagram 3-197 intel 80960CA-33 , -25, -16 2.1. The C-Series Core â , states cannot be extended. 3-201 80960CA-33 , -25, -16 Table 2 . 80960CA Pin , resumed. 3-202 80960CA-33 , -25, -16 Table 2 . 80960CA Pin Description—External Bus Signals , H(Q) R(0) 3-203 80960CA-33 , -25, -16 Table 3 . 80960CA Pin Description—Processor Control , (falling) activated source. 3-205 I 3 80960CA-33 , -25, -16 3.3. 80960CA Pinout 3.3.1


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PDF 80960CA-33, 32-BIT 64-bit
Not Available

Abstract: No abstract text available
Text: non-supervisor requests. 1-206 OmiHTfi bbb 80960CA-33 , -25,-16 Table 4. 80960CA Pin Description â , ■80960CA-33 , -25, -16 Table 4. 80960CA Pin Description — Processor Control Signals , – 80960CA-33 , -25, -16 3.3 80960CA Mechanical Data 3.3.1 80960CA PGA Pinout Tables 6 and 7 list , 80960CA-33 , -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • • Two Instructions/Clock , -0 06 DmiMflfl 71? 80960CA-33 , -25, -16 80960CA-33 , -25, -16 32-BIT HIGH-PERFORMANCE


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PDF 80960CA-33, 32-BIT 64-bit 80960CA 80960CA
29023

Abstract: No abstract text available
Text: Architecture The 27960CX provides a no-glue, synchronous burst interface to the 80960CA's bus. It operates in , -, 16- and 32-bit wide 27960CX interfaces to the 80960CA. The designs offer a simple "no-glue" interface , minimum £ 3 setup time of 5 ns (tsvcH> a* 33 MHz is required. With the 80960CA's maximum valid ad dress , access. The 27960CX provides a no glue synchronous burst interface to the 80960CA bus. Internally the , bandwidth in 80960CA applications. An asynchronous m icrocontroller RESET feature puts the outputs in the


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PDF 27960CX 27960CX 29023
1995 - 47410

Abstract: Intel i960 benchmark 80960 EVALUATION PLATFORM dhrystone dhrystone intel 80960CF 80960CA 80960JD 80960JA 80960JF
Text: with a larger instruction cache - clearly distinguish it from the 80960CA. In the Stanford test suite , cache. The 80960JD core operates at a frequencey which is double that of the bus. The 80960CA features , Evaluation Board 40/20 MHz 00-1-00 128 Kbytes of 8 ns SRAM 80960CA /CF (DRAM & SRAM) TomCAt , . Benchmark Results - DRAM Benchmark Program 80960JA 80960CA 80960JF 80960JD 80960CF Notes , 80960JA 80960CA 80960JF 80960JD 80960CF 653271 57591 689271 884892 87998


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PDF 80960JA 80960JF 80960JD 80960CA 33MHz. 20MHz. 25MHz 80960JA, 47410 Intel i960 benchmark 80960 EVALUATION PLATFORM dhrystone dhrystone intel 80960CF
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