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74HCS74

Abstract: 78los 78 los d871 grid tie inverter 79L0B OP-07 inverter amplifier AD566 digital to analog converter interfacing with 8051 AD847
Text: CONVERT VJL/ START 78 LOS OUT ICS IN ONO y V» Figure 3. AD7885 Evaluation Board Circuit Diagram


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PDF AN-229 AD788516-Bit AD7885 16-bit R078B5 74HCS74 78los 78 los d871 grid tie inverter 79L0B OP-07 inverter amplifier AD566 digital to analog converter interfacing with 8051 AD847
2006 - MDIO clause 45

Abstract: remote control transmiter 78 los MDIO clause 45 specification remote transmiter TQFP-100 SCAN25100 SCAN12100TYA SCAN12100 AVDD33
Text: clock. (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V Receiver CPRI loss of signal ( LOS ) status (8-bit mode only). LVCMOS 0 = signal detected (per CPRI standard) 1 = signal lost , other pins, >2 kV CDM Hot plug protection LOS , LOF, 8b/10b line code violation, comma, and receiver , powered down and ROUT [9:0] as well as LOS , LOCKB, CDET, RXCLK, and SYSCLK are high impedance. 1 = , Duplicate of Register Address 3. 10 LOF RC CPRI Loss of Frame (LOF) counter. 11 LOS RC


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PDF SCAN12100 SCAN12100 MDIO clause 45 remote control transmiter 78 los MDIO clause 45 specification remote transmiter TQFP-100 SCAN25100 SCAN12100TYA AVDD33
2006 - MDIO clause 45

Abstract: AVDD33 SCAN25100 SCAN25100TYA TQFP-100 MDIO clause 45 specification
Text: low.) LINE STATUS 78 LOS O, LVTTL or 1.8V Receiver CPRI loss of signal ( LOS ) status (8 , protection LOS , LOF, 8b/10b line code violation, comma, and receiver PLL lock reporting Programmable , ) See " LOS Detection" under "Functional Description" for more details. 77 LOCKB O, LVTTL or , powered up. RXPWDNB 0 = Receiver is powered down and ROUT [9:0] as well as LOS , LOCKB, CDET, RXCLK, and


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PDF SCAN25100 SCAN25100 MDIO clause 45 AVDD33 SCAN25100TYA TQFP-100 MDIO clause 45 specification
2006 - Not Available

Abstract: No abstract text available
Text: . (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V LVCMOS Receiver CPRI loss of , €¢ • >8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV CDM Hot plug protection LOS , LOF , Control RIN r CDR Pattern Verifier Precision Delay Calibration Measurement JTAG LOS 2 DeEmphasis PLL Local Loop Back Input FIFO DIN [0:9] Link Status (Lock, LOS , LOF, etc , 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47


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PDF SCAN12100 SNLS245D SCAN12100 SCAN25100
2006 - Not Available

Abstract: No abstract text available
Text: . (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V LVCMOS Receiver CPRI loss of , kV on All Other Pins, >2 kV CDM Hot Plug Protection LOS , LOF, 8b/10b Line Code Violation, Comma , etc. MDIO Link Status (Lock, LOS , LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay , Control RIN r CDR Pattern Verifier Precision Delay Calibration Measurement JTAG LOS , 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87


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PDF SCAN25100 SNLS223C SCAN25100
2006 - Not Available

Abstract: No abstract text available
Text: . (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V LVCMOS Receiver CPRI loss of , kV on All Other Pins, >2 kV CDM Hot Plug Protection LOS , LOF, 8b/10b Line Code Violation, Comma , etc. MDIO Link Status (Lock, LOS , LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay , Control RIN r CDR Pattern Verifier Precision Delay Calibration Measurement JTAG LOS , 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87


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PDF SCAN25100 SNLS223C SCAN25100
Not Available

Abstract: No abstract text available
Text: clock. (OPMODE must be low.) LINE STATUS 78 LOS 0, LVTTL or 1.8V Receiver CPRI loss of signal ( LOS ) status (8-bit mode only). LVCMOS a 0 = signal detected (per CPRI standard) 1 = signal lost , , >7 kV on all other pins, >2 kV CDM B Hot plug protection B LOS , LOF, 8b/10b line code violation , C C C C C c e c e c C D i IOVDD LOCKB LOS 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 , powered down and ROUT [9:0] as well as LOS , LOCKB, CDET, RXCLK, and SYSCLKare high impedance. 1 =


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PDF SCAN12100 SNLS245D SCAN12100 I7nl200ps
2008 - BTS 5010

Abstract: MDIO clause 45 SCAN25100 SCAN25100TYA TQFP-100 AVDD33 ask transmiter 78 los 802.3ae MDIO remote transmiter
Text: connected to REFCLKP & REFCLKN. 30.72 MHz output clock. (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V Receiver CPRI loss of signal ( LOS ) status (8-bit mode only). LVCMOS 0 = signal detected (per CPRI standard) 1 = signal lost (per CPRI standard) See " LOS Detection" under "Functional , Hot plug protection LOS , LOF, 8b/10b line code violation, comma, and receiver PLL lock reporting , powered down and ROUT [9:0] as well as LOS , LOCKB, CDET, RXCLK, and SYSCLK are high impedance. 1 =


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PDF SCAN25100 SCAN25100 BTS 5010 MDIO clause 45 SCAN25100TYA TQFP-100 AVDD33 ask transmiter 78 los 802.3ae MDIO remote transmiter
2008 - MDIO clause 45

Abstract: SCAN25100 K28-1 remote transmiter NSC crystal 30.72MHz SCAN12100TYA remote control rx tx TQFP-100 AVDD33 MDIO clause 45 specification
Text: . 30.72 MHz output clock. (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V Receiver CPRI loss of signal ( LOS ) status (8-bit mode only). LVCMOS 0 = signal detected (per CPRI standard) 1 = signal lost (per CPRI standard) See " LOS Detection" under "Functional Description" for more , kV on all other pins, >2 kV CDM Hot plug protection LOS , LOF, 8b/10b line code violation, comma , ROUT [9:0] as well as LOS , LOCKB, CDET, RXCLK, and SYSCLK are high impedance. 1 = Receiver is powered


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PDF SCAN12100 SCAN12100 MDIO clause 45 SCAN25100 K28-1 remote transmiter NSC crystal 30.72MHz SCAN12100TYA remote control rx tx TQFP-100 AVDD33 MDIO clause 45 specification
2005 - WJLXT384E B1

Abstract: FLLXT384BE WJLXT384LE.B1 WJLXT384E LXT384BE B1 FLLXT384 248994 945 INTEL CIRCUIT DIAGRAM LXT384BE DJLXT384LE
Text: Remote Loopback Register, RLOOP - 02h . 78 TAOS Enable Register, TAOS - 03h . 78 LOS Status Monitor Register, LOS - 04h . 79 DFM , line encoder/decoder LOS per ITU G.775, T1.231, and ETS 300 233 Diagnostics: - Can be configured for G , . 78 9.0 JTAG Boundary Scan


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PDF LXT384 048-MHz WJLXT384E B1 FLLXT384BE WJLXT384LE.B1 WJLXT384E LXT384BE B1 FLLXT384 248994 945 INTEL CIRCUIT DIAGRAM LXT384BE DJLXT384LE
Not Available

Abstract: No abstract text available
Text: clock. (OPMODE must be low.) LINE STATUS 78 LOS 0, LVTTL or 1.8V Receiver CPRI loss of signal , >8 kV ESD on the CML 10, >7 kV on all other pins, >2 kV CDM B Hot plug protection B LOS , LOF, 8b , Pin Control Link Status (Lock, LOS , LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay , |_ I- 1 I JTAG I Precision Delay Calibration Measurement LOS ~2008 National , 77 LOS ]l CDET 49 IOVDD GND 48 GND 47 S C A N 25100 AVDD18 VSEL


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PDF LS223B SCAN25100 I7nl200ps SCAN25100
2014 - Not Available

Abstract: No abstract text available
Text: Deassert level 78 LOS High Level Setting SET_LOS[6:0] = 101d Assert level 121 Deassert , incorporates a limiting amplifier and loss-of-signal ( LOS ) circuit. The limiting amplifier features dual-path , ROUT- 10G RX-LOS APC VCCTO TOUTA TOUTC VOUT 50Ω MUX LOS CSEL SDA SCL 50Π, -30mA to +30mA Voltage at TIN+, TIN-, RIN+, RIN-, LOS , DISABLE, FAULT, MDIN, RSSI, SCL, SDA, INTRPT , psP-P RX OMA BASED LOSS-OF-SIGNAL ( LOS ) SPECIFICATION (Notes 3 and 7) Assert/Deassert Time (Note


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PDF MAX3956 MAX3956 25Gbps
2014 - Not Available

Abstract: No abstract text available
Text: Deassert level 78 LOS High Level Setting SET_LOS[6:0] = 101d Assert level 121 Deassert , incorporates a limiting amplifier and loss-of-signal ( LOS ) circuit. The limiting amplifier features dual-path , TOUTA TOUTC VOUT 50Ω MUX LOS CSEL SDA SCL 50Ω 4G LPF RIN+ DDM VCC , ROUT+ and ROUT- . -30mA to +30mA Voltage at TIN+, TIN-, RIN+, RIN-, LOS , DISABLE , psP-P RX OMA BASED LOSS-OF-SIGNAL ( LOS ) SPECIFICATION (Notes 3 and 7) Assert/Deassert Time (Note


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PDF MAX3956 MAX3956 25Gbps
2013 - Not Available

Abstract: No abstract text available
Text: Deassert level 78 LOS High Level Setting SET_LOS[6:0] = 101d Assert level 121 Deassert , incorporates a limiting amplifier and loss-of-signal ( LOS ) circuit. The limiting amplifier features dual-path , APC VCCTO TOUTA TOUTC VOUT 50Ω MUX LOS CSEL SDA SCL 50Ω 4G LPF RIN , Voltage at TIN+, TIN-, RIN+, RIN-, LOS , DISABLE, FAULT, MDIN, RSSI, SCL, SDA, INTRPT, and CSEL .0.3V to , psP-P RX OMA BASED LOSS-OF-SIGNAL ( LOS ) SPECIFICATION (Notes 3 and 7) Assert/Deassert Time (Note


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PDF MAX3956 MAX3956 25Gbps
2013 - Not Available

Abstract: No abstract text available
Text: Deassert level 78 LOS High Level Setting SET_LOS[6:0] = 101d Assert level 121 Deassert , incorporates a limiting amplifier and loss-of-signal ( LOS ) circuit. The limiting amplifier features dual-path , APC VCCTO TOUTA TOUTC VOUT 50Ω MUX LOS CSEL SDA SCL 50Ω 4G LPF RIN , Voltage at TIN+, TIN-, RIN+, RIN-, LOS , DISABLE, FAULT, MDIN, RSSI, SCL, SDA, INTRPT, and CSEL .0.3V to , psP-P RX OMA BASED LOSS-OF-SIGNAL ( LOS ) SPECIFICATION (Notes 3 and 7) Assert/Deassert Time (Note


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PDF MAX3956 MAX3956 25Gbps
2014 - Not Available

Abstract: No abstract text available
Text: Deassert level 78 LOS High Level Setting SET_LOS[6:0] = 101d Assert level 121 Deassert , incorporates a limiting amplifier and loss-of-signal ( LOS ) circuit. The limiting amplifier features dual-path , TOUTA TOUTC VOUT 50Ω MUX LOS CSEL SDA SCL 50Ω 4G LPF RIN+ DDM VCC , ROUT+ and ROUT- . -30mA to +30mA Voltage at TIN+, TIN-, RIN+, RIN-, LOS , DISABLE , psP-P RX OMA BASED LOSS-OF-SIGNAL ( LOS ) SPECIFICATION (Notes 3 and 7) Assert/Deassert Time (Note


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PDF MAX3956 MAX3956 25Gbps
1997 - Not Available

Abstract: No abstract text available
Text: /HYHO 2QH &RPPXQLFDWLRQV OLQH RI VKRUWðKDXO WUDQVFHLYHUV WR , 78 5HFRPPHQGDWLRQ *ïææè IRU GHWHFWLQJ DQG , FOHDUð DQFHñ WKLV DSSOLFDWLRQ QRWH H[SODLQV , 78 5HFRPPHQGDWLRQ *ïææèï 7KH UHFRPPHQGDWLRQ JLYHV WKH , FRQIRUPLQJ WR UHFRPPHQGDWLRQ *ïæíêï 6HFWLRQ éïë RI , 78 *ïææè GDWHG 6HSWHPEHU ìääê VWDWHVã $ /26 GHIHFW , signal levels and consecutive pulse period conditions. With reference to declaring the LOS Condition, it , consecutive pulse intervals, where ìí 1 ëèè, a LOS must be declared.î In discussing clearing the LOS


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1996 - 7824 n3

Abstract: UC 3854 digital power ATM25 PE-67588 TLA-6M102 4-12PHY PHA50
Text: .32 .33 3.2 TC . 3.2.1 LOS .33 3.2.2 NRZI .33 3.2.3 .34 3.2.4 4B5B .34 3.2.5 , .41 3.5 CPU.42 3.5.1 .43 3.5.2 .44 3.6 .45 3.7 .45 3.7.1 LOS .45 3.7.2 HEC 4B5B , .52 4.2.2 CMR.53 4.2.3 PHY PICR.54 4.2.4 PHY PIMR.56 4.2.5 DCCOU.57 4.2.6 LOS LOSERR.58 4.2.7 LOS LOSMSK.59 10 4.2.8 PMD 1 LBPMDT.60 4.2.9 PMD 2 LBPMDU.61 4.2.10ATM LBATM , .77 5 5.1 .77 . 5.2 . . 78 . 5.2.1 Instruction register. 78 5.2.2


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PDF PD98408 T20TM S11409JJ3V0UM00 NEASCOT-T20 24NEC 7824 n3 UC 3854 digital power ATM25 PE-67588 TLA-6M102 4-12PHY PHA50
2004 - Not Available

Abstract: No abstract text available
Text: detect - Hysteresis Wavelength of Operation Electrical Differential Output Voltage Output LOS Voltage - Low Output LOS Voltage - High Symbol Sens Pin Pa Pd Min Typ Max -34 -10 -47 1.0 1100 0.6 0 2.0 -34 , Txdisable Mod_def(2) Mod_def(1) Mod_def(0) Rate select RX Los VeeR VeeR 1 2 3 4 5 6 7 8 9 10 VeeT TDTD , - SFP module depend on customer's PHY To I2C Bus Vcc3.3V 10K Los Of Signal , LOS RX GND RX GND Description Transmitter Ground Transmitter Fault Indication Transmitter Disable


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PDF SFF-8472 IEC-60825 SPS-33120W-CXX0 SPS-33120W-CXX0
2006 - Not Available

Abstract: No abstract text available
Text: detect - Hysteresis Wavelength of Operation Electrical Differential Output Voltage Output LOS Voltage - Low Output LOS Voltage - High Symbol Sens Pin Pa Pd Min Typ Max -34 -10 -47 1.0 1100 0.6 0 2.0 -34 , TX Txdisable Mod_def(2) Mod_def(1) Mod_def(0) Rate select RX Los VeeR VeeR 1 2 3 4 5 6 7 8 9 10 , - SFP module depend on customer's PHY To I2C Bus Vcc3.3V 10K Los Of Signal , LOS RX GND RX GND Description Transmitter Ground Transmitter Fault Indication Transmitter Disable


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PDF SPS-33120W-CXX0 SPS-33120W-CXX0
1999 - XRT84V24

Abstract: XRT84V24IV-160 XRT84V24IV-208 E1 frame
Text: Alarms · Detects LOF, COFA and LOS conditions · Each Framer Contains a 512 bit Elastic Store Buffer · , REV. 1.0.1 FIGURE 2. P IN OUT OF THE XRT84V24 IN THE 160 PIN PQFP PACKAGE LOS _0 TxPOS_0 TxNEG_0 TxLineClk_0 RxPOS_0 RxNEG_0 RxLineClk_0 LOS _1 GND TxPOS_1 TxNEG_1 TxLineClk_1 RxPOS_1 RxNEG , _0_SDO VDD RxLineClk_2 RxNEG_2 RxPOS_2 TxLineClk_2 TxNEG_2 TxPOS_2 GND LOS _2 RxLineClk_3 RxNEG_3 RxPOS_3 TxLineClk_3 TxNEG_3 TxPOS_3 LOS _3 NC 160 Lead PQFP 120 119 118 117 116 115 114


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PDF XRT84V24 XRT84V24 XRT84V24IV-160 XRT84V24IV-208 E1 frame
2002 - ao6418

Abstract: 24 port liu 6 PORT LIU E2 liu TVSS logos/INTEL DB2 LXT3108 M68302 M68360 MPC860
Text: . 60 13.3.1 Loss Of Signal ( LOS ). 60 13.3.1.1 Operation of USER LOS with Amplitude Detection . 62 13.3.1.2 Operation of USER LOS with Marks Density Detection. 62 13.3.2 Alarm , . 53 LOS Criteria for Intel® LXT3108 LIU . 61 LOS Register Configurations


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PDF LXT3108 LXT3108 ao6418 24 port liu 6 PORT LIU E2 liu TVSS logos/INTEL DB2 M68302 M68360 MPC860
2001 - GVIF

Abstract: GVIF cable 18bit TTL 40 pins lcd to 15 pins vga 30 pin xga lcd connector to vga connector QFP080-P-1414 CXB1452Q CXB1451Q 2SK303 QFP Package 80 lead
Text: ) RED0 (2) RED0 (1) VCCT RED0 (0) VEET 80 pin QFP (Plastic) LOS REFRQP SDATAP , Decoder VCCG 76 25 VCCG CNTL0 77 24 BLU0 (3) BLU1 (5) 78 23 BLU0 (4) BLU1 (4) 79 , , 18, 19 6, 7, 8, 9, 12, 13 78 , 79, 2, 3, 4, 5 TTL out Pixel data input in 1 pixcel/sftclk mode , switch LOS 50 TTL out Los of signal SDATAP/N 52, 53 Rx Serial input REFRQP/N , circuit SFTCLK, LOS (b') TTL output equivalent circuit REDxx, GRNxx, BLUxx, H/V sync, CNTLx VCCA


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PDF CXB1452Q 18bit 80pin PANEFP080-P-1414 42/COPPER QFP-80P-L03 QFP080-P-1414 GVIF GVIF cable 18bit TTL 40 pins lcd to 15 pins vga 30 pin xga lcd connector to vga connector QFP080-P-1414 CXB1452Q CXB1451Q 2SK303 QFP Package 80 lead
PILZ PNOZ m1p

Abstract: PILZ PNOZ mc3p PILZ PNOZ X1 PILZ pnoz m1p error reset PILZ PNOZmulti configurator 9 pilz pnoz 1 pnoz m1p PILZ pnoz m1p error Profibus pilz PNOZ EXAMPLE CONEXION
Text: 78 91 91 56 Controller 2 34 PROFIBUS DP DC 78 INFORMATION La , supérieur x10, au moyen d'un petit tournevis (dans notre exemple "3"). 0 56 56 x1 78 0 0 0 0 56 56 2 34 0 78 x10 - Réglez l'unité de l'adresse sur le commutateur rotatif inférieur x1 (dans notre exemple "6"). 91 x1 78 2 34 56 2 34 - On the lower , "6"). 78 78 91 x10 91 91 78 x1 2 34 In den Abbildungen ist als Beispiel


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1998 - Not Available

Abstract: No abstract text available
Text: Customer Education Services Class Schedule: North America 1998 through June 1999 DEC. 8-9 JAN. 6-7 7-8 20-21 FEB. 8-9 3-4 FPGA Tools Courses (2 days) LOCATIONS Huntsville, AL Phoenix, AZ San Jose, CA - Xilinx, Inc. Los Angeles, CA Irvine, CA San Diego, CA Toronto , 28-29 17-18 21-22 5-6 JUNE 23-24 7-8 7-8 by Stacey Pinckert , Courses (1 day) LOCATIONS Huntsville, AL Phoenix, AZ San Jose, CA Irvine, CA Los Angeles, CA San Diego


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