The Datasheet Archive

77V011 datasheet (1)

Part Manufacturer Description Type PDF
77V011 Integrated Device Technology 77V011 DPI to UTOPIA Level 2 Interface Original PDF

77V011 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - intel 8008 cpu

Abstract: ap 8022 b Ap-257 77V010 V400 AN-257 77V550 77V500 77V400 77V012
Text: . Path 1 of Figure shows a header lookup that uses the 77V011's subporting capabilities. An In-Stream , at power-up in systems with multiple 77V011s. This provides each 77V011 with its own In-Stream , Management Interface accesses PHYs connected to the 77V011. TAG & Port Address Removal UTOPIA II , pieces of the 77V011. The 77V011 is made up of a number of logical pieces. The DPI Receive Interface , cells from SwitchStar to the 77V011. In-Stream cells are received over the DPI Transmit interface. In


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PDF 77V011 77V011 AN-257 77V400 25Mbps 155Mbps 25Mbps intel 8008 cpu ap 8022 b Ap-257 77V010 V400 AN-257 77V550 77V500 77V400 77V012
1995 - DNA MARKING CODE

Abstract: utopia 2 WF-2
Text: llllatnemellllppuS no tamrofnI atneme ppuS The revision of the 77V011 can be determined visually from the date , dt 77V011 L155DA FWZ9929G The revision is also stored in the Device ID register at address , sdnuorakroW dna sno tp rcseD A no s veR Item #1 - The 77V011 polls the UTOPIA 2 receive ports out of sequence. Issue: The 77V011 may poll the UTOPIA 2 receive PHY ports out of sequence when DRxCLK is configured as , receive UTOPIA 2 interface. When this occurs the 77V011 will inadvertently skip PHY ports in the polling


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PDF 77V011 77V011 L155DA FWZ9929G 0x8000. 29MHz 40MHz 25Mbps DNA MARKING CODE utopia 2 WF-2
2001 - PHY registers map

Abstract: No abstract text available
Text: 77V011 Frequently Asked Questions 1. How many cells can be buffered in the 77V011? There are no internal FIFO's in the 77V011. Buffering inside the device (the pipeline) is less than one cell. The DTxCLK , padding) 03 f1 (crc-10 calculated by 77v011 ) 9. Can you recommend a suitable EEPROM to use with the 77V011? , is empty. 2. Does the 77V011 generate idle cells? No, the 77V011 does not generate Idle/Null cells. 3. Does the 77V011 start its Tx Byte Location and Rx Byte Location relative to zero or one? The Tx and Rx


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PDF 77V011 77V011? 77V011. 0x8002 0x8003. PHY registers map
1995 - 77V011

Abstract: FWZ9929G IDT77V011
Text: the 77V011. IDT77V011 Device Errata 2 of 2 October 22, 2001 Integrated Device Technology , IDT77V011 Device Errata Notes Supplemental Information The revision of the 77V011 can be , . Data Code dt 77V011 L155DA FWZ9929G The revision is also stored in the Device ID register at , 77V011 polls the UTOPIA 2 receive ports out of sequence. Issue: The 77V011 may poll the UTOPIA 2 receive , , and there is bursty back to back cells on the receive UTOPIA 2 interface. When this occurs the 77V011


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PDF IDT77V011 77V011 77V011 L155DA FWZ9929G 0x8000. FWZ9929G
2001 - Not Available

Abstract: No abstract text available
Text: 77V011. IDT77V011 Device Errata 2 of 2 October 22, 2001 Integrated Device Technology , /ATM_Switches_and_SARs- 77V011 .html CUSTOMER NOTIFICATION: As a result of Errata listed above, IDT has decided to notify , Errata Supplemental Information The revision of the 77V011 can be determined visually from the date code shown on the top marking. The date code is the third line of text. Notes dt 77V011 , 22, 2001: Added Item #4. Revision A - Descriptions and Workarounds Item #1 - The 77V011 polls the


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PDF IEN01-04 IDT77V011 SARs-77V011 77V011 77V011.
itt 8017

Abstract: 77V011 77V400 800B 800E 801C IDT77V011 IDT77V400 intel 8008 cpu
Text: PHYRST 74 O Normal PHY Reset. Resets the PHY device attached to the 77V011. PHYINT 71 I Normal PHY , transmit DPI interface the subport address is analyzed and extracted by the 77V011. The subport address is , the 77V011. It supports either a 4-bit or 8-bit Input Data Bus (DTxDATA[7:0]) and follows the standard , -3 bandwidth of a single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-Streamâ , the 77V011 and the PHY device(s) attached to it. SYSCLK 45 I Normal System Clock. CTRL A 52 o Normal


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PDF IDT77V011 25Mbps 16-bit 50MHz. 77V011 2975StenderWay itt 8017 77V400 800B 800E 801C IDT77V011 IDT77V400 intel 8008 cpu
1999 - intel 8008

Abstract: No abstract text available
Text: transmit DPI interface the subport address is analyzed and extracted by the 77V011. The subport address , DPI device to the 77V011. It supports either a 4bit or 8-bit Input Data Bus (DTxDATA[7:0]) and follows , 77V011 utilizes In-StreamTM programming for its device configuration options. The cells are received on , Temperature g e Device Interface The 77V011 uses a UTOPIA level 2 interface to receive and transmit ATM , contains two output test pins that can be controlled through the registers. Figure 2: 77V011 Interfaces


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PDF IDT77V011 25Mbps 16bit 50MHz. intel 8008
1999 - TBL27

Abstract: No abstract text available
Text: transmit DPI interface the subport address is analyzed and extracted by the 77V011. The subport address , used to transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports either a , 77V011 utilizes In-StreamTM programming for its device configuration options. The cells are received on , Translation Device Preliminary Industrial Temperature Range Device Interface The 77V011 uses a UTOPIA , registers. Figure 2: 77V011 Interfaces DPI R eceive Interface DRxCLK DRxFRM DRxDATA[7:0] RCLK RSOC


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PDF IDT77V011 25Mbps 16bit 50MHz. 5348tbl15 TBL27
1999 - 77V011

Abstract: 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Text: 77V011. The subport address is then interleaved with the Null PHY subport address (0x1F) and output on , DPI device to the 77V011. It supports either a 4bit or 8-bit Input Data Bus (DTxDATA[7:0]) and follows , single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-StreamTM programming , Preliminary Industrial Temperature Range Device Interface The 77V011 uses a UTOPIA level 2 interface to , registers. Figure 2: 77V011 Interfaces DPI R eceive Interface DRxCLK DRxFRM RCLK DRxDATA[7:0


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PDF 25Mbps 16bit IDT77V011 50MHz. I5/15/00 5348tbl15 77V011 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
2001 - 77V011

Abstract: 77V400 IDT77011 IDT77V011 IDT77V400 IDTV400 intel 8008 cpu
Text: the PHY device attached to the 77V011. PHYINT 71 I Normal PHY Interrupt. Phy layer , analyzed and extracted by the 77V011. The subport address is then interleaved with the Null PHY subport , transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports either a 4bit or 8 , -3 bandwidth of a single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-StreamTM , 77V011 and the PHY device(s) attached to it. SYSCLK 45 I Normal System Clock. CTRL_A


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PDF IDT77V011 25Mbps 16-bit 50MHz. 5348drw18. 5348tbl28. 77V011 77V400 IDT77011 IDT77V011 IDT77V400 IDTV400 intel 8008 cpu
1999 - intel 8008 cpu

Abstract: No abstract text available
Text: transmit DPI interface the subport address is analyzed and extracted by the 77V011. The subport address , used to transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports either a , 77V011 utilizes In-StreamTM programming for its device configuration options. The cells are received on , Translation Device Preliminary Industrial Temperature Range Device Interface The 77V011 uses a UTOPIA , registers. Figure 2: 77V011 Interfaces DPI R eceive Interface DRxCLK DRxFRM DRxDATA[7:0] RCLK RSOC


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PDF IDT77V011 25Mbps 16bit 50MHz. 5348tbl15 intel 8008 cpu
2001 - Not Available

Abstract: No abstract text available
Text: the PHY device attached to the 77V011. PHYINT 71 I Normal PHY Interrupt. Phy layer , analyzed and extracted by the 77V011. The subport address is then interleaved with the Null PHY subport , transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports either a 4bit or 8 , -3 bandwidth of a single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-Streamâ , 77V011 and the PHY device(s) attached to it. SYSCLK 45 I Normal System Clock. CTRL_A


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PDF IDT77V011 25Mbps 16-bit 50MHz. 5348drw18. 5348tbl28.
1999 - ty 8016

Abstract: 10.7 HY TY 8004 sm 8013 SM 8002 datasheet ty 8016 IDT77V400 77V011 77V400 800B
Text: address is analyzed and extracted by the 77V011. The subport address is then interleaved with the Null , Interface is used to transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports , single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-StreamTM programming , Temperature Range Device Interface The 77V011 uses a UTOPIA level 2 interface to receive and transmit ATM , contains two output test pins that can be controlled through the registers. Figure 2: 77V011 Interfaces


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PDF 25Mbps 16bit IDT77V011 50MHz. 5348drw45 ty 8016 10.7 HY TY 8004 sm 8013 SM 8002 datasheet ty 8016 IDT77V400 77V011 77V400 800B
1999 - sm 8013

Abstract: 77V011 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Text: address is analyzed and extracted by the 77V011. The subport address is then interleaved with the Null , Interface is used to transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports , single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-StreamTM programming , Temperature Range Device Interface The 77V011 uses a UTOPIA level 2 interface to receive and transmit ATM , contains two output test pins that can be controlled through the registers. Figure 2: 77V011 Interfaces


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PDF 25Mbps 16bit IDT77V011 50MHz. 5348drw45 sm 8013 77V011 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
1999 - Not Available

Abstract: No abstract text available
Text: address is analyzed and extracted by the 77V011. The subport address is then interleaved with the Null PHY , the 77V011. It supports either a 4bit or 8-bit Input Data Bus (DTxDATA[7:0]) and follows the standard , 77V011 utilizes In-StreamTM programming for its device configuration options. The cells are received on , 77V011 uses a UTOPIA level 2 interface to receive and transmit ATM cells to and from the PHY device. It , controlled through the registers. Figure 2: 77V011 Interfaces DPI R eceive Interface DRxCLK DRxFRM


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PDF IDT77V011 25Mbps 16bit 50MHz.
1999 - mbus

Abstract: SK 8022 ace dsc hen nu SM 8002 C
Text: ription 5348t bl11 address is analyzed and extracted by the 77V011. The subport address is then , the IDT SWITCHStAR or other DPI device to the 77V011. It supports either a 4bit or 8-bit Input Data , of lower bandwidth ports. The 77V011 utilizes In-StreamTM programming for its device configuration , Interface The 77V011 uses a UTOPIA level 2 interface to receive and transmit ATM cells to and from the PHY , pins that can be controlled through the registers. Figure 2: 77V011 Interfaces DPI R eceive


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PDF IDT77V011 25Mbps 16bit 50MHz. 5248drw26a 32-bytes 31-bytes. 5348drw18. 5348tbl28. mbus SK 8022 ace dsc hen nu SM 8002 C
1999 - 77V012

Abstract: IDT71V633 IDT77010 IDT77155 IDT77V011 IDT77V012 IDT77V1254 IDT77V400 IDT77V500
Text: traffic that can be received by a WAN Access Switch. The 77V011 provides a DPI to UTOPIA Level 2 , 770xx PHY WAN Access Network PHY 77V012 FR SAR T1/E1 77V011 xDSL ADSL 77010 77V400 Voice T1/E1 770xx 77V012 AAL2 77155 OC-3 UNI 71V633 77V011


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PDF AB-222 IDT77V400 77V500 770xx 77V012 77V011 77V400 71V633 77V012 IDT71V633 IDT77010 IDT77155 IDT77V011 IDT77V012 IDT77V1254 IDT77V500
77V011

Abstract: 77V400 77V500
Text: and Other: Obsolete Fab Technology / Process 77V011 devices. 77V400 and 77V500 devices are Obsolete Assembly Technology / Process no longer viable without the 77010 or 77V011 Obsolete Package


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PDF 77V400S156BC 77V400S156BCG 77V400S156DS 77V500S25BC 77V500S25BCG 77V500S25PF FRA-2265-01 QCA-1795 77V011 77V400 77V500
1999 - 77V011

Abstract: 77V012 IDT77010 IDT77252 IDT77V011
Text: 77V011-line card are shown in Figure 4.1. 01/27/99 31 Figure 4.1 4.1.5.5.1 77V011 device reset command Selection of the "Reset 77V011" option from the menu shown in Figure 4.1 opens the "Reset 77V011" dialog box shown in Figure 4.1. The user should specify the switch id and the port number to , .31 4.1.5.5.1 77V011 device reset 01/27/99 2 4.1.5.5.2 77V011 reset PHY command


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PDF SWDEMO11 idt77252 77V011 77V012 IDT77010 IDT77V011
1999 - DSLAM

Abstract: DSLAM configuration AB-220 IDT77V500 IDT77V400 IDT77V012 IDT77V011 IDT71V633 77V550 STM-1 Physical interface PHY
Text: ) 77V500 PHY IDT CPU or 77V550 STM-1, OC-3, etc. PHY PHY PHY 77V011 77V400 77V012 · · · PHY PHY (up to 8) PHY PHY DPI UTOPIA I o PHY PHY 77V011


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PDF AB-220 IDT77V500 77V500 77V550 77V011 77V400 77V012 71V633 5272drw01 DSLAM DSLAM configuration AB-220 IDT77V400 IDT77V012 IDT77V011 IDT71V633 77V550 STM-1 Physical interface PHY
77V011

Abstract: No abstract text available
Text: ) 77010L155PQF 77V011L155DA No replacement part available No replacement part available REASON FOR , Other: Obsolete Fab Technology / Process and 77V011 devices. Obsolete Assembly Technology


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PDF 77010L155PQF 77V011L155DA FRA-2265-01 QCA-1795 77V011
2000 - DSLAM

Abstract: 77V011 77V550 77V500 77V400 77V1254 77V1253 77V1054 77V012 DSLAM HEADER
Text: programming of Switch from remote 77V012 Header Translation Enables complex TAG switching 77V011


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PDF 77V1254 77V1054 77V1253 77V500 77V252 77V222 77V400 APP-BRF5-00050 DSLAM 77V011 77V550 77V500 77V400 77V1254 77V1253 77V1054 77V012 DSLAM HEADER
2001 - 77V011

Abstract: 77V012 77V500 AN-301 V400 V500
Text: 155Mbps ports for Sub Porting (each of these ports can be connected to either a 77V011 or a 77V012), and , their full header value. They are routed to an Access Switch1 Sub Port, where the 77V011 , or 77V012


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PDF 77V500 AN-301 77V011 77V012 AN-301 V400 V500
2001 - 77V400

Abstract: 77V500 IDT77500 IDT77V011 IDT77V012 IDT77V400 IDT77V500 V400 OD031
Text: for the 77V011. Sub-porting and Multicast Sub-porting using the IDT77V011 enables multiple PHYs to , /16 1 PHY Phy SwitchStar Chipset DPI-4 or DPI-8 PHY Phy 2 77V011 77011


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PDF 16x16 IDT77500/IDT77V400s. IDT77V500s IDT77V400s 77V400 77V500 IDT77500 IDT77V011 IDT77V012 IDT77V400 IDT77V500 V400 OD031
1997 - Not Available

Abstract: No abstract text available
Text: Layer). As with 77V011-line card, the 77V012 line cards could be configured using one or more of the , , 77V011 & 77V012 Switch BIOS Layer In-stream Access Sub-Layer Switch Access Layer (NIC Driver Interface


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