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Citizen Electronics Co Ltd
CM315D32768HZFT Crystal 32.768kHz 12.5pF 2-Pin CSMD T/R (Alt: CM315D32768HZFT)
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Avnet CM315D32768HZFT Tape and Reel 0 16 Weeks 3,000 - - - - - More Info
Citizen Finedevice Co Ltd
CM200C32768HZFT 32.768KHZ PLASTIC SMD - 12.5pF - 5ppm
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Newark element14 CM200C32768HZFT Bulk 0 1 $0.961 $0.684 $0.453 $0.338 $0.309 More Info
America II Electronics CM200C32768HZFT 12,000 - - - - - More Info
New Advantage Corporation CM200C32768HZFT 21,000 21,000 - - - - $0.41 More Info
Citizen Finedevice Co Ltd
CFS-20632768HZFB 32.768KHZ CYLINDER T/H - 12.5pF - 5ppm
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Newark element14 CFS-20632768HZFB Bulk 0 1 $0.54 $0.362 $0.198 $0.141 $0.127 More Info
mc
MS1VT1N32K768HZ
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
ComS.I.T. MS1VT1N32K768HZ 5,000 - - - - - More Info
Others
2X6TF-32768HZ INSTOCK
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Chip 1 Exchange 2X6TF-32768HZ 9,920 - - - - - More Info
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Citizen Finedevice Co Ltd
CM315D32768HZFT
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
New Advantage Corporation CM315D32768HZFT 9,000 9,000 - - - - $0.3818 More Info

768Hz Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - 50hz to 60hz converter circuit diagram

Abstract: max132 application kp1835 pt100 sensor interface WITH ADC Data Logger max132 50hz into 60hz circuit diagram pt100 interface WITH ADC SPRAGUE 715p DIN132 MAX132
Text: with a clock frequency of 32, 768Hz. If different clock frequencies are used, select CINT using the , above 32, 768Hz. The raw data can be used where highest accuracy is not required, and the least , AGND = IN LO = REF- = 0V, REF+ = 545mV, RINT = 602k, CINT = 0.0047µF, CREF = 0.1µF, fCLK = 32, 768Hz , IN LO = REF- = 0V, REF+ = 545mV, R INT = 602k, CINT = 0.0047µF, CREF = 0.1µF, fCLK = 32, 768Hz , 60Hz , connected to a 32, 768Hz crystal. Do not connect with external clock source. 6 OSC1 Oscillator Input


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PDF 18-Bit MAX132 512mV MAX132 DIN132 DOUT132 50hz to 60hz converter circuit diagram max132 application kp1835 pt100 sensor interface WITH ADC Data Logger max132 50hz into 60hz circuit diagram pt100 interface WITH ADC SPRAGUE 715p
2002 - kp1835

Abstract: max132 application 50hz to 60hz converter circuit diagram MAX132 MAX132ENG MAX132MRG MAX132EWG MAX132CWG MAX132CNG pt100 rtd spi
Text: with a clock frequency of 32, 768Hz. If different clock frequencies are used, select CINT using the , above 32, 768Hz. The raw data can be used where highest accuracy is not required, and the least , AGND = IN LO = REF- = 0V, REF+ = 545mV, RINT = 602k, CINT = 0.0047µF, CREF = 0.1µF, fCLK = 32, 768Hz , IN LO = REF- = 0V, REF+ = 545mV, R INT = 602k, CINT = 0.0047µF, CREF = 0.1µF, fCLK = 32, 768Hz , 60Hz , connected to a 32, 768Hz crystal. Do not connect with external clock source. 6 OSC1 Oscillator Input


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PDF 18-Bit MAX132 512mV MAX132 DIN132 DOUT132 kp1835 max132 application 50hz to 60hz converter circuit diagram MAX132ENG MAX132MRG MAX132EWG MAX132CWG MAX132CNG pt100 rtd spi
MAX132ENG

Abstract: MAX132
Text: frequen­ cy is 32, 768Hz. If different clock frequencies are used, select CINT using the following , conversion rates, although the 50Hz mode is recommended for clock rates above 32, 768Hz. The raw data can be , 0.0047nF, CREF = 0.1 jiF, f C L K = 32, 768Hz , 60Hz mode, Ta = Tmin to Tmax, unless otherwise noted , , CINT = 0.0047nF, CREF = 0.1 (iF, TCLK = 32, 768Hz , 60Hz mode, Ta = T m in to Tm ax , unless otherwise , HI 512m V INPUT V- P3 OSCI DGND 0SC2 6H 0 H r 32, 768Hz Figure 1. Test and


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PDF 50Hz/60H MAX132CNG MAX132CWG MAX132C/D MAX132ENG MAX132
50hz to 60hz converter circuit diagram

Abstract: ctc 1403 MAX135 MAX135CPI MAX135EPI
Text: integrator capacitor when the clock frequency is 32, 768Hz. If different clock frequencies are used, select CI , , RINT = 402kQ, CINT = 0.0047mF, CREF = 0.1 jiF, fclk = 32, 768Hz , 60Hz mode, Ta = Tmin to Tmax. unless , , CINT = 0.0047nF, CREF = 0.1nF. fCLK = 32, 768Hz , 60Hz mode, Ta = Tmin to Tmax. unless otherwise noted , data on the rising edge 4 OSC2 Oscillator Output 2 normally connected to a 32, 768Hz crystal. 5 OSC1 Oscillator Input 1 normally connected to a 32, 768Hz crystal, or may be connected to an external clock. 6-13


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PDF 15-Bit MAX135 15-bit, 18-bit 125juA 300mV 50hz to 60hz converter circuit diagram ctc 1403 MAX135CPI MAX135EPI
max132cng maxim

Abstract: max132cwg MAX132ENG MAX132
Text: 602k£2 integrator resistor and a 4.7nF integrator ca p a citor when the clock frequen cy is 32, 768Hz. If , m ode is recom m ended for clo ck rates above 32, 768Hz. The raw data can be used where highest , , 768Hz , 60Hz mode, Ta = Tmin to Tm ax . unless otherwise noted.) PARAMETER ACCURACY Resolution Zero Error , LO = OV, REF HI = 545mV, RINT = 602kQ, CINT = 0.0047 m F, CREF = O.IfiF, fCLK = 32, 768Hz , 60Hz mode , 0SC1 IN LO IN HI 512mV INPUT -5V VDGND 0SC2 32, 768Hz Figure 1, Test and Typical


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PDF 50Hz/60Hz 18-bit max132cng maxim max132cwg MAX132ENG MAX132
1998 - DS-VT200

Abstract: DS-VT-200 32KHZ 768KHZ S3513A DSVT200 768-HZ
Text: =6pf Cg=335pf S-3513A 14 2. 19 (*) 32, 768HZ±5ppm1±13 () 5×10-6(1ppm)×60×60×24×30=13/ (1) (1ppm ) (2) 32, 768HZ (3) Cg VDD XIN SIO Cg XOUT SCK F32K CS VSS S , F32K 32,768 2 XIN ( 32, 768HZ ) Cd,Cg - 3 XOUT 4 VSS ( GND ) - , VDD=3 V,:()SII DS-VT-200(CL=6pF,32, 768HZ ) Min. Typ. Max. VSTA 10 1.7 , ) (Ta=25 °C, VDD=3 V,:()SII DS-VT-200(CL=6pF,32, 768HZ ) Min. Typ. Max. VDD Ta


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PDF S-3513A S-3513ACPU 32KHZIC 32KHZ DS-VT200 DS-VT-200 32KHZ 768KHZ S3513A DSVT200 768-HZ
Maxim ds1306 date code

Abstract: DS1389 RTC DS1306 56F800 DS1305 DS1306 DS1390 DS1305 circuit DSP56F800DEMO
Text: . 1 of 5 REV: 111203 2 of 5 A B C 1 B1 BATTERY 32, 768Hz X3 32, 768Hz X2 32, 768Hz X1 5 1 2 3 4 5 6 7 1 2 3 4 5 8 3 4 10 12 9 11


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PDF DS1306 32kHz DS1305 DSP56F800DEMO 0x0096; 0x0007; 0x0002; 0x00f3; Maxim ds1306 date code DS1389 RTC DS1306 56F800 DS1390 DS1305 circuit
50hz to 60hz converter circuit diagram

Abstract: vw t4 ICL8069 MAX135 MAX135CPI MAX135CWI MAX135EPI MAX135EWI
Text: resistor and a 4.7nF integrator capacitor when the clock frequency is 32, 768Hz. If different clock , , fCLK = 32, 768Hz , 60Hz mode, Ta = Tmin to Tmax. unless otherwise noted.) PARAMETER SYMBOL CONDITIONS , edge 4 5 OSC2 Oscillator Output 2 normally connected to a 32, 768Hz crystal. 0SC1 Oscillator Input 1 normally connected to a 32, 768Hz crystal, or may be connected to an external clock. 6-13 D0-D7 Three-State , that are greater than 32, 768Hz , use either the 50Hz or 60Hz mode; however, the 50Hz mode will Improve


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PDF 15-Bit MAX135 15-bit, 18-bit 300mV 50hz to 60hz converter circuit diagram vw t4 ICL8069 MAX135CPI MAX135CWI MAX135EPI MAX135EWI
2004 - digital alarm clock

Abstract: DS1375 J-STD-020A
Text: frequency = 400kHz. CLK pin running at 32, 768Hz , rise and fall times at 10ns or less. Specified with 2 , be 32, 768Hz , 8192Hz, 60Hz, or 50Hz square wave, 45% to 55% duty cycle. Square-Wave/Interrupt Output , /PM indicator. The DS1375 requires an external clock source selectable between 32, 768Hz , 8192Hz , OUTPUT FREQUENCY 1 X X As selected X X N/A (Interrupt) 0 0 0 32, 768Hz 0 0 1Hz 0 0 0 32, 768Hz 0 1 1.024kHz 0 0 0 32, 768Hz 1 0


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PDF DS1375 768kHz, 192kHz, 24-hour 12-hour DS1375 digital alarm clock J-STD-020A
2008 - transistor a1m

Abstract: digital clock with alarm design 12 Hour Digital Clock Circuit DS1375 DS1375T T633
Text: frequency = 400kHz. CLK pin running at 32, 768Hz , rise and fall times at 10ns or less. Specified with I2C , Clock Input. This pin must be 32, 768Hz , 8192Hz, 60Hz, or 50Hz square wave, 45% to 55% duty cycle. 2 , /PM indicator. The DS1375 requires an external clock source selectable between 32, 768Hz , 8192Hz , 1 X X As selected X X N/A (Interrupt) 0 0 0 32, 768Hz 0 0 1Hz 0 0 0 32, 768Hz 0 1 1.024kHz 0 0 0 32, 768Hz 1 0 4.096kHz 0


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PDF DS1375 768kHz, 192kHz, 24-hour 12-hour DS1375 transistor a1m digital clock with alarm design 12 Hour Digital Clock Circuit DS1375T T633
AX135C

Abstract: dielectric resonators
Text: a 4.7nF integrator capacitor when the clock frequency is 32, 768Hz. If dif ferent clock frequencies , , 768Hz crystal, or may be co nn e cte d to an external clock. Three-State Data Inputs/O utputs. See , in Table 1 that are greater than 32, 768Hz , use either the 50Hz or 60Hz mode; however, the 50Hz mode , (CREF), and a crystal. A 32, 768Hz crystal frequency is used to test the MAX135, The crystal frequency , /0Hz With a 32, 768Hz crystal, the 50Hz/60Hz bit sets the integration period equal to one line cycle


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PDF 15-Bit, 300mV 28-Pin MAX135 AX135C dielectric resonators
1996 - SK121

Abstract: control light intensity using SCR EL12 SP4415 SP4415CN SCHEMATIC circuit scr H-Bridge Nippon capacitors
Text: T= 25°C; VDD = 3.0V; Lamp Capacitance = 2000pF; Coil = 30 mH at 125 Ohms; Osc = 32, 768Hz (Unless , ground. The SP4415 is optimized for 32, 768Hz clock signals and is allowed to vary from 20 kHz to 60kHz , phases for the coil and lamp. The suggested oscillator frequency is 32, 768Hz . This clock frequency is internally divided to create two internal control signals, fCOIL and fLAMP. For example a 32, 768Hz signal


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PDF SP4415 140VPP SP4415 SP4415DS/06 SK121 control light intensity using SCR EL12 SP4415CN SCHEMATIC circuit scr H-Bridge Nippon capacitors
MAX132ENG

Abstract: MAX132
Text: 4.7nF integrator capacitor are recommended with a clock frequency of 32, 768Hz. If different clock , , although the 50Hz mode is recommended for clock rates above 32, 768Hz. The raw data can be used where , „¦, CINT = 0.0047µF, CREF = 0.1µF, fCLK = 32, 768Hz , 60Hz mode, TA = TMIN to TMAX, unless otherwise noted , , CREF = 0.1µF, fCLK = 32, 768Hz , 60Hz mode, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER , , 768Hz crystal. Do not connect with external clock source. 6 OSC1 Oscillator Input 1 is normally


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PDF MAX132 18-bit 512mV DIN132 DOUT132 MAX132ENG
2008 - Not Available

Abstract: No abstract text available
Text: frequency = 400kHz. CLK pin running at 32, 768Hz , rise and fall times at 10ns or less. Specified with I2C , Clock Input. This pin must be 32, 768Hz , 8192Hz, 60Hz, or 50Hz square wave, 45% to 55% duty cycle. 2 , /PM indicator. The DS1375 requires an external clock source selectable between 32, 768Hz , 8192Hz , FREQUENCY 1 X X As selected X X N/A (Interrupt) 0 0 0 32, 768Hz 0 0 1Hz 0 0 0 32, 768Hz 0 1 1.024kHz 0 0 0 32, 768Hz 1 0 4.096kHz


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PDF DS1375 768kHz, 192kHz, 24-hour 12-hour DS1375
2003 - DS1375

Abstract: J-STD-020A 8192Hz 12 Hour Digital Clock Circuit
Text: clocking at max frequency = 400kHz. CLK pin running at 32, 768Hz , rise and fall times at 10ns or less , be 32, 768Hz , 8192Hz, 60Hz, or 50Hz square wave, 45% to 55% duty cycle. Square-Wave/Interrupt Output , /PM indicator. The DS1375 requires an external clock source selectable between 32, 768Hz , 8192Hz , OUTPUT FREQUENCY 1 X X As selected X X N/A (Interrupt) 0 0 0 32, 768Hz 0 0 1Hz 0 0 0 32, 768Hz 0 1 1.024kHz 0 0 0 32, 768Hz 1 0


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PDF DS1375 768kHz, 192kHz, 24-hour 12-hour DS1375 J-STD-020A 8192Hz 12 Hour Digital Clock Circuit
1996 - SCHEMATIC circuit scr H-Bridge

Abstract: EL12 SP4415 SP4415CN rm 609 Nippon capacitors Sankyo STK-0050 Sankyo Shoji sk-80
Text: 3.0V; Lamp Capacitance = 2000pF; Coil = 30 mH at 125 Ohms; Osc = 32, 768Hz (Unless otherwise noted , external clock should range from (Vdd-1V) to ground. The SP4415 is optimized for 32, 768Hz clock signals , coil and lamp. The suggested oscillator frequency is 32, 768Hz . This clock frequency is internally divided to create two internal control signals, Fcoil and Flamp. For example a 32, 768Hz signal will be


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PDF SP4415 140Vpp SP4415 SP4415DS/01 SCHEMATIC circuit scr H-Bridge EL12 SP4415CN rm 609 Nippon capacitors Sankyo STK-0050 Sankyo Shoji sk-80
1997 - DS-VT-200

Abstract: DS-VT200 1024HZ 32768HZ 32KHZ S-3530A
Text: -3530A NO. 1 INT1 1 N INT1 ( VDD ) 2 XIN ( 32, 768HZ ) Cd ,Cg ¾ , =6pF,32, 768HZ ) VSTA Typ. Max. 1.7 10 Min. ¾ 5.5 V TSTA ¾ , -3530A DC 8DC(3V) (Ta=25°C, VDD=3 V,:()SII DS-VT-200(CL=6pF,32, 768HZ ) Min. Typ. Max , =6pF,32, 768HZ ) Min. Typ. Max. VDD Ta=-20+70°C 1.7 3.0 5.5 V


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PDF S-3530A S-3530A, 32KHZ S-3530AEFS DS-VT-200 DS-VT200 1024HZ 32768HZ 32KHZ S-3530A
1996 - ACT 6040

Abstract: CH5070AS-203K-006 gunze Nippon capacitors SCHEMATIC circuit scr oscillator
Text: = 32, 768Hz (Unless otherwise noted) PARAMETER Supply Voltage, VDD Supply Current, ICOIL+IDD Coil , is optimized for 32, 768Hz clock signals and is allowed to vary from 20 kHz to 60kHz. The externally , phases for the coil and lamp. The suggested oscillator frequency is 32, 768Hz . This clock frequency is internally divided to create two internal control signals, fCOIL and fLAMP. For example a 32, 768Hz signal


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PDF SP4415 140VPP SP4415 SP4415DS/05 ACT 6040 CH5070AS-203K-006 gunze Nippon capacitors SCHEMATIC circuit scr oscillator
32KHz crystal

Abstract: MAX6910 MAX6909 MAX6902 MAX6901 MAX6900 APP617 AN617 crystal oscillator 32.768 6pf 32khz crystal oscillator
Text: from +25°C ambient to +45°C ambient? drift = 32, 768Hz × (-0.04ppm/°C² × (1 × 10-6) × (20°C - 24°C)² = , {[1/[ = drift)/32, 768Hz ]] - 1s}/1s drift = {[1/[32, 768Hz - 0.8192Hz)/32,768]]- 1s}/1s = 0.00025s/s Error due to 25°C initial crystal tolerance of ±20ppm: initial = 32, 768Hz × (-20ppm × (1 × 10-6) =


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PDF 32kHz, 32768Hz, 768kHz 32kHz com/an617 MAX6900: MAX6901: MAX6902: MAX6909: 32KHz crystal MAX6910 MAX6909 MAX6902 MAX6901 MAX6900 APP617 AN617 crystal oscillator 32.768 6pf 32khz crystal oscillator
Not Available

Abstract: No abstract text available
Text: is a 32, 768Hz crystal oscillator. FUNCTIONS • 3 Function: HOUR, MINUTE, SECOND. • Tim e , doubler, voltage trlpler. Lower power consumption. 32, 768Hz Crystal frequency. Built-in voltage doubler , rystal Param eter Fp = 32, 768Hz C L = 10pF C1 = 4 fF C o = 2.0pF Rs = 35KÍJ Q = 35,000 f i g


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PDF KS5113 KS5113 768Hz
AX132M

Abstract: K2602 MAX132ENG MAX132
Text: , 768Hz. If different clock frequencies are used, select C in t using the fo l lowing equations: The , is rec omm ended for clock rates above 32, 768Hz. The raw data can be used where highest a ccuracy is , , REF+ = 545mV, R in t = 602k£2, C in t = 0.0047pF, C r e f = 0.1 pF, fCLK = 32, 768Hz , 60Hz mode, T a = , 0.0047pF, C r e f = 0.1 pF, fCLK = 32, 768Hz , 60Hz mode, T a = Tmin to T m a x , unless otherwise noted , connected to a 32, 768Hz crystal. Do not connect with external clock source. O scillator Input 1 is normally


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PDF MAX132 18-bit MAX132 768Hz MAX13 AX132M K2602 MAX132ENG
Not Available

Abstract: No abstract text available
Text: feedback resis­ tor for use with 32, 768Hz quartz crystals. The circuit operates from a single 1.5 volt , power consumption. 32, 768Hz crystal oscillator. Single 1.5V battery operation. Built-in voltage , * CMOS DIGITAL INTEGRATED CIRCUIT APPLICATION CIRCUIT * Quartz Crystal Parameter Fp = 32, 768Hz CL


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PDF KS5112 KS5112 768Hz
digital watch circuit

Abstract: ks531
Text: head of melody Very low stand-by current Designed to use with CMOS digital watch circuit 32, 768Hz , , 768Hz I I KS5310 Series OUT RPT _ II M S from Switches of " Watch Circuit `


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PDF KS5310 KS5310 768Hz digital watch circuit ks531
circuit diagram for samsung lcd

Abstract: ks531 IC mark A09 lcd circuit diagram for samsung digital alarm watch circuit
Text: tim e and alarm set · 32, 768Hz crystal frequency · On-chip oscillator and resistors · On-chip voltage , , 768Hz CL = 12.5pF C1 = 4 fF CO = 2.5pF Rs = 35K12 Q = 35,000 PAD DIAGRAM 180 G 2/D 2 470 760


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PDF KS5184 KS5184 KS5310 hour/24 Driv5055 circuit diagram for samsung lcd ks531 IC mark A09 lcd circuit diagram for samsung digital alarm watch circuit
APP2142

Abstract: DS1340 application note ds1340 AN2142 M41T00 32768 Crystal w04h
Text: subtracts 256 oscillator cycles for every 125,829,120 actual 32, 768Hz oscillator cycles (64 minutes). This , exactly 32, 768Hz , each of the 31 increments of the calibration bits would represent +10.7 or -5.35


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PDF DS1340, M41T00, DS1340 DS1340 com/an2142 DS1340: AN2142, APP2142 DS1340 application note AN2142 M41T00 32768 Crystal w04h
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