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Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
BM2P109TF BM2P109TF ECAD Model ROHM Semiconductor Switching Regulator,
BM2SC124FP2-LBZ BM2SC124FP2-LBZ ECAD Model ROHM Semiconductor Quasi-resonant(Low EMI) AC/DC Converter Built-in 1700 V SiC-MOSFET (FB OLP=Latch ,VCC OVP=Auto Restart)
BD9A600MUV BD9A600MUV ECAD Model ROHM Semiconductor 2.7V to 5.5V Input, 6A Integrated MOSFET, Single Synchronous Buck DC/DC Converter
BD9D321EFJ BD9D321EFJ ECAD Model ROHM Semiconductor 4.5 to 18V 3.0A 1ch Synchronous Buck Converter,External Current Detection Resistors, 1.4 ohm on resistor
BD9G341AEFJ-LB BD9G341AEFJ-LB ECAD Model ROHM Semiconductor 12V to 76V, Buck switching regulator with integrated 150mΩ power MOSFET (Industrial Grade)
BD9P205MUF-C BD9P205MUF-C ECAD Model ROHM Semiconductor 3.5V to 40V Input, 0.8V to 8.5V Output, 2A Single 2.2MHz Buck DC/DC Converter For Automotive, VQFN20FV4040 Package

75Mhz 4 channel rc receiver ic Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - Not Available

Abstract: No abstract text available
Text: channel . • • • • • • Up to 85MHz 10bit dual channel LVDS Receiver Up to 85MHz 10bit dual channel LVDS Transmitter Wide LVDS input skew margin: ± 480ps at 75MHz Accurate LVDS output timing: ± 250ps at 75MHz Reduced swing LVDS output mode supported to suppress the system EMI , receives the dual channel LVDS data streams and transmits the LVDS data through various line rate , CAP GND 3 62 GND VDD 4 61 VDD RA1– 5 60 TA1– RA1+ 6


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PDF THC63LVD1027 THC63LVD1027 85MHz 10Bits 85MHz, 30bits 595Mbps
2010 - Not Available

Abstract: No abstract text available
Text: ns CLKOUT=50MHz 0 1000 ps Receiver Skew CLKOUT= 75MHz -550 0 550 ps , THC63LVD104C_Rev.2.1_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat , Open LVDS Input Block Diagram LVDS INPUT CMOS/TTL OUTPUT 7 RC +/RD+/- RCLK+/- RD6-RD0 , RE2 RE1 RE0 RD6 RD5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RARA+ RBRB


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PDF THC63LVD104C THC63LVD104C 112MHz 30Bits 35bits 112MHz, 784Mbps
2013 - Not Available

Abstract: No abstract text available
Text: — + 4 μA Conditions Min. Typ. Max. Units V LVDS Receiver DC , , VIC_RX = 1.2V , tRCH = 4 /7 tRCP LVDS Receiver Input Timing tRIP0 tRIP1 tRIP2 tRIP3 tRIP4 tRIP5 , Output. • • • • • • 30bits/pixel dual link LVDS Receiver 30bits/pixel dual Link LVDS Transmitter Wide LVDS input skew margin: ± 480ps at 75MHz Accurate LVDS output timing: ± 250ps at 75MHz Reduced swing LVDS output mode supported to suppress the system EMI Various line rate


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PDF THC63LVD1027 THC63LVD1027 30bits/pixel 480ps 75MHz 250ps
2010 - THC63LVD104c

Abstract: THC63LVD104A THC63LVD104 Thine 784-Mbps THC63LVDF64x lvds to NTSC
Text: T 125.0 ns CLKOUT=50MHz 0 1000 ps Receiver Skew CLKOUT= 75MHz -550 0 , THC63LVD104C_Rev.1.10_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat , Block Diagram LVDS INPUT CMOS/TTL OUTPUT 7 RC +/RD+/- RCLK+/- RD6-RD0 7 PLL RC6-RC0 , RE0 RD6 RD5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RARA+ RBRB+ LVCC


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PDF THC63LVD104C THC63LVD104C 112MHz 30Bits 35bits 112MHz, 784Mbps THC63LVD104A THC63LVD104 Thine 784-Mbps THC63LVDF64x lvds to NTSC
2010 - Not Available

Abstract: No abstract text available
Text: channel . • • • • • • Up to 85MHz 10bit dual channel LVDS Receiver Up to 85MHz 10bit dual channel LVDS Transmitter Wide LVDS input skew margin: ± 480ps at 75MHz Accurate LVDS output timing: ± 250ps at 75MHz Reduced swing LVDS output mode supported to suppress the system EMI , receives the dual channel LVDS data streams and transmits the LVDS data through various line rate , CAP GND 3 62 GND VDD 4 61 VDD RA1– 5 60 TA1– RA1+ 6


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PDF THC63LVD1027 THC63LVD1027 85MHz 10Bits 85MHz, 30bits 595Mbps
2008 - Not Available

Abstract: No abstract text available
Text: to 75MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold , 75MHz , 21 bits of TTL data are transmitted at a rate of 525Mbps per LVDS data channel . Using a 75MHz , . 4 RECEIVER SWITCHING CHARACTERISTICS*1 (VDD = 3.0V to 3.6V; TA = -55°C to +125°C); Unless , Position for Bit 4 (Figure 10) Receiver Input Strobe Position for Bit 5 (Figure 10) Receiver Input Strobe , Delay (Figure 7) Receiver Phase Lock Loop Set (Figure 8) Receiver Powerdown Delay (Figure 9) f= 75MHz f= 75MHz


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PDF UT54LVDS218 75MHz MIL-STD-883 48-lead
2003 - Aeroflex UTMC lvds receiver

Abstract: No abstract text available
Text: 15 to 75MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold , 75MHz , 21 bits of TTL data are transmitted at a rate of 525Mbps per LVDS data channel . Using a 75MHz , . Guaranteed by characterization. 4 RECEIVER SWITCHING CHARACTERISTICS1 (VDD = 3.0V to 3.6V; TA = -55°C , Strobe Position for Bit 3 (Figure 10) Receiver Input Strobe Position for Bit 4 (Figure 10) Receiver Input , Loop Set (Figure 8) Receiver Powerdown Delay (Figure 9) f= 75MHz f= 75MHz f= 75MHz f= 75MHz f= 75MHz f= 75MHz


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PDF UT54LVDS218 75MHz MIL-STD-883 48-lead Aeroflex UTMC lvds receiver
m1305 transistor

Abstract: w431 MRF1421C Diode LT 4104 NJT1946A 7082a NJT1949 magnetron 2j42 MSF1422B magnetron 5kw
Text: multiplexer x2 Q uad, * 4 Dual channel multiplexer *2 Hexad, *1 Dual channel multiplexer x3 Q uad, *2 Dual , CHARACTERISTIC Xp [nm] 900 900 V ceo m 40 40 Ic iL T y p . Ee laiA l 12 4 I ceo M ax. [m W /em 2 , Video Cassette Recorder Satellite Receiver A P P L IC A T IO N B R O A D C A ST IN G SY S T E M , 500 6 200 500 6 200 500 5 80 250 6 20 75 4 300 1500 5 80 250 5 80 250 15 0 .2 0.4 10 0.05 0 .2 15 0 .2 , rv /^ s ] 0.17 70 0.5 3 0.5 13 0.5 1 10 1 3 3 4 7 14 5.5 5 12 3 3 3 10 500 500


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PDF NJMOP-07 NJM318 NJM741 NJM2107F NJM2130 NJM425# NJM5534 NJM353 NJM1458 NJM2041 m1305 transistor w431 MRF1421C Diode LT 4104 NJT1946A 7082a NJT1949 magnetron 2j42 MSF1422B magnetron 5kw
2006 - Not Available

Abstract: No abstract text available
Text: 15 to 75MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold , 75MHz , 21 bits of TTL data are transmitted at a rate of 525Mbps per LVDS data channel . Using a 75MHz , . Guaranteed by characterization. 4 RECEIVER SWITCHING CHARACTERISTICS1 (VDD = 3.0V to 3.6V; TA = -55°C , Strobe Position for Bit 3 (Figure 10) Receiver Input Strobe Position for Bit 4 (Figure 10) Receiver Input , Loop Set (Figure 8) Receiver Powerdown Delay (Figure 9) f= 75MHz f= 75MHz f= 75MHz f= 75MHz f= 75MHz f= 75MHz


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PDF UT54LVDS218 75MHz MIL-STD-883 48-lead
2008 - UT54LVDS218

Abstract: No abstract text available
Text: 15 to 75MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold , 75MHz , 21 bits of TTL data are transmitted at a rate of 525Mbps per LVDS data channel . Using a 75MHz , of one second. 4 . Guaranteed by characterization. 4 RECEIVER SWITCHING CHARACTERISTICS1 (VDD = , (Figure 10) Receiver Input Strobe Position for Bit 3 (Figure 10) Receiver Input Strobe Position for Bit 4 , ) Receiver Phase Lock Loop Set (Figure 8) Receiver Powerdown Delay (Figure 9) f= 75MHz f= 75MHz f= 75MHz f= 75MHz


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PDF UT54LVDS218 75MHz MIL-STD-883 48-lead
2008 - 54LVDS218

Abstract: UT54LVDS218 lvds217 Aeroflex UTMC lvds receiver LVDS218
Text: 6.22 6.96 ns RSPos43 Receiver Input Strobe Position for Bit 4 (Figure 10) f= 75MHz , 525Mbps per LVDS data channel . Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). 15 to 75MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold , . Tested functionally. 4 RECEIVER SWITCHING CHARACTERISTICS*1 (VDD = 3.0V to 3.6V; TA = -55°C to , Position for Bit 0 (Figure 10) RSPos13 Receiver Input Strobe Position for Bit 1 (Figure 10) f= 75MHz


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PDF UT54LVDS218 75MHz, 525Mbps 75MHz 54LVDS218 lvds217 Aeroflex UTMC lvds receiver LVDS218
Not Available

Abstract: No abstract text available
Text: Input Strobe Position for Bit 4 (Figure 10) f= 75MHz 8.12 8.86 ns RSPos53 Receiver , bits of TTL data are transmitted at a rate of 525Mbps per LVDS data channel . Using a 75MHz clock, the , . 3. Guaranteed by characterization. 4 . Tested functionally. 4 RECEIVER SWITCHING , Input Strobe Position for Bit 1 (Figure 10) f= 75MHz 2.41 3.15 ns RSPos23 Receiver Input Strobe Position for Bit 2 (Figure 10) f= 75MHz 4.31 5.05 ns RSPos33 Receiver


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PDF UT54LVDS218 75MHz, 525Mbps 75MHz
2001 - Not Available

Abstract: No abstract text available
Text: ) CMOS/TTL High-to-Low Transition Time (Figure 4 ) f= 75MHz Receiver Input Strobe Position for Bit 0 , DD = 3.6 V only. IN D 4 EV EL O PM EN RECEIVER SWITCHING CHARACTERISTICS (V DD = , (Figure 9) Receiver Input Strobe Position for Bit 3 (Figure 9) Receiver Input Strobe Position for Bit 4 , Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 4 , 2001 FEATURES q q q q q q q q q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low


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PDF UT54LVDS218 48-lead
2002 - 54LVDS218

Abstract: UT54LVDS218 LVDS217 marking RAD
Text: RSPos4 Receiver Input Strobe Position for Bit 4 (Figure 10) f= 75MHz 7.89 8.65 ns RSPos5 , temperature specification. 3. Guaranteed by characterization. 4 RECEIVER SWITCHING CHARACTERISTICS (V , Time (Figure 5) 3.5 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 10) f= 75MHz 0.27 1.01 ns RSPos1 Receiver Input Strobe Position for Bit 1 (Figure 10) f= 75MHz 2.18 2.92 ns RSPos2 Receiver Input Strobe Position for Bit 2 (Figure 10) f= 75MHz 4.08 4.82


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PDF UT54LVDS218 48-lead 54LVDS218 LVDS217 marking RAD
2001 - Not Available

Abstract: No abstract text available
Text: Time (Figure 4 ) CMOS/TTL High-to-Low Transition Time (Figure 4 ) f= 75MHz Receiver Input Strobe Position , . 3. Guaranteed by characterization. 4 . Devices are tested @ VDD = 3.6V only. RECEIVER SWITCHING , Position for Bit 4 (Figure 9) Receiver Input Strobe Position for Bit 5 (Figure 9) Receiver Input Strobe , . Figure 10. Receiver LVDS Skew Margin IN D EV EL 9 O PM EN T PACKAGING 5 6 4 , q q q q q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power


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PDF UT54LVDS218 MIL-STD-883
2001 - Not Available

Abstract: No abstract text available
Text: ) CMOS/TTL High-to-Low Transition Time (Figure 4 ) f= 75MHz Receiver Input Strobe Position for Bit 0 , DD = 3.6 V only. IN D 4 EV EL O PM EN RECEIVER SWITCHING CHARACTERISTICS (V DD = , (Figure 9) Receiver Input Strobe Position for Bit 3 (Figure 9) Receiver Input Strobe Position for Bit 4 , q q q q q q q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low , frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel . Using


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PDF UT54LVDS218 48-lead
2002 - 54LVDS218

Abstract: LVDS217
Text: EN LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-) T -100 0.2 -10 -10 -20 4 -15 +100 mV , Position for Bit 3 (Figure 10) Receiver Input Strobe Position for Bit 4 (Figure 10) Receiver Input Strobe , f= 75MHz f= 75MHz f= 75MHz RxCLK IN to RxCLK OUT Delay (Figure 7) Receiver Phase Lock Loop Set , q q q q q q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low , frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel . Using


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PDF UT54LVDS218 48-lead 54LVDS218 LVDS217
2009 - THC63LVD104C

Abstract: thc63lvd104c_rev.1.00_e THC63LVD104A lvds cable lvds to NTSC THC63LV Thine lvds receiver
Text: THC63LVD104C_Rev.1.00_E THC63LVD104C 112MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat , Block Diagram LVDS INPUT CMOS/TTL OUTPUT 7 RC +/RD+/- RCLK+/- RD6-RD0 7 PLL RC6-RC0 , RE0 RD6 RD5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RARA+ RBRB+ LVCC , Type RA+, RA- 50, 49 LVDS IN RB+, RB- 52, 51 LVDS IN RC +, RC - 55, 54 LVDS IN


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PDF THC63LVD104C THC63LVD104C 112MHz 30Bits 35bits 112MHz, 784Mbps thc63lvd104c_rev.1.00_e THC63LVD104A lvds cable lvds to NTSC THC63LV Thine lvds receiver
2009 - FLUKE 179

Abstract: board for fluke 179 MARCONI 2024 C103 C107 GRM1885C1H101J GRM188R71H104K MAX2037 C80-C103 EG1903-ND
Text: CWD receiver , this will take approximately 30µs for 5 bits per channel . 10 4 ) After the shift , Optional Individual Channel 4 x fLO LO Input Drive Capability 269mW Power Consumption per Channel , voltage · Three ammeters · 4-channel , 500MHz oscilloscope (e.g., TEK TDS3054B) Connections , serial shift register. Each channel has a corresponding 5-bit shift register ( 4 bits for phase , register ( 4 bits for phase programming and 1 bit for channel enable), which is used to program the output


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PDF MAX2038 12-bit MAX2037 22nV/Hz MAX2038 FLUKE 179 board for fluke 179 MARCONI 2024 C103 C107 GRM1885C1H101J GRM188R71H104K MAX2037 C80-C103 EG1903-ND
Not Available

Abstract: No abstract text available
Text: 4 -input Differential Receiver A0 A1 S/D EN 2-405 J IT W M ■S51fl4bB 0 0 1 0 0 1 3 ■LT1204 T V P ic m flpp u c m i o n s Differential Receiver Switching Waveforms 4 -lnput Twisted-Pair , 8Vp.p. 4 -Input Differential Receiver LT1204S can be connected inverting and noninverting as shown to make a 4 -input differential receiver . The receiver can be used to convert differential signals , r r u v m . _ LT12Q4 TECHNOLOGY 4 -Input V id e o M u


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PDF LT12Q4 75MHz 30MHz 10MHz: LT1204 10MHz. 40mVP LT1204s 100fl
2013 - R25G2

Abstract: No abstract text available
Text: and Receiver of 4 bits operate to 250MHz. It can be used for a variety of purposes, home appliances , ) RGB10bits dual channel LVDS Receiver and Transmitter 2) Operating frequency range : 20135MHz 3) Power down mode supported. 4 ) Support spread spectrum clock generator. 5) Support reduced swing LVDS for low EMI , ] B1[2] B1[0] RCLK2+/ RA 2+/ RB 2+/ RC 2+/ RD 2+/ RE 2+/ G2[ 4 ] B2[5] DE data11 data12 R2[9] B2[ 4 , Interface IC of ROHM "Serializer" "Deserializer" operates from 20MHz to 135MHz wide clock range, and number


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PDF 70bit BU90RT102 13057EBT08 20MHz 135MHz 250MHz. RGB10bits 20135MHz R1102A R25G2
2010 - LVDS fin 1002

Abstract: BU90RT102 c1005x7r1h222kt GRM155B30G225ME15D Murata grm155r60j225me15d CM05X5R CM05X5R225M04AH GRM155B HSYNC, VSYNC, DE 2NTR
Text: and Receiver of 4 bits operate to 250MHz. It can be used for a variety of purposes, home appliances , ) RGB10bits dual channel LVDS Receiver and Transmitter 2) Operating frequency range : 20135MHz 3) Power down mode supported. 4 ) Support spread spectrum clock generator. 5) Support reduced swing LVDS for low EMI , ] R2[5] R2[ 4 ] RB 2+/ - B2[5] B2[ 4 ] G2[9] G2[8] G2[7] G2[6] G2[5] RC 2+/ - , Interface IC of ROHM "Serializer" "Deserializer" operates from 8MHz to 150MHz wide clock range, and number


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PDF 70bit BU90RT102 10057EAT08 150MHz 250MHz. RGB10bits 20135MHz R1010A LVDS fin 1002 BU90RT102 c1005x7r1h222kt GRM155B30G225ME15D Murata grm155r60j225me15d CM05X5R CM05X5R225M04AH GRM155B HSYNC, VSYNC, DE 2NTR
2009 - MARCONI 2024

Abstract: fluke 179 diagram FLUKE 179 board for fluke 179 capacitor 100nf 50v 0805 Xr7 datasheet capacitor 100nf 50v 0805 Xr7 C103 C107 GRM1885C1H101J GRM188R71H104K
Text: CWD receiver , this will take approximately 30µs for 5 bits per channel . 10 4 ) After the shift , Optional Individual Channel 4 x fLO LO Input Drive Capability 269mW Power Consumption per Channel , output voltage · Three ammeters · 4-channel , 500MHz oscilloscope (e.g., TEK TDS3054B , serial shift register. Each channel has a corresponding 5-bit shift register ( 4 bits for phase , register ( 4 bits for phase programming and 1 bit for channel enable), which is used to program the output


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PDF MAX2036 10-bit MAX2035 60nV/Hz MARCONI 2024 fluke 179 diagram FLUKE 179 board for fluke 179 capacitor 100nf 50v 0805 Xr7 datasheet capacitor 100nf 50v 0805 Xr7 C103 C107 GRM1885C1H101J GRM188R71H104K
2009 - MARCONI 2024

Abstract: capacitor 100nf 50v 0805 Xr7 datasheet FLUKE 83 HP3440 R164-R171 board for fluke 179 FLUKE 83 III schematic fluke 179 fluke 179 diagram max2036evkit
Text: CWD receiver , this will take approximately 30µs for 5 bits per channel . 10 4 ) After the shift , Optional Individual Channel 4 x fLO LO Input Drive Capability 269mW Power Consumption per Channel , output voltage · Three ammeters · 4-channel , 500MHz oscilloscope (e.g., TEK TDS3054B , serial shift register. Each channel has a corresponding 5-bit shift register ( 4 bits for phase , register ( 4 bits for phase programming and 1 bit for channel enable), which is used to program the output


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PDF MAX2036 10-bit MAX2035 60nV/Hz MARCONI 2024 capacitor 100nf 50v 0805 Xr7 datasheet FLUKE 83 HP3440 R164-R171 board for fluke 179 FLUKE 83 III schematic fluke 179 fluke 179 diagram max2036evkit
2009 - MARCONI 2024

Abstract: FLUKE 179 FLUKE 337 FLUKE 83 FLUKE 112 18pf capacitance smd tdk chn 4539 FLUKE 83 FLUKE C103 C107
Text: CWD receiver , this will take approximately 30µs for 5 bits per channel . 10 4 ) After the shift , Optional Individual Channel 4 x fLO LO Input Drive Capability 269mW Power Consumption per Channel , voltage · Three ammeters · 4-channel , 500MHz oscilloscope (e.g., TEK TDS3054B) Connections , serial shift register. Each channel has a corresponding 5-bit shift register ( 4 bits for phase , register ( 4 bits for phase programming and 1 bit for channel enable), which is used to program the output


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PDF MAX2038 12-bit MAX2037 22nV/Hz MAX2038 MARCONI 2024 FLUKE 179 FLUKE 337 FLUKE 83 FLUKE 112 18pf capacitance smd tdk chn 4539 FLUKE 83 FLUKE C103 C107
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