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74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Text: Flip-Flops 74LS112 , S112 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE §D Asynchronous set , are initiated by the HIGH-to-LOW transition of CP. TYPE 74LS112 74S112 TYPICAL i MAX 45MHz 125MHz , In. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) ®,[I «,E · > iE * o iG E 0,11 , Product Specification Flip-Flops 74LS112 , S112 DC ELECTRICAL CHARACTERISTICS PARAMETER (Over recommended operating free-air temperature range unless otherwise noted.) 74LS112 TEST CONDITIONS1 Min Typ2


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PDF 1N916, 1N3064, 500ns 500ns 74ls112 pin diagram 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
74ls112 pin diagram

Abstract: 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform N74S112N N74S112D N74LS112N N74LS112D 74S112
Text: Specification Flip-Flops 74LS112 , S112 LOGIC DIAGRAM FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS , Signetics Logic Products 74LS112 , S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product , HIGH-to-LOW transition of CP. TYPE TYPICAL fHAX TYPICAL SUPPLY CURRENT (TOTAL) 74LS112 45MHz 4mA 74S112 , -2.0mA lIL, and a 74LS unit load (LSul) is 20//A l,H and -0.4mA lIL. PIN CONFIGURATION LOGIC SYMBOL , otherwise noted.) PARAMETER TEST CONDITIONS1 74LS112 74S112 Min Typ2 Max Min Typ2 Max UNIT


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PDF 74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform N74S112N N74S112D N74LS112N N74LS112D 74S112
74ls112 pin diagram

Abstract: 74ls112 pin configuration 74ls112 function table 74LS112 74S112 74ls112 waveform N74LS112N N74S112N N74LS112D 74LS
Text: 74LS112 , S112 LOGIC DIAGRAM FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd CP J K Q Q , Signetics 74LS112 , S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , the HIGH-to-LOW transition of CP. TYPE TYPICAL fHAX TYPICAL SUPPLY CURRENT (TOTAL) 74LS112 45MHz 4mA , 50nA l,H and -2.0mA l,L, and a 74LS unit load (LSul) is 20,uA l,H and -0.4mA l,L. PIN CONFIGURATION , Logic Products Product Specification Flip-Flops 74LS112 , S112 DC ELECTRICAL CHARACTERISTICS (Over


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PDF 74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74ls112 pin configuration 74ls112 function table 74LS112 74S112 74ls112 waveform N74LS112N N74S112N N74LS112D 74LS
74ls112 pin configuration

Abstract: 74ls112 function table 74LS112 74S112
Text: Signetics 74LS112 , S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , the HIGH-to-LOW transition of CP. TYPE 74LS112 74S112 TYPICAL f , AX 45MHz 125MHz TYPICAL SUPPLY , 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) & ,|T K ,d JiOE ®Dl[Z o ,d ' Q , 74LS112 , S112 FUNCTION TABLE INPUTS OPERATING MODE Sd Asynchronous set Asynchronous reset (clear , Product S pecification Flip-Flops 74LS112 , S112 DC ELECTRICAL CHARACTERISTICS PARAMETER (Over


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PDF 74LS112, 1N916, 1N3064, 500ns 500ns 74ls112 pin configuration 74ls112 function table 74LS112 74S112
Not Available

Abstract: No abstract text available
Text: GD54/ 74LS112 DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH SET AND RESET Features Pin C o n fig u ra tio n • Negative edge-triggering • Diode clamped inputs • Independent input/output terminals for each flip-flop. • Direct set and reset inputs • Q and Q outputs Vcc , pulse. Block Diagram (Each Flip Flop) CLOCK INPUT 4 -8 8 z 2Q CK K This device , / 74LS112 Absolute Maximum Ratings • S u p p ly v o lta g e , V cc .


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PDF GD54/74LS112
74LS412

Abstract: 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112
Text: Signetics 74LS112 , S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , the HIGH-to-LOW transition of CP. TY PE 74LS112 74S 112 TY P IC A L f MAx 45M H z 125M H z T Y P , 10Su! 74LS 4LSul 3LSul 1LSul 10LSul D ata inputs O utputs PIN CONFIGURATION LOGIC SYMBOL , ro d u c t S p e c ific a tio n Flip-Flops 74LS112 , 5112 DC ELECTRICAL CHARACTERISTICS PA R , ro d u c t S p e c ific a tio n Flip-Flops 74LS112 , S112 AC SET-UP REQUIREMENTS PA R A M E


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PDF 74LS112, 500ns 500ns 74LS412 74LS41 74ls112n 74LS112D 74ls112 pin configuration 74LS112
74LS112P

Abstract: 74LS112D 74ls112 pin diagram 74LS112PC 74LS112 74s112p 74LS112DC 54S112DM 74LS112F S4 74
Text: 112 /54S/74S112 0//oû'7 \/54LS/ 74LS112 b/zooL DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP , Level L = LOW Voltage Level ORDERING CODE: See Section 9 CONNECTION DIAGRAM PINOUT A cp, [7 Ki (T , vcc ÎFlCpi ï7|CD2 13] CPs ÏU k2 Tt] J2 ÏÔ]Sd2 T]o2 LOGIC SYMBOL PKGS PIN OUT COMMERCIAL GRADE , €”9 1-0 CP 13—O CP 2— K _ Cd 0 K Q Cd 0-7 15 Vcc = Pin 16 GND = Pin 8 INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions PIN NAMES DESCRIPTION 54/74S (U.L.) HIGH/LOW 54/74LS (U.L.) HIGH


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PDF /54S/74S112 \/54LS/74LS112 54/74LS 54/74S S4/74LS 74LS112P 74LS112D 74ls112 pin diagram 74LS112PC 74LS112 74s112p 74LS112DC 54S112DM 74LS112F S4 74
8 pin dip j k flipflop ic

Abstract: 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram
Text: 00b37fl7 S | T-lk-07-0 7 112 CO NN ECTIO N DIAGRAM PINOUT A 54S/74S112 54LS/ 74LS112 , - ORDERING CODE: See Section 9 PIN PKGS Plastic DIP (P) C eram ic DIP (D) Flatpak (F) O UT A A A . C O M M , 54S112DM, 54LS112DM 54S112FM, 54LS112FM Vcc = Pin 16 G N D = Pin 8 6B 4L INPUT LO AD IN G /FAN -O U T: See Section 3 fo r U.L. definitions PIN NAMES J1, J2, K1, «2 CP1, CP2 C d i . CD2 S01, SD2_ Q i , 02 , } GEE D | b'SDUSS 0Db37flfi 7 | T 'LO G IC DIAGRAM (one half shown) y t 0 7 o ? CP DC CH


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PDF 00b37fl7 T-lk-07-0 54S/74S112 54LS/74LS112 54/74S 54/74LS 8 pin dip j k flipflop ic 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram
Not Available

Abstract: No abstract text available
Text: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/ 74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs are enabled and data w ill be , 2— ORDERING CODE: See Section 9 PIN 10 1 112 LOGIC DIAGRAM (one half shown) CP , . definitions PIN NAMES J1, J2, K l, K2 CP1. CP2 C di , CD2 S d i , Sd 2 Q i , Q 2, Q i, Q 2


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PDF 54S/74S112 4LS/74LS112 54/74LS 54/74S
74ls112 pin diagram

Abstract: No abstract text available
Text: tpLH^tpHL V q q (Op r .)= 2 V ^ 6 V Pin and Function Compatible with 74LS112 ' ABSOLUTE MAXIMUM , ”L "L _r H H TOGGLE NO CHANGE X : LOGIC DIAGRAM NO CHANGE D o n 't c a r e


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PDF TC74HC112P/F 74HC112P/F TC74HC112 TC74H C112P/F 74ls112 pin diagram
74HC112 pin diagram

Abstract: 74ls112 function table 74HC112
Text: (OPR) = 2 to 6V a PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS112 DESCRIPTION The M54/74HC112 is a high , excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal , FUNCTION Q H L H CLEAR PRESET OH H L Qn On NO CHANGE TOGGLE NO CHANGE LOGIC DIAGRAM (1/2 , Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC V qq or


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PDF M54HC112 M74HC112 M74HC112 54/74LS112 M54/74HC112 M54/74HC112 74HC112 pin diagram 74ls112 function table 74HC112
74ls112 pin diagram

Abstract: M54HC112 M54HC112F1R M74HC112 M74HC112B1R M74HC112C1R M74HC112M1R
Text: VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS112 B1R (Plastic Package) F1R , . PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection , Care PIN DESCRIPTION IEC LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 13 1CK , Reset inputs 8 16 GND V CC Ground (0V) Positive Supply Voltage LOGIC DIAGRAM (1/2 Package , mA mA IO DC Output Source Sink Current Per Output Pin ± 25 mA DC VCC or Ground


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PDF M54HC112 M74HC112 54/74LS112 M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R M54/74HC112 74ls112 pin diagram M54HC112 M54HC112F1R M74HC112 M74HC112B1R M74HC112C1R M74HC112M1R
74HC112 pin diagram

Abstract: 74hc112 IC 74HC112 74ls112 waveform 74HC74 M74HC112 74ls112 function table M54HC112F1 M54HC112 74HC
Text: RANGE Vcc (OPR) = 2 to 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS112 DESCRIPTION The M54/74HC112 , M74HC112 C1 M74HC112 B1N M74HC112 M1 M74HC112 F1 PIN CONNECTIONS (top view) 1PR NC IQ 75 D' D , an On NO CHANGE X: DON'T CARE I i LOGIC DIAGRAM (1/2 Package) ABSOLUTE MAXIMUM RATINGS Symbol


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PDF M54HC112 M74HC112 54/74LS112 M54/74HC112 M54HC112/M74HC112 M54/74HC112 K50V- 74HC112 pin diagram 74hc112 IC 74HC112 74ls112 waveform 74HC74 M74HC112 74ls112 function table M54HC112F1 74HC
1994 - IC 74HC112

Abstract: 74ls112 pin diagram 74ls112 function table 74LS112 JK EDGE TRIGGERED FLIP FLOP JK flip flop IC diagram M54HC112F1R Toggle flip flop IC M74HC112B1R M74HC112C1R M74HC112M1R
Text: VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS112 B1R (Plastic Package) F1R , . PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection , Care PIN DESCRIPTION IEC LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 13 1CK , Reset inputs 8 16 GND V CC Ground (0V) Positive Supply Voltage LOGIC DIAGRAM (1/2 Package , mA mA IO DC Output Source Sink Current Per Output Pin ± 25 mA DC VCC or Ground


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PDF M54HC112 M74HC112 54/74LS112 M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R M54/74HC112 IC 74HC112 74ls112 pin diagram 74ls112 function table 74LS112 JK EDGE TRIGGERED FLIP FLOP JK flip flop IC diagram M54HC112F1R Toggle flip flop IC M74HC112B1R M74HC112C1R M74HC112M1R
74ls112 function table

Abstract: No abstract text available
Text: Range- -Vcc (opr.) =2 V ~ 6V · Pin and Function Compatible with 74LS112 · · · · · 'C C 1K 1J 1M , Handbook. 1997 08-07 - 1/6 TOSHIBA TC74HC112AP/AF/AFN SYSTEM DIAGRAM H> [>- Q


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PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 16PIN 200mil 74ls112 function table
IC 74HC112

Abstract: H74HC112 74LS112 J-K flip flop clock inputs 54HC 74HC M54HC112 M74HC112 H11L 74ls112 pin diagram
Text: (opr) = 2V to 6V Pin and Function compatible with 54/ 74LS112 TRUTH TABLE INPUTS OUTPUT preset , Chip Carrier ORDERING NUMBERS: M54HC112 F1 M74HC112 B1 M74HC112 F1 M74HC112 C1 PIN CONNECTIONS (top , H74HC112 LOGIC DIAGRAM (1/2 Package) j clock- _ o— • o c> - * . E> -O-9 PR£SET _ £> .  , DC Output Source Sink Current Per Output Pin ± 25 mA ice or 'gnd DC Vcc or Ground Current ± 50 mA


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PDF M54HC112 H74HC112 M54/74HC112 M54HC112/M74HC112 IC 74HC112 H74HC112 74LS112 J-K flip flop clock inputs 54HC 74HC M54HC112 M74HC112 H11L 74ls112 pin diagram
Not Available

Abstract: No abstract text available
Text: – WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2 to 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS112 , DESCRIPTION PIN CONNECTIONS (top view) The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH , j r X: DON’T CARE LOGIC DIAGRAM (1/2 Package) s > > j- o - £> + 3 - , mA >0 DC Output Source Sink Current Per Output Pin ± 25 mA !CC or 'GND Pd Tstg


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PDF 280/o 54/74LS112 74HC112 S-10216
Not Available

Abstract: No abstract text available
Text: tPLH = tPHL ■WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS112 M1R C1R (Micro Package) (Chip Carrier) ORD ER COOES , voltage. M74HC112M1R M74HC112C1R PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT , TOGGLE H H H X X _r Qn Qn NO CHANGE X: Don’t Care PIN DESCRIPTION PIN , (0V) 16 Vcc Positive Supply Voltage 6, 7 > > LC1 390 LOGIC DIAGRAM (1/2 Package


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PDF 54/74LS112 M54HC112F1R M74HC112B1R M54/74H M54/M74HC112
2006 - 74LS112

Abstract: TC74HC112AF TC74HC112AFN TC74HC112AP
Text: Pin and function compatible with 74LS112 Pin Assignment TC74HC112AFN Weight DIP16-P , Toggle H H X X Qn Qn No Change No Change X: Don't care System Diagram 2


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PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A 74LS112 TC74HC112AFN
2006 - Not Available

Abstract: No abstract text available
Text: ) = 2 to 6 V • Pin and function compatible with 74LS112 Pin Assignment TC74HC112AFN , care System Diagram 2 2006-06-01 TC74HC112AP/AF/AFN Absolute Maximum Ratings (Note 1


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PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A
74ls112 function table

Abstract: ph c5V diode 74LS112 J-K flip flop clock inputs
Text: Voltage Range . . V^ Q ( 0 p r .)=2V % 6V · Pin and Function Compatible with 74LS112 ' ABSOLUTE MAXIMUM RATINGS ! °1 ; . .' ·' '^ ! 1 1 PARAMETER Supply Voltage , MFP16( F l 6 0 C - P ) S ' - PIN ASSIGNMENT V V mA mA mA mA mW 10K IK 1J 1ER IQ, IQ °C °C 2 Q


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PDF TC74HC112P/F TC74HC112P/F TC74HC112 58MHz 74ls112 function table ph c5V diode 74LS112 J-K flip flop clock inputs
74LS112

Abstract: TC74HC112AF TC74HC112AFN TC74HC112AP 74ls112 function table
Text: Delays.tPLH—tPHL • Wide Operating Voltage Range-—Vcc (opr.) = 2V~6V • Pin and Function Compatible with 74LS112 TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR J K CK Q Q L H X X X L H CLEAR H L X X X H L , . P ( DIPI 6-P-300-2.54A ) Weight : 1.00g (Typ.) 16 F (SOP16-P-300-1.27) Weight: 0.18g (Typ.) PIN , Reliability Handbook. 1997-08-07 1/6 TOSHIBA TC74HC112AP/AF/AFN SYSTEM DIAGRAM CK —O—pc[>- -<>-l>â


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PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 75MAX 735TYP 74LS112 TC74HC112AF TC74HC112AFN TC74HC112AP 74ls112 function table
74ls112 function table

Abstract: 16PIN 74LS112 TC74HC112AF TC74HC112AFN TC74HC112AP 74ls112 pin diagram
Text: (opr.) = 2V~6V • Pin and Function Compatible with 74LS112 TRUTH TABLE INPUTS OUTPUTS FUNCTION , .) PIN ASSIGNMENT 1CK 1 c HH ] 16 VCC 1K 2 [ ] 15 1CLR 1J 3 C ] 14 2CLR 1PR 4 £ ] 13 2CK 1Q 5  , (SOP16-P-300-1.27) Weight: 0.18g (Typ.) 1 2001-05-17 TOSHIBA TC74HC112AP/AF/AFN SYSTEM DIAGRAM CK


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PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 74ls112 function table 16PIN 74LS112 TC74HC112AF TC74HC112AFN TC74HC112AP 74ls112 pin diagram
2007 - Not Available

Abstract: No abstract text available
Text: Wide operating voltage range: VCC (opr) = 2 to 6 V Pin and function compatible with 74LS112 Pin , Diagram 2 2006-06-01 TC74HC112AP/AF/AFN Absolute Maximum Ratings (Note 1) Characteristics


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PDF TC74HC112AP/AF/AFN TC74HC112AP TC74HC112AF TC74HC112AFN TC74HC112A
74LS112

Abstract: No abstract text available
Text: .) = 67MHz (typ.) at V CC = 5V nh PIN ASSIGNMENT · Low Power Dissipation.Ice = 2 , Balanced Propagation Delays tpu-i-tpHL · Wide Operating Voltage Range-" Vcc (opr.) = 2 V ~ 6V · Pin and Function Compatible with 74LS112 oh lo L 1CK 1K 1J 1PR 1Q 1Q 2Q GND 1 £ 2 £ ] 16 Vcc ] 15 1CLR , /AF/AFN SYSTEM DIAGRAM CK - P>0- -T-<£> 4 > -[ > ° - Q Q 961001 EBA2' 9 0 # The


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PDF TC74HC112AP/AF/AFN TC74HC112AP, TC74HC112AF, TC74HC112AFN TC74HC112A 16PIN DIP16-P-300-2 16PIN 200mil 74LS112
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