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74hc74 pin diagram Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2012 - 74HC74

Abstract:
Text: 74HC74 ; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 4 - 27 August 2012 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge , voltages in excess of VCC. 2. Features and benefits Input levels: For 74HC74 : CMOS level For 74HCT74 , leads (300 mil) Version SOT27-1 Type number NXP Semiconductors 74HC74 ; 74HCT74 Dual D-type , ; 14 terminals; body 2.5 3 0.85 mm 4. Functional diagram 1SD SD D CP FF Q 4 10 1SD 2SD 2 12 3 11


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PDF 74HC74; 74HCT74 74HC74 74HCT74 HCT74 74hc74 pin diagram 74HC74 application 74HCT74DB 74HC74P 74HC74N 74HC74DB 74HC74BQ 74HC74 application note
2013 - Not Available

Abstract:
Text: diagram © NXP B.V. 2013. All rights reserved. 2 of 20 74HC74 -Q100; 74HCT74-Q100 NXP , 74HC74 -Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 2 — 6 September 2013 Product data sheet 1. General description The 74HC74 -Q100; 74HCT74 , levels:  For 74HC74 -Q100: CMOS level  For 74HCT74-Q100: TTL level  Symmetrical output , )  Multiple package options 74HC74 -Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type


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PDF 74HC74-Q100; 74HCT74-Q100 74HCT74-Q100
2012 - Not Available

Abstract:
Text: 74HC74 -Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 1 — 7 August 2012 Product data sheet 1. General description The 74HC74 -Q100; 74HCT74-Q100 are , levels:  For 74HC74 -Q100: CMOS level  For 74HCT74-Q100: TTL level  Symmetrical output , )  Multiple package options 74HC74 -Q100; 74HCT74-Q100 NXP Semiconductors Dual D-type , diagram 4 2 3 1SD 1D 1CP SD Q D Q 4 10 3 1SD 2SD 2 2 12 3 11 SD


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PDF 74HC74-Q100; 74HCT74-Q100 74HCT74-Q100
2012 - 74HC74

Abstract:
Text: 74HC74 -Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 1 - 7 August 2012 Product data sheet 1. General description The 74HC74 -Q100; 74HCT74-Q100 are dual , 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC74 -Q100: CMOS level For 74HCT74 , ) Multiple package options NXP Semiconductors 74HC74 -Q100; 74HCT74-Q100 Dual D-type flip-flop with , terminals; body 2.5 3 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Type number 4. Functional diagram 1SD


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PDF 74HC74-Q100; 74HCT74-Q100 74HCT74-Q100 74HC74 74HC74-Q100 74HC74 application note 74HC74BQ 74hc74 pin diagram TTL 74hc74 Current 74HCT74 CI 74hc74 74HCT74 74HC74 application
2007 - HC74G

Abstract:
Text: , 2007 February, 2007 - Rev. 0 1 Publication Order Number: 74HC74 /D 74HC74 PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 1 14 VCC RESET 1 DATA 1 2 13 RESET 2 CLOCK 1 3 , 74HC74 Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The 74HC74 is , Q2 Q2 10 PIN 14 = VCC PIN 7 = GND H L L H H* H* H L L H No Change No Change No , to GND) ­ 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA mA Iout DC


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PDF 74HC74 74HC74 SOIC-14 74HC74/D HC74G 74HC74 application 74HC74 application note 74HC74D 74HC74DG 74hc74 pin diagram 74HC74D-T TTL 74hc74 74HC74DR2G
2007 - 74hc74

Abstract:
Text: : 74HC74 /D 74HC74 PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 RESET 1 1 14 VCC DATA 1 2 , RESET Figure 5. EXPANDED LOGIC DIAGRAM http://onsemi.com 5 74HC74 PACKAGE DIMENSIONS SOICâ , 74HC74 Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS The 74HC74 , X X X H L X X X Q Q SET 2 10 PIN 14 = VCC PIN 7 = GND H L L H H* H* H , + 0.5 V Iin DC Input Current, per Pin ±20 mA mA Iout DC Output Current, per


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PDF 74HC74 74HC74 74HC74/D HC74G
2003 - 74HC74

Abstract:
Text: ; positive-edge trigger 74HC74 ; 74HCT74 PINNING PIN SYMBOL DESCRIPTION 1 1RD asynchronous , INTEGRATED CIRCUITS DATA SHEET 74HC74 ; 74HCT74 Dual D-type flip-flop with set and reset , 74HC74 ; 74HCT74 FEATURES GENERAL DESCRIPTION · Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL , total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. For 74HC74 the condition is VI


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PDF 74HC74; 74HCT74 74HC/HCT74 SCA75 613508/03/pp22 74HC74 74HC74 application note 74HCT74 74HCT74 DATASHEET 74HC74N 74HC74 datasheet Current 74HCT74 74hc74 pin diagram 74HC74 application TTL 74hc74
74HC74

Abstract:
Text: GD54/ 74HC74 , GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description , characteristic of CMOS • Diode protection on all inputs Pin Configuration 1CLR [~T~ u m] vcc 1 D [~2 , Package Logic Diagram S 4 2 ID Ó PR 1 Q 3 1 CLK CLK FF1 Q CLR ? 10 6 1 CLR 9 , diagram Function Table INPUTS OUTPUTS PR CLR CLK nD nQ nQ L H X X H L H L X X L H L L X X H H , transition 4-89 This Material Copyrighted By Its Respective Manufacturer GD54/ 74HC74 , GD54/74HCT74


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PDF GD54/74HC74, GD54/74HCT74 54/74LS74. 74HC74 74ls74 timing setup hold 74hc74 pin diagram 74LS74 PINOUT 74HC74 pin configuration 74hct74 Current 74HCT74 TTL 74hc74 GD74HCT74 74HC
74HC74

Abstract:
Text: GD54/ 74HC74 , GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description , immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration ICLR[~T u h]vcc , Logic Diagram 5 4 2 iPB ID h PB D Q CLK F F1 Q CLR 9 IQ 3 1 CLK IQ 6 'CCS 9 10 , diagram Function Table INPUTS OUTPUTS PR CLR CLK nD nQ nQ L H X X H L H L X X L H L L X X H H , transition 3-23 4DSÖ7S7 QQ042Ö7 ISO ■GD54/ 74HC74 , GD54/74HCT74 Absolute Maximum Ratings SYMBOL


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PDF GD54/74HC74, GD54/74HCT74 54/74LS74. 00042T1 402A757 DQ042T2 74HC74 74hct74 74LS74 pinout 74HC74 pin configuration 74hc74 pin diagram TTL 74hc74 74ls74 timing setup hold GD74HCT74 Current 74HCT74 000M2AA
74HC74

Abstract:
Text: M74HC74 M1 M74HC74 F1 PIN CONNECTIONS (top view) DESCRIPTION The M54/ 74HC74 is a high speed CMOS DUAL D , CARE October 1988 1/5 139 M54/ 74HC74 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol , PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 M1 Micro Package 1 B1N Plastic Package F1 Ceramic Frit , DC Output Source Sink Current Per Output Pin DC Vcc or Ground Current Power Dissipation Storage , " '/#» MiBB8>[?[LïCW®MCS Æ 7 SGS-THOMSON M54/ 74HC74 DC SPECIFICATIONS TA = 25°C 54HC and


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PDF 54/74LS74 M54HC74 M74HC74 M54/74HC74 74HC74 of 74HC74 ic 54HC74 pin DIAGRAM OF IC 74HC74 74hc74 pin diagram 74ls74 ic chip IC 74hc74
of 74HC74 ic

Abstract:
Text: PROPAGATION DELAYS tPLH = tpHL ■WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2V to 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 DESCRIPTION The M54/ 74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH , PIN CONNECTIONS (top view) 1CLR [7 1D [7 1 CK [J 1 PR 1 a 10 [s GND [T 3 [I a ia u u ICE , October 1988 1/5 139 This Material Copyrighted By Its Respective Manufacturer I M54/ 74HC74 I LOGIC DIAGRAM f ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vcc Supply Voltage -0.5 to 7 V V| DC


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PDF M54HC74 M74HC74 54/74LS74 M54/74HC74 M54/74HC74 of 74HC74 ic 74HC74 IC 74hc74 pin DIAGRAM OF IC 74HC74 74hc74 pin diagram M74HC74 GIJ diode 74ls74 ic chip 74HC
Not Available

Abstract:
Text: Connection 1/5 139 I M54/ 74HC74 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol , tPLH = tpHL WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 , NUMBERS: M54HC74 F1 M74HC74 C1 M74HC74 B1N M74HC74 M1 M74HC74 F1 PIN CONNECTIONS (top view) DESCRIPTION The M54/ 74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH PRESETANDCLEARfabricated in silicon , Pin ± 25 mA ■o icc or Ignd ± 50 mW - 6 5 to 150 Storage Temperature Tstg


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PDF M54HC74 M74HC74 54/74LS74 M54HC74 M74HC74 M54/74HC74 M54/74HC74
ic 74 hc 10

Abstract:
Text: GD54/ 74HC74 , GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These , operation over wide temperature ranges to meet in­ dustry and military specifications. Pin , Table Logic Diagram OUTPUTS INPUTS PR CLR CLK nD nQ nQ L H L H L L X , Logic diagram H L X t Qn+1 H H = = = = = t r L H L H Qn+1 H L HIGH , CLK transition 4 -8 9 GD54/ 74HC74 , GD54/74HCT74 Absolute Maximum Ratings PARAMETER


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PDF GD54/74HC74, GD54/74HCT74 ic 74 hc 10
74hc74an

Abstract:
Text: . Technical Data File Number 1476 High-Speed CMOS Logic CD54/ 74HC74 CD54/74HCT74 T-HU'O^-DB HARRIS SEMICOND SECTOR 5~Vee « PIN 14 «NO « PIN 7 92CS-369S5BI FUNCTIONAL DIAGRAM 27E D B 4302271 DD17Slb M , pin compatible with the standard 54LS/74LS logic family. The CD54HC74 and CD54HCT74 are supplied in 14 , . 1 — Logic Diagram H = High Level (Steady State) L = Low Level (Steady State) X = Don't Care â , Technical Data_ T-46-07-08 CD54/ 74HC74 CD54/74HCT74 MAXIMUM RATINGS, Absolute-Maximum Values: DC


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PDF CD54/74HC74 CD54/74HCT74 92CS-369S5BI DD17Slb RCA-CD54/74HC74and 92CS-36967 T-46-07-08 D54/74H 74hc74an 74HC74 CD74HC74 CI 74hc74 74hc74 pin diagram Current 74HCT74 74hc74c CD54HC74 CD54HCT74 CD74HCT74
M74HC74

Abstract:
Text: OPERATING VOLTAGE RANGE Vcc (OPR) = 2V to 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 FI , M74HC74 C1 M74HC74 M1 M74HC74 B1N M74HC74 F1 PIN CONNECTIONS (top view) DESCRIPTION Thè M54/ 74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH PRESETANDCLEARfabricated in silicon gate C2MOS , 1/5 139 * M54/ 74HC74 ® ® 7^2^237 003^005 21b ■S6TH S G S-THOMSON LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value - 0.5 to 7 Unit DC Input


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PDF 54/74LS74 M54/74HC74 M74HC74
74HC74

Abstract:
Text: . Fig. 1 - Logic Diagram 109 Technical Data CD54/ 74HC74 CD54/74HCT74 MAXIMUM RATINGS , Technical Data File Number 1476 CD54/ 74HC74 CD54/74HCT74 High-Speed CMOS Logic Dual D , QMO » P!W 7 9ÎCS-36965m FUNCTIONAL DIAGRAM TheRCA-CD54/74HC74andCD 54 , level at the appropriate input. The 54HCT/74HCT logic family is functionally as well as pin compatible , - - 2Q ZQ 92CS 3 6 9 6 4 110 Technical Data CD54/ 74HC74 CD54/74HCT74 ST A TIC ELE C


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PDF CD54/74HC74 CD54/74HCT74 CS-36965m TheRCA-CD54/74HC74andCD 54/74HCT74utilizesilicongate indepe125 54HCT 74HCT COS4/74HC74 74HC74 of 74HC74 ic IC 74hc74 pin DIAGRAM OF IC 74HC74 74hc74an
74hc74an

Abstract:
Text: Technical Data File Number » E l 3fl7SDfll 00114Tb 7 | ~ D T-4fc-07-<?5 1476 CD54/ 74HC74 CD54 , 5V, CL = 15 pF, 7* = 25°C A R ^ - 0 F /F -2 > -* 0 s Y Vrf. a H H 14 «NO « PIN T 9ZCS- 3 6965R I CLOCX - >CP SET - - FUNCTIONAL DIAGRAM The RCA-CD54/74HC74andCD54/74HCT74 utilize silicongate , input. The 54HCT/74HCT logic fam ily is functionally as well as pin compatible with the standard 54LS , - 369 6 6 Fig. 1 - Logic Diagram NOTÉS: QO = the level of Q before the indicated input


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PDF 00114Tb T-4fc-07-< CD54/74HC74 CD54/74HCT74 6965R 3A750A1 74hc74an 74HC74 74HCT74 74HCT74 truth table Current 74HCT74
1995 - 75HC04

Abstract:
Text: designed in a 1.4µm CMOS process. As illustrated in the functional block diagram , Figure 2, the HI5710 is , mode, controlled by the TESTMODE input pin , where the output data bits are held at known fixed logic , connected The operation of the part is depicted in the timing diagram of Figure 3. There is a 3 cycle , . Evaluation Board Block Diagram CLOCK CLK OUT 1/16 MM 2.5V REF 2.0V +2 JP1 4.0V VRT , +5VA +5VD Application Note 9511 Functional Block Diagram + S/H AMP VIN 39 x8 12


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PDF AN9511 HI5710 HI5710 10-bit, HA5020 CA158A REF03 74HC541 75HC04 Multivibrator 74HC74 74HC221 Multivibrator 74HC00 AN9102 spst push button switch BNC-144 74HC74 schematic application 74HC00 harris 74hc741
1999 - Multivibrator 74HC74

Abstract:
Text: . As illustrated in the functional block diagram , Figure 2, the HI5710 is a 2-step A/D converter , input pin , where the output data bits are held at known fixed logic levels to facilitate in-circuit , the part is depicted in the timing diagram of Figure 3. There is a 3 cycle clock delay from the analog input sampling point to the corresponding digital output data. Evaluation Board Block Diagram , +5VA +5VD Application Note 9511 Functional Block Diagram + S/H AMP VIN 39 x8 12


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PDF AN9511 HI5710 HI5710 10-bit, Multivibrator 74HC74 75HC04 Multivibrator 74HC00 74HC74 schematic application 74HC74 AN9214 AN9511 spst push button AN890 AN9214.2
1995 - 75HC04

Abstract:
Text: designed in a 1.4µm CMOS process. As illustrated in the functional block diagram , Figure 2, the HI5710 is , mode, controlled by the TESTMODE input pin , where the output data bits are held at known fixed logic , connected The operation of the part is depicted in the timing diagram of Figure 3. There is a 3 cycle , . Evaluation Board Block Diagram CLOCK CLK OUT 1/16 MM 2.5V REF 2.0V +2 JP1 4.0V VRT , +5VA +5VD Application Note 9511 Functional Block Diagram + S/H AMP VIN 39 x8 12


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PDF AN9511 HI5710 HI5710 10-bit, HA5020 CA158A REF03 74HC541 75HC04 Multivibrator 74HC00 74HC74 schematic application AN9511 74hc741 74HC00 harris spst push button AN8906 AN9214 74hc221
1998 - 74HC74

Abstract:
Text: CD54/ 74HC74 , CD54/74HCT74 Data sheet acquired from Harris Semiconductor SCHS124B January 1998 - , at the appropriate input. The HCT logic family is functionally as well as pin compatible with the , Handling Procedures. Copyright © 2002, Texas Instruments Incorporated 1 CD54/ 74HC74 , CD54/74HCT74 , 1Q 6 GND 7 14 VCC 13 2R 12 2D 11 2CP 10 2S 9 2Q 8 2Q Functional Diagram 1 RESET 2 DATA 3 CLOCK 4 SET RESET 13 R D 11 CLOCK 10 F/F 2 CP S SET 8 Q GND = PIN 7 VCC = PIN 14 D F/F 1 CP S 6 Q R 5 Q 12


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PDF CD54/74HC74, CD54/74HCT74 SCHS124B HCT74 74HC74 CI 74hc74 IC 74hc74 of 74HC74 ic pin DIAGRAM OF IC 74HC74 TTL 74hc74 74HCT74 truth table HC-36/74HCT74 of 74HC74 ic harris
74HC74

Abstract:
Text: ; positive-edge trigger 74HC74 ; 74HCT74 FEATURES GENERAL DESCRIPTION · Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low , Volts; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. For 74HC74 the , reset; positive-edge trigger 74HC74 ; 74HCT74 FUNCTION TABLES Table 1 See note 1 INPUT , Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74


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PDF 74HC74; 74HCT74 74HC/HCT74 EIA/JESD22-A114-A OT108-1 076E06 MS-012 74HC74 Current 74HCT74 74HCT74 74HC74N 74HCT74N 74HCT74DB 74HCT74D CI 74hc74 74HC74DB 74HC74D
74HC74

Abstract:
Text: ; positive-edge trigger 74HC74 ; 74HCT74 FEATURES GENERAL DESCRIPTION · Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low , Volts; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. For 74HC74 the , reset; positive-edge trigger 74HC74 ; 74HCT74 FUNCTION TABLES Table 1 See note 1 INPUT , Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74


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PDF 74HC74; 74HCT74 74HC/HCT74 EIA/JESD22-A114-A OT108-1 076E06 MS-012 74HC74 74HCT74 74HCT74N 74HC74D 74HC74DB 74HC74N 74HCT74DB 74HCT74D 74HC74PW TTL 74hc74
1996 - 74HC04

Abstract:
Text: 0.22µF ceramic capacitor 1µF ceramic capacitor 18- pin header Open 2- pin jumpers LEDs 10k, 5% resistors 470k, 5% resistor 620, 5% resistors 10k, 9- pin SIP resistor 100k, 9- pin SIP resistor Maxim MAX196BCNI 74HC74 dual flip-flop 74HC04 hex inverter Maxim MXL1014CN quad op amps 74HC574 octal latch Table 1 , 1. MAX196 Stand-Alone Demo Circuit Timing Diagram 2 , +5V R3 470k 74HC74 RDDEMO 4 3 2 1 S Q >CLK D Q R GND BYPASS CAPACITORS OPAMPV+ C9 0.1µF C8 1µF 14 D11


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PDF MAX196 12-bit, 16-bit MAX198. MAX198, 74HC04 circuit using 74hc574 .h116 MAX196BCNI H118 H117 D1 h116 74HC74 of capacitor 0.1uf
2001 - 74HC74

Abstract:
Text: Connect the other end of the wire soldered to pin 5 of the 74HC125 at U7 to pin 12 of the 74HC74 device , convenient to solder to. Figure 2: Modifications to pin 12 of the 74HC74 at U3 5 6 Remove the , Connect the other end of the wire soldered to pin 5 of the 74HC125 at U6 to pin 12 of the 74HC74 device , convenient to solder to. Figure 4: Modifications to pin 12 of the 74HC74 at U3 5 Short circuit the , device is plugged at the U7 socket (Figure 1). Remove this device from the socket and bend pin 5


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PDF AN1483 ST7MDT20M-EPB, ST7MDT20J-EPB ST7MDT10-EPB ST7MDT20J-EPB, ST7MDT20M-EPB 74HC74 74HC125 74HC74 application 74HC74 application note AN1483 74HC74 datasheet
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