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    74LVC109PW,118 Search Results

    74LVC109PW,118 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74LVC109PW,118 NXP Semiconductors Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT403-1 (TSSOP16); Container: Reel Pack, SMD, 13" Original PDF
    74LVC109PW,118 NXP Semiconductors 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM,PLASTIC, MO-153, SOT403-1, TSSOP1-16, FF/Latch Original PDF
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    74LVC109PW,118 Price and Stock

    NXP Semiconductors 74LVC109PW,118

    IC FF JK TYPE DUAL 1BIT 16TSSOP
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    DigiKey 74LVC109PW,118 Reel
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    Nexperia 74LVC109PW,118

    Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin TSSOP T/R
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    Chip1Stop 74LVC109PW,118 Cut Tape 30
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