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74LS76 logic diagram Datasheets Context Search

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ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: Signetics Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K , and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , ¶]qj »02 E T]j2 LOGIC SYMBOL LS76 «' «o, » r —IS »— Ja *®> Cj Roj Qj|O-10 K. no, o, ~T 76 -is «- o* >-1« 12—I Ki Roj Qa|0-1C LOGIC SYMBOL (IEE/IEC) 76 LS76 ij CI n 15


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PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: Flip-Flops 7476, LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products , HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 E ®D 1OE *01 GE


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
Text: FLIP-FLOP LOGIC DIAGRAM MODE SELECT- TRUTH TABLE OPERATING MODE ®D Asynchronous Set Asynchronous , 54/7476 54H/74H76 54LS/ 74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K , . The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup , levels as shown in the Truth Table. LOGIC SYMBOL 2 7 4- J SD Q -15 9 , . d. The 74LS76 is edge triggered. Data m ust be stable one setup tim e p rio r to the negative edge o


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PDF 54H/74H76 54LS/74LS76 74H76 74LS76 54H/74H 54S/74S 54LS/74LS logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
Text: 54/7476 54H/74H76 54LS/ 74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK , signotics This Material Copyrighted By Its Respective Manufacturer LOGIC DIAGRAM MODE SELECT—TRUTH , . The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup , the output states are unpredictabfe if Sd and Rd go HIGH simultaneously. d. The 74LS76 is edge


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PDF 54H/74H76 54LS/74LS76 74H76 74LS76 7476 truth table 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: , LS76 LOGIC DIAGRAM S 0 - y xC " Q K - -J CP LD0280GS FUNCTION TABLE INPUTS , Sjgnetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products , HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , l|H and -0 .4 m A lIL. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP


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PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: 81501 Signetics Logic Products Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products , HIGH for conventional operation. The 74LS76 is a negative edge-triggered flip-flop. The J and K inputs , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , . PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP, U 33*1 D o , 1J


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , Signetics Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K , and K inputs must be stable while the Clock is HIGH for conventional operation. The 74LS76 is a , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , ’ 3302 "02 u T]j2 LOGIC SYMBOL 'LS76 — 15 »— J, «' "to, O'P-" ~T 3 7$ Kl Ro, % ~7 LOGIC


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PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
7476 truth table

Abstract: 7476 logic diagram 74LS76P 7476PC 74ls76
Text: NATIONA L SEMICOND -CLOGIO 02E D | b S O U S E 76 GGbBVSO t , | 3 T-YL- 0 7 -0 7 CONNECTION DIAGRAM PINOUT A 54/7476 54H/74H76 54LS/ 74LS76 DUAL JK FLIP-FLOP (With Separate Sets, Clears , both Q and Q HIGH LOGIC SYMBOL The 'LS76 is a dual JK, negative edge-triggered flip-flop also , /74LS (U.L.) HIGH/LOW 0.5/0.25 2.0/0.5 1.5/0.5 1.5/0.5 10/5.0 (2.5) LÖGIC DIAGRAMS (one half shown , SEHICOND { LOGIC } OSE D | b S O U S E 0Db3?E5 0 | 76 SYMBOL PARAMETER 54/74 Min Icc Power Supply


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PDF 54H/74H76 54LS/74LS76 54/74H 54/74LS CLS76) 7476 truth table 7476 logic diagram 74LS76P 7476PC 74ls76
74LS76

Abstract: flip-flop 74ls76 Jk 74ls76
Text: SANYO SE MIC ONDU CT OR CORP ~ 1EE I ) | 7Ti707b GODEbbñ IC74HG76M * _\ * ·» - . .v f e -07-o 7 . C M O S High-Speed Standard Logic _ LC74H C Series Dual J-K Flip-Flop with Set and Reset Features · The LC74HC76M consists o f 2 identical J-K type flip-flops. · Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL ( 74LS76 ) w ith the , functionally as well as pln-out compatible with the standard 54LS/74LS T T L logic family. Absolute Maximum


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PDF 7Ti707b IC74HG76M -07-o LC74H LC74HC76M 74LS76) 54LS/74LS 10sec LC74HC76. 74LS76 flip-flop 74ls76 Jk 74ls76
74LS76P

Abstract: 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout IC 74LS76
Text: 76 CO NNECTIO N DIAGRAM PINOUT A /54/7476 0 / / o / c ^ ^S4H/74H76 Gf / ci 7 ^ 54LS/ 74LS76 £ v / 6 / 6 DUAL JK FLIP-FLOP (With Separate Sets, Clears and Clocks) DESCRIPTION - The '76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip-flop. Inputs to the master section are controlled by the clo ck pulse. The clock pulse , both Q and Q HIGH LOGIC SYMBOL The 'LS76 is a dual JK, negative edge-triggered flip -flo p also


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PDF S4H/74H76 54LS/74LS76£ 54/74H 54/74LS CLS76) 74LS76P 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout IC 74LS76
74HC76

Abstract: DIODE A7N 54HC 74HC M54HC76 M74HC76 M74HC76B1N
Text: 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS76 DESCRIPTION The M54/74HC76 is a high speed CMOS , of LSTTL combined with true CMOS low power consumption. Depending on with the logic level at the J , PRESET are independent of the clock and are accomplished by a logic low on the corresponding input. All , October 1988 1/5 149 This Material Copyrighted By Its Respective Manufacturer M54/74HC76 LOGIC DIAGRAM (1/2 Package) >■D> * >':D- rC> Jfît>ÎOî J O E> r'OO ° kf r £H>a * ABSOLUTE


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PDF M54HC76 M74HC76 54/74LS76 M54/74HC76 M54/74HC76 k50v- 74HC76 DIODE A7N 54HC 74HC M74HC76 M74HC76B1N
74ls76 jk flip-flop logic symbol and truth table

Abstract: 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop 74LS76D pin diagram of 7476 74LS76DC Jk 74ls76 pin out
Text: 76 ^54/7476 O/Zô/b, ^54H/74H76 l/54LS/ 74LS76 Gf/otù, DUAL JK FLIP-FLOP (With Separate Sets, Clears and Clocks) DESCRIPTION —The '76 and 'H76 are dual JK master/slave flip-flops with separate Direct Set, Direct Clear and Clock Pulse inputs for each flip-flop. In puts to the master section are , Table on the HIGH-to-LOW clock transitions. ORDERING CODE: See Section 9 CONNECTION DIAGRAM PIN OUT A , 5476FM, 54H76FM 54LS76FM 4L LOGIC SYMBOL 4 — j 80 q —ris îh j s° q —11 1—0 cp 6 —o cp


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PDF 54H/74H76 l/54LS/74LS76 54/74H 54/74LS CLS76) 74ls76 jk flip-flop logic symbol and truth table 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop 74LS76D pin diagram of 7476 74LS76DC Jk 74ls76 pin out
74Ls76 truth table

Abstract: TC74HC76AP Jk 74ls76 pin out
Text: R -.£>- L - £ > > - j - £>>-1_s 0 < t > -K H < F Logic Diagram , with the logic level applied to the J and K inputs, the outputs change state on the negative going tran , logic level on the corresponding input. All inputs are equipped with protection circuits against static , Compatible with 74LS76 2P R 20 3 to 2Q 3 l1 2C Ü R » [ 3. ( T O P V IE W ) 2J Pin Assignm , X X Q L H H 0 H Clear Preset No Change L H L H X ûn L H. H IEC Logic


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PDF TC74HC76AP/AF TC74HCT76A 65MHzflyp. TC74HC/HCT 74Ls76 truth table TC74HC76AP Jk 74ls76 pin out
74LS76 IC

Abstract: TC74HC76AP IC 74LS76 AF4 equivalent TC74HC76A
Text: accordance with the logic level applied to the J and K inputs,the outputs change state on the negative going , logic level on the corresponding input. All inputs are equipped with protection circuits against static , Vcc (opr) = 2V ~6V · Pin and Function Compatible with 74LS76 . TRUTH TABLE 2CK 2 PR 2C LR » , ) SYMBOL TEST CONDITION _ _ TC74HC76AP/AF-3 229 SYSTEM DIAGRAM (1/2 package) TC74HC76AP


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PDF TC74HC76AP/AF TC74HC76A TC74HC76AP/AF-3 TC74HC76AP/AF-4 74LS76 IC TC74HC76AP IC 74LS76 AF4 equivalent
logic ic 74LS76 pin diagram

Abstract: 74hc76 pin diagram for IC 74ls76 74LS76 IC IC 74LS76 of ic 74LS76 IC 74LS76 pin diagram M54HC76 M74HC76 74HC
Text: 129 7/84 This Material Copyrighted By Its Respective Manufacturer M54HC76 M74HC76 LOGIC DIAGRAM (1 , accordance with the logic level on the J and K inputs this device changes state on negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic , 54/ 74LS76 INPUTS OUTPUTS FUNCTION CLR PR J K CK Q tr L H * * * L H CLEAR H L * * * H L


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PDF M54/74HC76 logic ic 74LS76 pin diagram 74hc76 pin diagram for IC 74ls76 74LS76 IC IC 74LS76 of ic 74LS76 IC 74LS76 pin diagram M54HC76 M74HC76 74HC
M74HC76

Abstract: No abstract text available
Text: VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS76 V nih M1R C1R , with the logic level at the J and K inputs this device changes state on the nega­ tive going , logic low on the corresponding in­ put. All inputs are equipped with protection circuits against , IEC LOGIC SYMBOL NAME AND FUNCTION PIN No SYMBOL 1, 6 1CK, 2CK 2, 7 1PR, 2PR 3 , Positive Supply Voltage Clock Input (HIGH to LOW edge triggered) Set Inputs (Active LOW) LOGIC


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PDF M54HC76 M74HC76 54/74LS76 54HC76F1R 74HC76B1R M54/74HC76 M54/M74HC76 M74HC76
logic ic 74LS76 pin diagram

Abstract: j-k flip flop 74ls76 IC 74LS76
Text: £ 15 ns, tf g 6 ns, PR R = 1MHz Truth tables Logic diagram ( 1/2) N o tes 1. H: 2. L: 3.1 , LS TTL DN74LS Series DN74LS76 D N 74LS76 D ^ 74^ 7^ Dual J-K F lip -F lo p s (with S e t and Reset) Description D N 7 4 L S 7 6 contains tw o negative-edge triggered J-K flip-flop circuits, each w ith independent clock-C P, J, K, and directcoupled set and reset input terminals. P -2 · · · · · Features Negative-edge trigger Independent input and ou tp u t term inals for each flip-flop


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PDF DN74LS DN74LS76 74LS76 16-pin logic ic 74LS76 pin diagram j-k flip flop 74ls76 IC 74LS76
1994 - 74HC76

Abstract: logic ic 74LS76 pin diagram pin diagram for IC 74ls76 74ls76 jk flip-flop logic symbol and truth table IC 74LS76 74LS76 IC M74HC76B1R 74Ls76 truth table M74HC76M1R M54HC76F1R
Text: Inputs: Flip-Flop 1 and 2 5 13 GND V CC Ground (0V) Positive Supply Voltage LOGIC DIAGRAM , VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS76 B1R (Plastic Package) F1R , low power consumption. Depending on with the logic level at the J and K inputs this device changes , clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with , LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 6 1CK, 2CK Clock Input (HIGH to LOW


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PDF M54HC76 M74HC76 54/74LS76 M54HC76F1R M74HC76M1R M74HC76B1R M74HC76C1R M54/74HC76 74HC76 logic ic 74LS76 pin diagram pin diagram for IC 74ls76 74ls76 jk flip-flop logic symbol and truth table IC 74LS76 74LS76 IC M74HC76B1R 74Ls76 truth table M74HC76M1R M54HC76F1R
MAX77100

Abstract: IC74 IC-74
Text: No.3628 f MLC74HC76M CMOS High-Speed Standard Logic Dual J-K Flip-Flop with Reset and Set , process technology to achieve operating speeds sim ilar to LS-TTL ( 74LS76 ) with the low power dissipation , compatible with the standard 54LS/74LS TTL logic family. A b so lu te M axim um R atin g s a tT a = 2 5 ± 2 , Information (« c ed in g eircurt diagram s and c rc w t para m eters) herein is (or eis/npl« only; it is nol , ED? i ( T o p V iew ) Logie Diagram Input Protection Circuit vcc vss T IC74HC7S V


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PDF 0010S31 MLC74HC76M MLC74HC76M 74LS76) 54LS/74LS MLC74HC MAX77100 IC74 IC-74
74hct76

Abstract: HC76 Jk 74ls76 pin out 74HC76 LS 74LS76 GD54/74HCT76 74LS76 pinout 74HC LOGIC PINOUT GD74HC76 GD54HC76
Text: Types at 2V at 4 .5 V at 6V GD54/74HCT Types at 4 5V 1000 500 400 500 ns Logic Diagram Fig. 1 Logic diagram (one flip-flop) 4-102 GD54/74HC/HC76, GD54/74HCT76 DC Electrical Characteristics for HC SYMBOL , GD54/74HC76, GD54/74HCT76 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/ 74LS76 . These flip-flops are edge sensitive to the clock input , and accomplished by a low logic level on the corresponding input. These devices are characterized for


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PDF GD54/74HC76, GD54/74HCT76 54/74LS76. GD54/74HC/HC76, 74hct76 HC76 Jk 74ls76 pin out 74HC76 LS 74LS76 GD54/74HCT76 74LS76 pinout 74HC LOGIC PINOUT GD74HC76 GD54HC76
74HC76

Abstract: logic ic 74LS76 pin diagram M74HC76
Text: FUNCTION COMPATIBLE WITH 54/ 74LS76 DESCRIPTION The M54/74HC76 is a high speed CMOS DUAL J-K FLIP FLOP , true CMOS low power con sumption. Depending on with the logic level at the J and K inputs this device , the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with , CONTACT SGS-THOMSON C Tn NO CHANGE X: DON'T CARE October 1988 149 M 5 4 /7 4 H C 7 6 LOGIC DIAGRAM (1/2 Package) -t>t> 1 ABSOLUTE MAXIMUM RATINGS Symbol v c c V| Vo iK ·o k *0 Ice or !gnd


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PDF M54HC76 M74HC76 54/74LS76 M54/74HC76 M54/74HC76 74HC76 logic ic 74LS76 pin diagram M74HC76
74ls76 jk flip-flop logic symbol and truth table

Abstract: 74hc76 pin diagram for IC 74ls76 74LS76 IC M74HC76 M74HC76B1R M74HC76C1R M54HC76F1R M54HC76 logic ic 74LS76 pin diagram
Text: Inputs: Flip-Flop 1 and 2 5 13 GND V CC Ground (0V) Positive Supply Voltage LOGIC DIAGRAM , VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS76 B1R (Plastic Package) F1R , low power consumption. Depending on with the logic level at the J and K inputs this device changes , clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with , LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 6 1CK, 2CK Clock Input (HIGH to LOW


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PDF M54HC76 M74HC76 54/74LS76 M54HC76F1R M74HC76M1R M74HC76B1R M74HC76C1R M54/74HC76 74ls76 jk flip-flop logic symbol and truth table 74hc76 pin diagram for IC 74ls76 74LS76 IC M74HC76 M74HC76B1R M74HC76C1R M54HC76F1R M54HC76 logic ic 74LS76 pin diagram
74HC76

Abstract: 54HC76 logic ic 74LS76 pin diagram Toggle flip flop IC
Text: Flip-Flop Outputs Data Inputs: Flip-Flop 1 and 2 Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL LOGIC DIAGRAM (1/2 Package) 1 5 -£ 0 L > > - ^ J r , WITH 54/ 74LS76 DESCRIPTION The M54/74HC76 Is a high speed CMOS DUAL J-K FLIP FLOP fabricated in silicon , power con sumption. Depending on with the logic level at the J and K inputs this device changes state on , are ac complished by a logic low on the corresponding in put. All inputs are equipped with protection


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PDF 54HC76 74HC76 10LSTTL 54/74LS76 M54/74HC76 74HC76 logic ic 74LS76 pin diagram Toggle flip flop IC
74hc76

Abstract: M74HC76
Text: 4 22^ ■S G T H s _TH0NS0N LOGIC DIAGRAM (1 /2 P a c k a g e ) X > I , COMPATIBLE WITH 54/ 74LS76 ORDERING NUMBERS: M54HC76 F1 M74HC76 C1 M74HC76 B1N M74HC76 M1 M74HC76 F1 , ­ sumption. Depending on with the logic level at the J and K inputs this device changes state on the ne , accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits


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PDF M54HC76 M74HC76 54/74LS76 M54HC76 M74HC76 M54/74HC76 G031fll7 74hc76
74hc76

Abstract: M74HC76
Text: X: DON’T CARE October 1988 149 M54/74HC76 LOGIC DIAGRAM (1/2 Package) ABSOLUTE MAXIMUM , RANGE VCc (OPR) = 2V to 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS76 DESCRIPTION The M54 , on with the logic level at the J and K inputs this device changes state on the ne­ gative going , logic low on the corresponding input. All inputs are equipped with protection circuits against static


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PDF M54HC76 M74HC76 54/74LS76 M54/74HC76 and35 M54/74HC76 74hc76 M74HC76
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