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Part Manufacturer Description Datasheet Download Buy Part
SN74LS73AD Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70
SN74LS73ADE4 Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70
SN74LS73ADG4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SO-14
SN74LS73ADR Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70
SN74LS73ADRE4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SO-14
SN74LS73ADRG4 Texas Instruments Dual J-K Flip-Flops with Clear 14-SOIC 0 to 70

Search Stock (34)

  You can filter table by choosing multiple options from dropdownShowing 34 results of 34
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
74LS73N Signetics New Advantage Corporation - -
74LS73NA+1 Rochester Electronics - -
74LS73NA+2 Rochester Electronics - -
74LS73PC Rochester Electronics - -
DM74LS73ACW Rochester Electronics - -
DM74LS73AM Rochester Electronics - -
DM74LS73AMX Rochester Electronics - -
DM74LS73AN Rochester Electronics - -
N74LS73N Signetics High Technology Bristol Electronics - -
NTE74LS73 NTE Electronics Inc Master Electronics 37 $2.60 $1.73
SN74LS73AD Rochester Electronics - -
SN74LS73AD Texas Instruments TME Electronic Components 98 $2.13 $1.31
SN74LS73AD Texas Instruments Avnet 0 $1.08 $0.93
SN74LS73AD Texas Instruments Rochester Electronics 15,611 $1.36 $1.10
SN74LS73ADR Texas Instruments Rochester Electronics 12,500 $1.14 $0.93
SN74LS73ADR Texas Instruments Avnet 0 $0.90 $0.78
SN74LS73ADR Texas Instruments Texas Instruments 5,343 $1.67 $0.71
SN74LS73ADR Texas Instruments Chip1Stop 1,406 $1.46 $1.13
SN74LS73ADRG4 Texas Instruments Avnet 0 $0.90 $0.78
SN74LS73AJ Motorola Semiconductor Products Bristol Electronics - -
SN74LS73AN Rochester Electronics - -
SN74LS73AN Texas Instruments Avnet 17 $1.37 $0.96
SN74LS73AN Motorola Semiconductor Products Bristol Electronics - -
SN74LS73AN Texas Instruments Texas Instruments 2,460 $1.84 $0.78
SN74LS73AN Texas Instruments TME Electronic Components 43 $1.87 $1.16
SN74LS73AN Texas Instruments Newark element14 248 $2.02 $0.89
SN74LS73AN Texas Instruments Schukat electronic 70 €1.24 €0.89
SN74LS73AN Texas Instruments Chip1Stop 1 $2.18 $2.18
SN74LS73AN Texas Instruments Newark element14 40 $2.02 $0.89
SN74LS73AN Texas Instruments element14 Asia-Pacific 238 $2.54 $1.24
SN74LS73AN Texas Instruments Farnell element14 167 £1.32 £0.99
SN74LS73ANE4 Texas Instruments Avnet 0 $0.99 $0.86
SN74LS73ANS Texas Instruments Rochester Electronics - -
SW74LS73AD Motorola Semiconductor Products New Advantage Corporation - -

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74LS73 datasheet (15)

Part Manufacturer Description Type PDF
74LS73 Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Original PDF
74LS73 Hitachi Semiconductor Dual J-K Flip-Flops(with Clear) Original PDF
74LS73 Motorola DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP Original PDF
74LS73 Texas Instruments DUAL J-K FLIP-FLOPS WITH CLEAR Original PDF
74LS73 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
74LS73 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
74LS73 Signetics Dual J-K Flip-Flop Scan PDF
74LS73 Signetics Dual J-K Flip-Flop Scan PDF
74LS73 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
74LS73A Fairchild Semiconductor Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Original PDF
74LS73A Hitachi Semiconductor Dual J-K Flip-Flops(with Clear) Original PDF
74LS73A Texas Instruments DUAL J-K FLIP-FLOPS WITH CLEAR Original PDF
74LS73DC Fairchild Semiconductor Dual JK Flip-Flop Scan PDF
74LS73FC Fairchild Semiconductor Dual JK Flip-Flop Scan PDF
74LS73PC Fairchild Semiconductor Dual JK Flip-Flop Scan PDF

74LS73 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
pin diagram of 7473

Abstract:
Text: the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop. The , CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5 , Clock is HIGH for conventional operation. 2. The 74LS73 is edge triggered. Data must be stable one , 1.0 40 80 74LS73 Min 2.7 80 -1.6 -3.2 -3.2 10 -57 40 Typ2 3.4 0.35 0.25 -20 Max 0.5


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PDF 74LS73 1N916, 1N3064, 500ns pin diagram of 7473 pin diagram of ttl 7473 7473 JK flip flop 7473 pin diagram 7473 7473 ttl ttl 7473 74LS73 dual JK fan out 74ls73
pin diagram of 7473

Abstract:
Text: while the C lock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop , and HIGH. asynchronous LOW, it over inputs, forcing the Q output TYPE 7473 74LS73 TYPICAL f max 20MHz , Clock is HIGH for conventional operation. 2. The 74LS73 is edge triggered. Data must be stable one , recommended operating free-air temperature range unless otherwise noted.) 7473 PARAMETER VCc = 74LS73


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PDF 74LS73 1N916, 1N3064, 500ns 500ns pin diagram of 7473 ttl 7473 7473 pin diagram N74LS73 p 7473 n ok2t Flip-Flops 7473 74LS73 TTL 7473 ttl
Not Available

Abstract:
Text: while the C lock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered , f MAX TYPICAL SUPPLY CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA , stable while the Clock is HIGH tor conventional operation. The 74LS73 is edge triggered. Data must be , operating free-air temperature range unless otherwise noted.) 74LS73 7473 UNIT T e a l (JUNUIIIUNS


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PDF 74LS73 1N916, 1N3064, 500ns
7473 pin diagram

Abstract:
Text: the Q output H IG H . TYPE 7473 74LS73 TYPICAL fMAX 20MHz 45MHz TYPICAL SUPPLY CURRENT (TOTAL , operation. 2. The 74LS73 is edge triggered. Data must be stable one set-up time prior to the negative edge , v oe = MIN, V|H - MIN, V|L " MAX, Iq h 74LS73 UNIT Max Min 2.7 0.4 Typ2 3.4 Typ2 3.4


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PDF 1N916, 1N3064, 500ns 500ns 7473 pin diagram 74LS73 pin diagram of 7473 7473 7473 dual JK pin diagram of ttl 7473 TTL 74ls73
74LS73

Abstract:
Text: 54/7473 54H/74H73 54LS/ 74LS73 LOGIC SYMBOL DESCRIPTION The "73" is a dual Flip-Flop with individual JK, Clock and direct Reset inputs. The 7473 and 74H73 are positive pulse triggered 'flipflops. JK information is loaded into the master while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW , conventional operation. The 74LS73 is a negative edge triggered flip-flop. The J and K inputs must be stable , conventional operation. d. The 74LS73 is edge triggered. Data must be stable one setup time prior to the


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PDF 54H/74H73 54LS/74LS73 74H73 74LS73 54H/74H 54S/74S 54LS/74LS 74H73must pin diagram of 7473 74LS73 dual JK 7473 7473 pin diagram 7473 JK flip flop S5473F N7473F N7473N
IC 7473

Abstract:
Text: the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop. The J , . asynchronous LOW, it over inputs, forcing the (5 output TYPE 7473 74LS73 TYPICAL f , AX 20MHz 45MHz , c k is HIGH fo r conventional operation. The 74LS73 is edge triggered. Data m ust be stable one , recommended operating free-air temperature range unless otherwise noted.) 7473 74LS73 UNIT Min Typ2 3.4 0.2


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PDF 74LS73 1N916, 1N3064, 500ns 500ns IC 7473 pin diagram for IC 7473 circuit diagram for IC 7473 pin DIAGRAM OF IC 7473 IC 74LS73 7473 pin diagram ic 7473 pin diagram Flip-Flop 7473 7473 equivalent pin configuration of IC 7473
circuit diagram for IC 7473

Abstract:
Text: while the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop , TYPICAL SUPPLY CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA TYPE ORDERING , Clock is HIGH for conventional operation. The 74LS73 is edge triggered. Data must be stable one set-up , temperature range unless otherwise noted.) 74LS73 7473 PARAMETER UNIT T b S I ( J U N U I 1IU N S


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PDF 74LS73 1N916, 1N3064, 500ns circuit diagram for IC 7473 IC 7473 ic 7473 jk flipflop pin diagram for IC 7473
7473 pin diagram

Abstract:
Text: the Clock is HIGH for conventional operation. The 74LS73 is a negative edge-triggered flip-flop. The , CURRENT (TOTAL) 7473 20MHz 10mA 74LS73 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V +5% , Clock is HIGH for conventional operation. 2. The 74LS73 is edge triggered. Data must be stable one , .) PARAMETER TEST CONDITIONS1 7473 74LS73 UNIT Min Typ2 Max Min Typ2 Max Voh HIGH-level output


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PDF 74LS73 1N916, 1N3064, 500ns 7473 pin diagram TTL 7473 pin diagram of 7473 74LS73 dual JK 7473 ttl 7473 7473 JK flip flop TTL 74ls73 Flip-Flop 7473
74LS183

Abstract:
Text: CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151


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PDF LZ93/LZ95/LZ96/LZ97 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS183 74LS275 74LS97 74ls series 74LS93 74LS356 74LS55 74LS396
74ls73

Abstract:
Text: -68-7473 1J 1Ü IQ ONO 2K 2Q 2d 07X» x -T®! (7473) 7 D , <7 7- 9 O i- Ht 1 7 ') - 7 1 > fx- y ->' h 'J if ( 74LS73 ) 9 a -t 9 _I J— T- 9 -1 n- ' tsu' thold O 9 >> T (N, LSÄiä) 7473 Dual JK-FFs with Clear 1(5) 74 LS 73 HB Al) IN ibJj OUT II LS ALS ALSK F S AS AC ACT HC HCl HCT BC BCT *


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PDF 74LS73) 74ls73 74LS73 dual JK 74 HCL 4 7473 dual JK 7473 7473 HCT 74ls731 HC 165
TTL 74ls74

Abstract:
Text: o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/ 74LS73 •54/74107, *54LS/74LS107 14 — J 0 -12 I- J


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PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54L15 TTL 74ls74 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73 74ls74 TTL 74ls76 74LS109
74LS73

Abstract:
Text: INPUTS ä - ! - O (Each Flip-Flop) 54/ 74LS73 INPUTS CLEAR CLOCK J K OUTPUTS a a a 0


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PDF 54/74H 54/74LS 74LS73
pin DIAGRAM OF IC 74HC73

Abstract:
Text: OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS73 C1R (Chip


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PDF M54HC73 M74HC73 73F1R 73B1R 54/74LS73 M74HC73M 74HC73C1R M54/74HC73 74HC73 pin DIAGRAM OF IC 74HC73 74HC73 IC 74LS73 M74HC73 Toggle flip flop IC
pin DIAGRAM OF IC 74HC73

Abstract:
Text: SGS -THOMSON M54HC73 _M74HC73 DUAL J-K FLIP FLOP WITH CLEAR ■HIGH SPEED 'MAX = 60 MHz (TYP.) at VCC= 5V ■LOW POWER DISSIPATION ICC = 2 nA (MAX.) at TA = 25°C ■HIGH NOISE IMMUNITY Vnih = Vnil = 28"/o VCC (MIN.) ■OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■SYMMETRICAL OUTPUT IMPEDANCE |OH| = |OL = 4 mA (MIN.) ■BALANCED PROPAGATION DELAYS tPLH = tPHL ■WIDE OPERATING VOLTAGE RANGE VCc (OPR) = 2V to 6V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS73 DESCRIPTION The M54/74HC73


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PDF M54HC73 M74HC73 54/74LS73 M54/74HC73 M54/74HC73 pin DIAGRAM OF IC 74HC73 IC 74LS73 74hc73 M74HC73 ic 74LS73 CMOS diode yz 040 M54HC73 74HC M74HC73B1N pin diagram for IC 74hc73
CI 7474

Abstract:
Text: o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/ 74LS73 •54/74107, *54LS/74LS107 14 — J 0 -12 I- J


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PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
TTL 74ls74

Abstract:
Text: o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/ 74LS73 •54/74107, *54LS/74LS107 14 — J 0 -12 I- J


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PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
pin diagram for IC 7473

Abstract:
Text: 7473PC, 74H73PC 74LS73PC 7473DC, 74H73DC 74LS73DC 7473FC, 74H73FC 74LS73FC 5473DM, 54H73DM 54LS73DM , ' NATIONAL SENICOND {LOGIO DEE D | b S D l l S E OOfc.3712 7 | 73 54/7473 54H/74H73 54LS/ 74LS73 DUAL JK FLIP-FLOP (W ith S ep arate Clears and Clocks) D ESC R IP TIO N - The '73 and 'H73 dual J K master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling


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PDF 54H/74H73 54LS/74LS73 54/74H 54/74LS CLS73) pin diagram for IC 7473 pin DIAGRAM OF IC 7473 74LS73D pin diagram of 7473 7473PC 74LS73 dual JK 74H73 IC 7473 ic 7473 pin diagram IC 74LS73
7473 JK flip flop

Abstract:
Text: ) OUT COMMERCIAL GRADE V cc = +5.0 V ±5%, Ta = 0°C to +70° C 7473PC, 74H73PC 74LS73PC 7473DC, 74H73DC 74LS73DC 7473FC, 74H73FC 74LS73FC 5473DM, 54H73DM 54LS73DM 5473FM, 54H73FM 54LS73FM MILITARY GRADE Vcc = , 73 CO NNECTIO N DIAGRAM PINOUT A 54/7473 ^ /54H /74H 73 O f1014 I/54LS/ 74LS73 DUAL JK FLIP-FLOP (With Separate Clears and Clocks) D E S C R IP TIO N - The '73 and 'H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled


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PDF f1014 I/54LS/74LS73 54/74H 54/74LS CLS73) 7473 JK flip flop IC 74LS73 74LS73D 7473PC 74LS73 dual JK JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 ic jk flip flop 7473 pin DIAGRAM OF IC 7473 d flip flop
logic ic 7476 pin diagram

Abstract:
Text: 54/7473, 54H/74H73, 54LS/ 74LS73 *54/74107, ` 54LS/74LS107 14 - J 1 - 0 CP 3- K Q -1 2 2- J 5 -0 CP


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PDF 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279 54H/74H73, 54LS/74LS73 54LS/74LS107 logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74LS107 IC 74196 74LS109 7476 Connection diagram 74109 dual JK d146 7474 D latch
TC74HC73A

Abstract:
Text: with 74LS73 (U) ( !) (3) (2 ) (7) (5) (10) (6) ^ ^ «> 2Q ^ (9) 2 0 1 CK CLR 1K Vcc 2 CK CLR 2J 1C 2


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PDF TC74HC73AP/AF TC74HC73A 55MHz TC74HC/HCT
74KC

Abstract:
Text: Function compatible with 54/ 74LS73 TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR J K CK Q Q L X X X L H


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PDF M54HC73 M74HC73 M54/74HC73 74KC IC 74LS73 pin DIAGRAM OF IC 74HC73 74LS73 dual JK M74HC73 74hc73 74HC JK flip flop IC M54HC73 54HC
ic 74LS73 CMOS

Abstract:
Text: Voltage Range ··· Vcc (opr)=2V ~6V · Pin and Function Compatible with 74LS73 TRU TH TABLE INPUTS CLR K J


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PDF TC74HC73AP/AF TC74HC73A 55MHi HC-191 HC-192 ic 74LS73 CMOS IC 74LS73
TC74HC73AP

Abstract:
Text: Operating Voltage Range Vq; (opr)=2V ~6V · Pin and Function Com patible with 74LS73 1 CK 1 C 1 CLR 2C 1K 3


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PDF TC74HC73AP/AF TC74HC73A 55MHz TC74HC73AP/AF-3 TC74HC73AP/AF-4 TC74HC73AP
FZH115B

Abstract:
Text: 74HC42 74LS47 74LS51 74LS53 74LS54 74HC51 7472 7473 74LS73 74HC73 7474 7475 , 74LS670 74LS73 74LS74 1+ £0.75 £1.19 £0.60 £1.19 £0.73 £1.37 £0.44 £0.89 £0.54 £0.58 £0.77


Original
PDF 74INTEGRATED Line-to-10 150ns 16-DIL 150ns 18-pin 250ns 300ns FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
pin diagram for IC 7473

Abstract:
Text: ) Flatpak (R PIN OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, Ta = 0°C to +70° C 7473PC, 74H73PC 74LS73PC 7473DC, 74H73DC 74LS73DC 7473FC, 74H73FC 74LS73FC MILITARY GRADE Vcc = +5.0 V ±10%, Ta = -55° C to , 73 54/7473 ^ /54H/74H73 c/fûic/ 1/54LS/ 74LS73 C?//c>/Z> DUAL JK FLIP-FLOP (With Separate Clears and Clocks) DESCRIPTION —The '73 and 'H73 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse


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PDF /54H/74H73 1/54LS/74LS73 54/74H 54/74LS CLS73) pin diagram for IC 7473 7473PC ic 7473 pin diagram of 7473 pin DIAGRAM OF IC 7473 7473 pin diagram Flip-Flop 7473PC 74LS73 dual JK IC 74LS73 74LS73DC
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