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Part Manufacturer Description Datasheet Download Buy Part
SN74LS490J Texas Instruments LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, CERAMIC, DIP-16
SN74LS490J-00 Texas Instruments LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16
SN74LS490N-10 Texas Instruments LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16
SN74LS490D Texas Instruments LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, PLASTIC, SO-16
SN74LS490N Texas Instruments Asynchronous decade counters 16-PDIP 0 to 70
SN74LS490DR Texas Instruments LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, PLASTIC, SO-16
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74LS490N Rochester Electronics - - -
SN74LS490N Rochester Electronics LLC Rochester Electronics 1,195 $14.84 $12.89
SN74LS490N Motorola Semiconductor Products Bristol Electronics 8 $8.96 $5.82
SN74LS490N Motorola Semiconductor Products Chip One Exchange 200 - -
SN74LS490N Texas Instruments New Advantage Corporation 5 - -
T74LS490B1 STMicroelectronics Chip One Exchange 16 - -

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74LS490 datasheet (6)

Part Manufacturer Description Type PDF
74LS490 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
74LS490 Signetics Dual BCD Decade Ripple Counter Scan PDF
74LS490 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
74LS490DC Fairchild Semiconductor Dual Decade Counter Scan PDF
74LS490FC Fairchild Semiconductor Dual Decade Counter Scan PDF
74LS490PC Fairchild Semiconductor Dual Decade Counter Scan PDF

74LS490 Datasheets Context Search

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74ls490

Abstract: No abstract text available
Text: MOTOROLA SN54/ 74LS490 DUAL DECADE COUNTER The SN54/ 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54/ 74LS490 has individual Clock, Master Reset and Mas ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code. · · · · Dual Version of SN54/ 74LS490 , / 74LS490 GUARANTEED OPERATING RANGES Symbol V CC S u pply Voltage Parameter 54 74 54 74 54, 74 54 74 , Conditions 25 Vcc = 5 .0 V FAST AND LS TTL DATA 5-354 SN54/ 74LS490 AC CHARACTERISTICS (TA


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PDF SN54/74LS490 74ls490
Not Available

Abstract: No abstract text available
Text: Signetics Logic Products Counter 74LS490 Dual BCD Decade Ripple Counter Product , Reset (clear) TYPE 74LS490 TYPICAL fM AX 55MHz TYPICAL SUPPLY CURRENT (TOTAL) 15mA ORDERING CODE , Specification Counter 74LS490 LOGIC DIAGRAM MODE SELECTION - FUNCTION TABLE FOR h THE 490 RESET , Signetlcs Logic Products Product Specification Counter 74LS490 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) 74LS490 PARAMETER Min


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PDF 74LS490 74LS490 55MHz N74LS490N BC490 1N916, 1N3064, 500ns 500ns
1996 - truth table NOT gate 74

Abstract: 74LS490 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/ 74LS490 DUAL DECADE COUNTER The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code. · · · · Dual Version of SN54 / 74LS490 , / 74LS490 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply , VCC = 5 0 V 5.0 SN54/ 74LS490 AC CHARACTERISTICS (TA = 25°C) Limits Symbol S b l Parameter


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PDF SN54/74LS490 74LS490 74LS490 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
74ls490

Abstract: No abstract text available
Text: Signetics 74LS490 Counter Dual BCD Decade Ripple Counter Product Specification Logic , e t-to -9 ) · A s y n c h ro n o u s M a s te r R e s e t (c le a r) TYPE 74LS490 TYPICAL tMAx 55MHz , 81500 S ignetics Logic Products P roduct S pecification Counter 74LS490 LOGIC DIAGRAM , pecification Counter 74LS490 DC ELECTRICAL CHARACTERISTICS PARAMETER Voh V ol V ik . ' I ih (Over recommended operating free-air temperature range unless otherwise noted.) 74LS490 TEST CONDITIONS1 Min Typ2


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PDF 74LS490 74LS490 55MHz are90 1N916, 1N3064, 500ns 500ns
Signetics 565

Abstract: 1N3064 1N916 74LS 74LS490 N74LS490N
Text: Signetics Logic Products 74LS490 Counter Dual BCD Decade Ripple Counter Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74LS490 55MHz 15mA ORDERING CODE PACKAGES , Specification Counter 74LS490 LOGIC DIAGRAM (4,12) t""*" — (2,14) ^ ( ) = Pin numbers Vcc = pin 16 GND , Copyrighted By Its Respective Manufacturer Signetics Logic Products Product Specification Counter 74LS490 , noted.) PARAMETER TEST CONDITIONS1 74LS490 UNIT Min Typ2 Max Vqh HIGH-level output voltage


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PDF 74LS490 74LS490 55MHz N74LS490N 1N916, 1N3064, 500ns Signetics 565 1N3064 1N916 74LS N74LS490N
74LS490

Abstract: 198S 1N3064 1N916 74LS ISM040S N74LS490N bcd counter 74 90 pin diagram of 74LS
Text: Œ ZI 74LS490 Counter Dual BCD Decade Ripple Counter Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74LS490 55MHz 15mA ORDERING CODE PACKAGES , Counter 74LS490 LOGIC DIAGRAM -t>o- (4.12) ^ 0.15) CP (2,14) R„' I CP «D S (3,13) J8" 0 , Product Specification Counter 74LS490 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 74LS490 UNIT Min Typ2 Max


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PDF 1N916, 1N3064, 500ns 74LS490 198S 1N3064 1N916 74LS ISM040S N74LS490N bcd counter 74 90 pin diagram of 74LS
bcd decade counter ttl

Abstract: FAST AND LS TTL truth table NOT gate 74 74LS490 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/ 74LS490 DUAL DECADE COUNTER The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code. · · · · Dual Version of SN54 / 74LS490 , SN54 / 74LS490 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC , Test Conditions FAST AND LS TTL DATA 5-564 VCC = 5.0 V SN54/ 74LS490 AC CHARACTERISTICS (TA


Original
PDF SN54/74LS490 74LS490 74LS490 bcd decade counter ttl FAST AND LS TTL truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Not Available

Abstract: No abstract text available
Text: Signetics 74LS490 Counter Dual BCD Decade Ripple Counter Product Specification Logic , Reset (clear) TYPE 74LS490 TYPICAL f max 55MHz TYPICAL SUPPLY CURRENT (TOTAL) 15mA ORDERING CODE , P roduct S p ecification Counter 74LS490 LOGIC DIAGRAM MODE SELECTION - FUNCTION TABLE , n Counter 74LS490 DC ELECTRICAL CHARACTERISTICS PARAMETER Voh V ol V|k . 1 1 ih HIGH-level , .) 74LS490 TEST CONDITIONS1 Min Typ2 3.4 0.35 0.25 0.5 0.4 -1 .5 MR, MS inputs CP input MR, MS inputs 0.1 0.2


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PDF 74LS490 74LS490 55MHz N74LS490N 1N916, 1N3064, 500ns 500ns
Not Available

Abstract: No abstract text available
Text: Signetics Counter 74LS490 Dual BCD Decade Ripple Counter Product Specification Logic , Reset (clear) TYPE 74LS490 TYPICAL fMAX 55MHz TYPICAL SUPPLY CURRENT (TOTAL) 15mA ORDERING CODE , 5-564 853-0488 81500 Signetics Logic Products Product S p ecification Counter 74LS490 , Signetics Logic Products Product S pecifica tio n Counter 74LS490 DC ELECTRICAL CHARACTERISTICS PARAMETER Voh (Over recommended operating free-air temperature range unless otherwise noted.) 74LS490


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PDF 74LS490 74LS490 55MHz 1N916, 1N3064, 500ns
Not Available

Abstract: No abstract text available
Text: / 74LS490 G U A R A H TC EO O Pg R A TlW O R A H aES SYMBOL VCC Ta >OH >OL Supply Voltage Operating Ambient , TYP MAX UNITS ns ns TEST CONDITIONS VCC - 5.0 V 20 25 FAST AND LS TTL DATA SN54/ 74LS490 AC


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PDF 54LS/74 LS490
Not Available

Abstract: No abstract text available
Text: (M) MOTOROLA SN54/ 74LS490 DUAL DECADE COUNTER The S N 54/74LS 490 contains a pair of high-speed 4-stage ripple counters. Each half of the S N 54/74LS 490 has individual Clock, Master Reset and Mas­ ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code. • Dual Version of , SN54/ 74LS490 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC , 5-354 SN54/ 74LS490 AC CHARACTERISTICS (T A = 2 5 °C ) Limits Symbol Parameter Min


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PDF SN54/74LS490 54/74LS
74LS93 P

Abstract: TTL 74LS93 TTL 74293 74293 pin diagram 74LS78 74176 74LS93 74LS490 74LS373 74293
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 —_ _ •— J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft—12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7—0 10—0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/ 74LS490 (each half) 4,12 , Asynchronous 54LS/ 74LS490 2x5 — X 50 6.0 100 D84 4L,6B,9B 20 Variable Modulo 9305 2x5,6,7,8 — J~ 26 44 210


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS290 54LS/74LS293 74LS93 P TTL 74LS93 TTL 74293 74293 pin diagram 74LS78 74176 74LS93 74LS490 74LS373 74293
74LS490

Abstract: No abstract text available
Text: L H 3 4 5 6 7 8 9 MOTOROLA SCHOTTKY TTL DEVICES SN 54LS/ 74LS490 GUARANTEED , 5-314 SN 54LS/ 74LS490 AC CHARACTERISTICS: Ta = 2S°C SYMBOL f MAX tPLH 'PHL 'PLH 'PHL 'PLH 'PHL


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PDF SN54LS490 SN74LS490 /74LS 54LS/74LS490 74LS490
counter 74490

Abstract: of 74ls90 IC decade counter
Text: SN 74LS490 . . . D, J OR N PA CKA G E (T O P V IE W ) 1CLK 1CLR 1QA 1SET9 1ÛB 1ÛC IQ d C c , 92 2QB 2QC 2Qn SN 54LS490 SN 74LS490 FK PA C K A G E FN P A C K A G E (T O P V IE W ) CC , reference. l SN 74LS490 M IN 4 .7 5 NOM 5 M AX 5 .2 5 -400 8 0 20 251 125 0 70 25 5 .5 NOM 5 M AX , .7 TYPÎ M AX M IN 2 SN 74LS490 TYPÎ M AX U N IT V 0 .8 - 1 .5 2 .7 3.4 0 .2 5 0 .3 5 0 .4


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PDF SN54490, SN54LS490, SN74490, SN74LS490 54LS90, 74LS90 counter 74490 of 74ls90 IC decade counter
74ls90 logic

Abstract: 74LS90 pin diagram of 74LS 74LS90 pin configuration 54LS490DM 54LS490FM 74LS490DC 74LS490FC 74LS490PC
Text: Vcc = +5.0 V ±10%, Ta = -55° C to +125°C TYPE Plastic DIP (P) A 74LS490PC 9B Ceramic DIP (D> A 74LS490DC 54LS490DM 6B Flatpak (F) A 74LS490FC 54LS490FM 4L CONNECTION DIAGRAM PINOUT A CPa [T *— 71 , 490 /c O 5 7 54LS/ 74LS490 DUAL DECADE COUNTER DESCRIPTION—The '490 contains a pair of high speed 4-stage ripple counters. Each half of the '490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8421 BCD code. • DUAL VERSION OF 54LS/74LS90 â


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PDF 54LS/74LS490 54LS/74LS90 74LS490PC 74LS490DC 54LS490DM 54/74LS 74ls90 logic 74LS90 pin diagram of 74LS 74LS90 pin configuration 54LS490FM 74LS490FC 74LS490PC
TTL 74293

Abstract: 74LS90 D127 74290 D124 74LS92 74LS93 7490 TTL 7493A 74LS197
Text: /74LS196 54/74197 54LS/74LS197 54LS/74LS290 54LS/74LS293 54LS/74LS390 54LS/74LS393 54LS/ 74LS490 9305 93S05


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PDF 54/7490A 54LS/74LS90 74LS92 54/7493A 54LS/74LS93 54LS/74LS196 54LS/74LS60 TTL 74293 74LS90 D127 74290 D124 74LS93 7490 TTL 7493A 74LS197
74162

Abstract: 74LS191 D129 pin diagram of 74163 74160 pin 74192 74LS190 pins 74LS162 74190 presettable digital clock
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 —_ _ •— J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft—12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7—0 10—0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/ 74LS490 (each half) 4,12 p—15 1,15—Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS163 54LS/74LS168 74162 74LS191 D129 pin diagram of 74163 74160 pin 74192 74LS190 pins 74LS162 74190 presettable digital clock
TTL 74293

Abstract: 7490A 74LS93 ttl 74LS173 TTL 7493A 74LS293 Asynchronous counter 74293 74LS293 pin D187 tc 9310
Text: 54LS/74LS393 2x8 — X 60 36 64 D195 4L,6B,9B 19 Asynchronous 54LS/ 74LS490 2x5 — X 50 6.0 100 D84 4L


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PDF 54LS/74LS173 54LS/74LS375 54LS/74LS390 54LS/74LS393 54LS/74LS290 54LS/74LS293 54LS/74LS390 54LS/74LS393 54LS/74LS490 93S05 TTL 74293 7490A 74LS93 ttl 74LS173 TTL 7493A 74LS293 Asynchronous counter 74293 74LS293 pin D187 tc 9310
counter 74490

Abstract: counter SN 74490 74490 SN7490 An 7522 ph DECADE 74490 ic la 7522
Text: temperature range of -5 5 °C to 125°C ; the SN 74490 and SN 74LS490 are characterized for use in industrial , .- 5 5 ° C to 125°C SN 74LS490 0 °C to 7 0 °C Storage temperature r a n g e , TYpt M AX M IN 2 SN 74LS490 TYPÎ U N IT V V V V TMA Vql Low-level output voltage mA


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PDF SNS4490, SN54LS490, SN74490. SN74LS490 SN5490A, SN54LS90, SN7490A, SN74LS90 counter 74490 counter SN 74490 74490 SN7490 An 7522 ph DECADE 74490 ic la 7522
sn 7492 ttl

Abstract: TTL 7493A 74293 pin diagram TTL 74293 7493A 74LS93 74162 74LS183 74293 74LS90
Text: Asynchronous 54LS/74LS393 2x8 — X 60 36 64 D195 4L,6B,9B 19 Asynchronous 54LS/ 74LS490 2x5 — X 50 6.0 100


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PDF 54/7490A, 54LS/74LS90 74LS92 S4/74293, 54LS/74LS293 S4/7493A, 54LS/74LS93 93L10, 93S10, 93L16, sn 7492 ttl TTL 7493A 74293 pin diagram TTL 74293 7493A 74LS93 74162 74LS183 74293 74LS90
7490A

Abstract: TTL 74293 74290 74LS93 7493A 93S62 74196 TTL ttl 7492 D115 D114
Text: / 74LS490 2x5 — X 50 6.0 100 D84 4L,6B,9B 20 Variable Modulo 9305 2x5,6,7,8 — J~ 26 44 210 D126 3I,7A


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PDF 93S43 93S62 54LS/74LS290 54LS/74LS293 54LS/74LS390 54LS/74LS393 54LS/74LS490 93S05 93L10 7490A TTL 74293 74290 74LS93 7493A 93S62 74196 TTL ttl 7492 D115 D114
Not Available

Abstract: No abstract text available
Text: HD74LS490. This circuit contains eight to ditional gating Dual 4-bit Decade Counters master-slave flip-flops and ad IBLOCK DIAGRAM (K) implement tw o individual 4-bit decade counters. Each decade counter has individual clock, clear, and set-to-9 inputs. BC D count sequences of any length up to divide-by-100 may be implemented with a single HD 74LS490. Buffering on each output is provided to ensure that suceptibility to collector communication is reduced significantly. All inputs are


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PDF HD74LS490. divide-by-100 74LS490. T-90-10 ib203
ttl 741

Abstract: 1. IC 74IS244 74LS244 diagram Fairchild 96106 741 16 PIN 74S140 E105 74S40
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 —_ _ •— J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft—12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7—0 10—0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/ 74LS490 (each half) 4,12 p—15 1,15—Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 74LS245 74ILS540 ttl 741 1. IC 74IS244 74LS244 diagram Fairchild 96106 741 16 PIN 74S140 E105 74S40
7475 D latch

Abstract: D146 D147 ci 7475 74LS109 rs latch 74LS78 74LS107 7475 data latch 74LS114
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 —_ _ •— J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ft—12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7—0 10—0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/ 74LS490 (each half) 4,12 p—15 1,15—Q 14 13 12 11 Vcc = Pin 16 GND = Pin 8 MS CP MR Qo Ol 02 03 2,14 5,11 7,9 3,13 8


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS279 93L14 7475 D latch D146 D147 ci 7475 74LS109 rs latch 74LS78 74LS107 7475 data latch 74LS114
Not Available

Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS490 KH4U4qo Dual 4 -bit Decade Counters D escrip tio n DN 74LS490 contains two asynchronous decade counter circuits with direct coupled reset input and nine direct-coupled set inputs. Features · Two circuits corresponding to LS90 and L S290 for high mounting density · Independent direct-coupled reset input and nine directcoupled set inputs for each circuit · High-speed counting (fmax = 35MHz typical) · Wide operating temperature range (Ta = - 2 0 to +75°C). A b solu te m


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PDF DN74LS DN74LS490 74LS490 35MHz DN74LS490 16-pin SO-16D) MA161
Supplyframe Tracking Pixel