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Part Manufacturer Supplier Stock Best Price Price Each Buy Part
74LS256DC National Semiconductor Corporation Rochester Electronics 4,042 $1.79 $1.46
74LS256PC National Semiconductor Corporation Rochester Electronics 1,933 $0.43 $0.35
SN74LS256D ON Semiconductor Rochester Electronics 5,510 $0.36 $0.29
SN74LS256J Motorola Semiconductor Products Bristol Electronics 64 $4.48 $2.09

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74LS256 datasheet (6)

Part Manufacturer Description Type PDF
74LS256 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
74LS256 Signetics Dual 4-Bit Addressable Latch Scan PDF
74LS256 Signetics Dual 4-Bit Addressable Latch Scan PDF
74LS256DC Fairchild Semiconductor Dual 4-Bit Addressable Latch Scan PDF
74LS256FC Fairchild Semiconductor Dual 4-Bit Addressable Latch Scan PDF
74LS256PC Fairchild Semiconductor Dual 4-Bit Addressable Latch Scan PDF

74LS256 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74256

Abstract: ttl 74256
Text: Signetìcs Latch 74LS256 Dual 4-Bit Addressable Latch Product Specification Logic , Clear input · Useful as dual 1-of-4 active HIGH decoder TYPE 74LS256 TYPICAL PROPAGATION DELAY 19ns , 74LS256 LOGIC DIAGRAM L002161S MODE SELECT- FUNCTION TABLE OPERATING MODE Clear Demultiplex , 5-438 Signetics Logic Products Product Specificotion Latch 74LS256 ABSOLUTE MAXIMUM , . December 4, 1985 5-439 Signetics Logic Products Product Specification Latch 74LS256 AC


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PDF 74LS256 SO-16 N74LS256N N74LS256D 1N916, 1N3064, 500ns 500ns 74256 ttl 74256
74256

Abstract: 74LS256 1N916 74LS N74LS256D N74LS256N
Text: Signetics 74LS256 Latch Logic Products Dual 4-Bit Addressable Latch Product Specification , latches, the enable TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS256 19ns 22mA , 74LS256 MODE SELECT—FUNCTION TABLE OPERATING INPUTS OUTPUTS MODE CLR Ë D A0 Ai Qo Qi o2 Qa , Respective Manufacturer Signetics Logic Products Product Specification Latch 74LS256 ABSOLUTE MAXIMUM , Copyrighted By Its Respective Manufacturer Signetics Logic Products Product Specification Latch 74LS256 AC


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PDF 74LS256 1N916, 1N3064, 500ns 74256 74LS256 1N916 74LS N74LS256D N74LS256N
ttl 74256

Abstract: 74256
Text: Signelics 74LS256 Latch Dual 4-Bit Addressable Latch Product Specification Logic Products , , the enable TYPE 74LS256 TYPICAL PROPAGATION DELAY 19ns TYPICAL SUPPLY CURRENT (TOTAL) 22mA , 7 853*0465 81500 Signetics Logic Products Product Specification Latch 74LS256 , Product Specification Latch 74LS256 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature , Product Specification Latch 74LS256 AC ELECTRICAL CHARACTERISTICS ta = 25"C, Vcc = 5.0V


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PDF 74LS256 1N916, 1N3064, 500ns 500ns ttl 74256 74256
1996 - SN54LSXXXJ

Abstract: SN74LSXXXD SN74LSXXXN
Text: SN54/ 74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/ 74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E , TTL DATA 14 13 10 11 12 SN54/ 74LS256 LOGIC DIAGRAM E Da 14 3 4 A0 , -Channel Demultiplexer Clear FAST AND LS TTL DATA 5-2 MODE SN54/ 74LS256 GUARANTEED OPERATING RANGES Symbol , 5-3 VCC = 5.0 V, 50V CL = 15 pF SN54/ 74LS256 AC SET-UP REQUIREMENTS (TA = 25°C) Limits


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PDF SN54/74LS256 SN54/74LS256 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Not Available

Abstract: No abstract text available
Text: MOTOROLA SN54/ 74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/ 74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A q , A-|), an active LOW Enable , SN54/ 74LS256 LOGIC DIAGRAM VCC = PIN 16 GND = PIN 8 0 = PIN NUMBERS TRUTH TABLE CL L L L L L , -Channel Demultiplexer Clear FAST AND LS TTL DATA 5-262 SN54/ 74LS256 GU ARANTEED OPERATING RANGES S ym bol VCC , SN54/ 74LS256 AC SET-UP REQUIREMENTS (TA = 25°C) L im its Sym bol Param eter Data Setup Time ts th


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PDF SN54/74LS256
Not Available

Abstract: No abstract text available
Text: (M ) M O TO R O LA SN54/ 74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/ 74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (Ao, A-|), an active LOW , Q3a 4 E 10 11 12 SN54/ 74LS256 LOGIC DIAGRAM Vcc = PIN 16 GND = PIN 8 0 = , ultiplexer H L C lear MODE FAST AND LS T T L DATA 5-262 Latch SN54/ 74LS256 GUARANTEED , bol FAST AND LS TTL DATA 5-263 V C C = 5 0 V, C l - 15 pF SN54/ 74LS256 AC SET-UP


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PDF SN54/74LS256 SN54/74LS256
74256

Abstract: ttl 74256 74LS256 demultiplexer 74ls 1N3064 1N916 74LS N74LS256D N74LS256N
Text: Signetics 74LS256 Latch Logic Products Dual 4-Bit Addressable Latch Product Specification , latches, the enable TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74LS256 19ns 22mA , Specification Latch LOGIC DIAGRAM 74LS256 MODE SELECT—FUNCTION TABLE OPERATING INPUTS OUTPUTS , Specification Latch 74LS256 ABSOLUTE MAXIMUM RATINGS (Over operating free-air temperature range unless , Manufacturer Signetics Logic Products Product Specification Latch 74LS256 AC ELECTRICAL CHARACTERISTICS TA =


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PDF 74LS256 1N916, 1N3064, 500ns 74256 ttl 74256 74LS256 demultiplexer 74ls 1N3064 1N916 74LS N74LS256D N74LS256N
Not Available

Abstract: No abstract text available
Text: Signetics 74LS256 Latch Dual 4-Bit Addressable Latch Product Specification Logic Products , 81500 Signetics Logic Products Product Specification Latch 74LS256 LOGIC DIAGRAM MODE , , 1985 5 -4 3 8 o II Signetics Logic Products Product Specification Latch 74LS256 , Product Specification Latch 74LS256 AC ELECTRICAL CHARACTERISTICS T A = 2 5 " C, V oe = 5.0V , Products Product Specification Latch 74LS256 AC WAVEFORMS 'A - 'P H L - f Hi < L 1 -'P


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PDF 74LS256 4LS256N 1N916, 1N3064, 500ns 500ns
74ls70

Abstract: No abstract text available
Text: Signetics 74LS256 Latch Dual 4-Bit Addressable Latch Product Specification Logic Products , S pecifications, s ee the Signetics M ilitary Products D ata M anual. TYPE 74LS256 TYPICAL , Signetics Logic Products P roduct S p ecification Latch 74LS256 LOGIC DIAGRAM MODE , Products P roduct S p ecification Latch 74LS256 ABSOLUTE MAXIMUM RATINGS Vcc V|N i|N Vqut Ta , roduct S pecifica tio n Latch 74LS256 AC ELECTRICAL CHARACTERISTICS TA = 25»C, Vc c = 5.0V


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PDF 74LS256 SO-16 N74LS256N N74LS256D 500ns 500ns 74ls70
74LS256

Abstract: SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Text: SN54/ 74LS256 DUAL 4-BIT ADDRESSABLE LATCH The SN54/ 74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E , Q0a Q1a Q2a Q3a 4 14 13 10 11 12 SN54/ 74LS256 LOGIC DIAGRAM E 14 3 Da , -Channel Demultiplexer Clear FAST AND LS TTL DATA 5-422 MODE SN54/ 74LS256 GUARANTEED OPERATING RANGES , , CL = 15 pF SN54/ 74LS256 AC SET-UP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min


Original
PDF SN54/74LS256 SN54/74LS256 74LS256 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Not Available

Abstract: No abstract text available
Text: / 74LS256 LO G IC SYM BOL 3 I °a 2 1 15 k e An A0 A1 CL 14 13 1 1 I I *0 A1 CL E , SCHOTTKY TTL DEVICES SN54LS/ 74LS256 / P C C H A R A C T E R IS T IC S O V ER O PERA TIN G T EM P , SCHOTTKY TTL DEVICES SN54LS/ 74LS256 A C S E T U P R EQ U IREM EN TS: TA = 25°C SYM BOL *s ts 'h ih


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PDF
Not Available

Abstract: No abstract text available
Text: M O TOR OLA SN54/ 74LS256 D E S C R IP T IO N - T h e S N 5 4 L S / 7 4 L S 2 5 6 is a D ual 4 -B it Addressable Latch w ith common control inputs; th ese include tw o Address inputs (A o, A i ) , an active LO W En able input (E ) and an actiyè LO W C le a r input (CL). E ach latch h a s a Data , °C mA mA Vcc ta 'oh *o l FAST AND LS TTL DATA SN54/ 74LS256 DC CHAHACTCW SnCS OVER , L = 15p F Fig. 3 V Cc = 5.0 V, CL = 1 5 p F Fig. 5 FAST AND US TTL DATA 5-220 SN54/ 74LS256


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PDF SN54/74LS256
74LS78

Abstract: D flip-flop 74175 pin 93L38 74ls373 74LS374 D190 D150 74LS374 74LS373 74ls373 D Flip-Flop D134
Text: /74LS374 D87 54LS/ 74LS256 3 4 7 8 13 14 17 18 Do Di 02 D3 D4 Ds De D7 11 - CP 1 —0 OE , / 74LS256 8xD X 2(L) 12 20 20 100 ID87 4L,6B,9B 11 6-Bit D Flip-Flop 54/74174 6 L 1(-T) 20 20 — 225 D152


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 /74LS573 93L34 74LS78 D flip-flop 74175 pin 93L38 74ls373 74LS374 D190 D150 74LS374 74LS373 74ls373 D Flip-Flop D134
74162

Abstract: 74LS191 D129 pin diagram of 74163 74160 pin 74192 74LS190 pins 74LS162 74190 presettable digital clock
Text: /74LS374 D87 54LS/ 74LS256 3 4 7 8 13 14 17 18 Do Di 02 D3 D4 Ds De D7 11 - CP 1 —0 OE


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS163 54LS/74LS168 74162 74LS191 D129 pin diagram of 74163 74160 pin 74192 74LS190 pins 74LS162 74190 presettable digital clock
74ls373 parallel port

Abstract: d92 02 74175 ttl pin diagram 74ls175 pin diagram 74198 74198 ttl D173 9z17 74LS194 93L38
Text: /74LS374 D87 54LS/ 74LS256 3 4 7 8 13 14 17 18 Do Di 02 D3 D4 Ds De D7 11 - CP 1 —0 OE , 54/74116 8xD 2xL 2x2 AND 15 19 12 300 D151 4M,6N,9N 10 Dual 4-Bit Addr. Latch 54LS/ 74LS256 8xD X 2(L


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 /74LS573 93L34 74ls373 parallel port d92 02 74175 ttl pin diagram 74ls175 pin diagram 74198 74198 ttl D173 9z17 74LS194 93L38
Not Available

Abstract: No abstract text available
Text: ackage C1 P lastic C hip C arrier O R D ER IN G NUM BER S: T 54LS256 D2 T74LS 256 C1 T 74LS256 D1 T74LS 256 M1 T 74LS256 B1 PIN CONNECTION (top view) DUAL IN LINE • SERIAL-TO-PARALLEL


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PDF T54LS256/T74LS256
Not Available

Abstract: No abstract text available
Text: ±5%, T a = 0 °C to +70° C 74LS256PC 74LS256DC 74LS256FC 54LS256DM 54LS256FM MILITARY GRADE V cc = +5.0 , 256 CO NN ECTIO N DIAGRAM PINOUT A 54LS/ 74LS256 v n u ~ f DUAL 4-BIT ADDRESSABLE LATCH AoQ A ,H D , [3 SI V C C i s ] CL 14J È T â jD b H ]Q 3 b ï j ] Q 2b ]Ö | Q i b J ]Q o b DESCRIPTION - The '256 is a dual 4-b it addressable latch w ith com m on control inputs; these include tw o Address inputs (Ao, Ai), an active LOW En able in put (E) and an active LOW Clear input (CL). Each latch


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PDF 54LS/74LS256 54/74LS
D flip-flop 74175 pin

Abstract: 74175 D flip flop 8-bit ttl latch D134 93L38 74LS573 D187 D154 ttl 7497 74ls175 pin diagram
Text: -Bit Addr. Latch 54LS/ 74LS256 8xD X 2(L) 12 20 20 100 ID87 4L,6B,9B 11 6-Bit D Flip-Flop 54/74174 6 L 1(-T


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PDF 54LS/74LS173 54LS/74LS375 54LS/74LS390 54LS/74LS393 /74LS573 93L34 54LS/74LS259 93L38 54LS/74LS170 54ILS/74LS670 D flip-flop 74175 pin 74175 D flip flop 8-bit ttl latch D134 74LS573 D187 D154 ttl 7497 74ls175 pin diagram
74LS93 P

Abstract: TTL 74LS93 TTL 74293 74293 pin diagram 74LS78 74176 74LS93 74LS490 74LS373 74293
Text: /74LS374 D87 54LS/ 74LS256 3 4 7 8 13 14 17 18 Do Di 02 D3 D4 Ds De D7 11 - CP 1 —0 OE


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS290 54LS/74LS293 74LS93 P TTL 74LS93 TTL 74293 74293 pin diagram 74LS78 74176 74LS93 74LS490 74LS373 74293
74LS573

Abstract: 74LS573 "LATCH" 74LS573 latch d flip-flop D178 D177 D190 D150 93L38 7491 8-bit
Text: / 74LS256 8xD X 2(L) 12 20 20 100 ID87 4L,6B,9B 11 6-Bit D Flip-Flop 54/74174 6 L 1(-T) 20 20 — 225 D152


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PDF 93L28 54LS/74LS573 54LS/74LS352 54LS/74LS353 /74LS573 93L34 54LS/74LS259 93L38 54LS/74LS170 54ILS/74LS670 74LS573 74LS573 "LATCH" 74LS573 latch d flip-flop D178 D177 D190 D150 7491 8-bit
7475 d-flip flop

Abstract: 7475 D flip-flop ci 7475 D134 74279 9374 93L38 FLIP FLOP 7475 Register 7475 93L08
Text: 54/74116 8xD 2xL 2x2 AND 15 19 12 300 D151 4M,6N,9N 10 Dual 4-Bit Addr. Latch 54LS/ 74LS256 8xD X 2(L


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PDF 93L14 54LS/74LS279 54LS/74LS75 93L08, 54LS/74LS77 /74LS573 93L34 54LS/74LS259 93L38 54LS/74LS170 7475 d-flip flop 7475 D flip-flop ci 7475 D134 74279 9374 FLIP FLOP 7475 Register 7475 93L08
74191 8 bit

Abstract: 93L21 74LS152 D134 D flip-flop 74175 pin D132 7442 logic diagram 74155 D133 74155 PIN DIAGRAM
Text: 2xL 2x2 AND 15 19 12 300 D151 4M,6N,9N 10 Dual 4-Bit Addr. Latch 54LS/ 74LS256 8xD X 2(L) 12 20 20 100


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PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 74191 8 bit 93L21 74LS152 D134 D flip-flop 74175 pin D132 7442 logic diagram 74155 D133 74155 PIN DIAGRAM
7443 Flip-Flop

Abstract: 74191 8 bit D134 7443 d Flip-Flop 74LS42 93L38 9B23 93L11 D135 74155
Text: / 74LS256 8xD X 2(L) 12 20 20 100 ID87 4L,6B,9B 11 6-Bit D Flip-Flop 54/74174 6 L 1(-T) 20 20 — 225 D152


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PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 7443 Flip-Flop 74191 8 bit D134 7443 d Flip-Flop 74LS42 93L38 9B23 93L11 D135 74155
74153 mux

Abstract: MUX 74157 74174 shift register 74157 mux CI 74151 mux 74153 74LS152 D flip-flop 74175 pin 74152 mux MUX 74151
Text: 300 D151 4M,6N,9N 10 Dual 4-Bit Addr. Latch 54LS/ 74LS256 8xD X 2(L) 12 20 20 100 ID87 4L,6B,9B 11 6


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PDF 54LS/74LS170, 54LS/74LS670 93L09 54LS/74LS298 93L22, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257 74153 mux MUX 74157 74174 shift register 74157 mux CI 74151 mux 74153 74LS152 D flip-flop 74175 pin 74152 mux MUX 74151
ttl 741

Abstract: 1. IC 74IS244 74LS244 diagram Fairchild 96106 741 16 PIN 74S140 E105 74S40
Text: /74LS374 D87 54LS/ 74LS256 3 4 7 8 13 14 17 18 Do Di 02 D3 D4 Ds De D7 11 - CP 1 —0 OE


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 74LS245 74ILS540 ttl 741 1. IC 74IS244 74LS244 diagram Fairchild 96106 741 16 PIN 74S140 E105 74S40
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