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LTC2656CIFE-L16#TRPBF Linear Technology LTC2656 - Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
LTC1450LIG Linear Technology IC PARALLEL, WORD INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDSO24, 0.209 INCH, PLASTIC, SSOP-24, Digital to Analog Converter
LTC2636CDE-LMI10#TRPBF Linear Technology LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference; Package: DFN; Pins: 14; Temperature Range: 0°C to 70°C
LTC2636HDE-HZ10#TRPBF Linear Technology LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference; Package: DFN; Pins: 14; Temperature Range: -40°C to 125°C
LTC2636IDE-HMX10#TRPBF Linear Technology LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference; Package: DFN; Pins: 14; Temperature Range: -40°C to 85°C
LTC2636HMS-LMI10#PBF Linear Technology LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

74LS138 3 to 8 decoder notes Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function 74LS138 LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
Text: Signetics 74LS138 , S138 Decoders/Demultiplexers 1-Of- 8 Decoder /Demultiplexer Product , de vice to a 1-of-32 (5 lines to 32 lines) decoder with just four '1 38 s and one inverter. The , state Operating free-air temperature range 74LS 7.0 -0.5 to +7.0 - 3 0 to +1 " 0.5 to +V cc 0 to 70 74S 7.0 -0.5 to +5.5 - 3 0 to +5 -0.5 to + V cc UNIT V V mA V "C RECOMM ENDED OPERATING CONDITIONS , expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138


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PDF 74LS138, 74LS138 74S138 N74S13BN, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
74ls138 truth table

Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74ls138 demultiplexer demultiplexer 3 to 8 truth table 74LS138 3 to 8 decoder Pin LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
Text: (g) MOTOROLA 1-0F-8 DECODER / DEMULTIPLEXER The LSTTL/MSI SN54/ 74LS138 is a high speed 1-of- 8 , AND LS TTL DATA SN54/ 74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of- 8 Decoder , decoding. The multiple input enables allow parallel ex pansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , Effects SN54/ 74LS138 1-0F-8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY ranimniinfmninm VCC Oo


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PDF SN54/74LS138 1-of-24 LS138 1-of-32 LS138s SN54/74LS138 74ls138 truth table 74LS138 74 LS 138 DECODER connection for 74LS138 74ls138 demultiplexer demultiplexer 3 to 8 truth table 74LS138 3 to 8 decoder Pin LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
1996 - 74LS138

Abstract: 74LS138 3 to 8 decoder Pin 74LS138 pin diagram ls138 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
Text: SN54/ 74LS138 1-OF- 8 DECODER / DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of- 8 , decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1-OF- 8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability , = PIN 8 = PIN NUMBERS 6 1 2 3 456 12 3 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 15


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PDF SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder Pin 74LS138 pin diagram 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
LOGIC OF 74LS138

Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder TTL 74ls138 74ls138 function 74LS138 3 to 8 decoder Pin
Text: Signetics 74LS138 , S138 Decoders/Demultiplexers 1-Of- 8 Decoder /Demultiplexer Product , 27 12 ns tPHL Address to output 3 logic levels 39 12 tpLH Propagation delay Waveform 2 18 8 , 16 GND = Pin 8 FUNCTION TABLE inputs outputs e, e2 e3 a0 ai a2 0 1 2 3 4 5 6 7 H X X , Enable to output 3 logic levels 38 11 TEST CIRCUITS AND WAVEFORMS Test Circuit For 74 Totem-Pole , '138 decoder accepts three binary weighted inputs (A0, A), A2) and when enabled, provides eight


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PDF 74LS138, 1-of-32 1N916, 1N3064, 500ns LOGIC OF 74LS138 pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder TTL 74ls138 74ls138 function 74LS138 3 to 8 decoder Pin
LOGIC OF 74LS138

Abstract: 74LS138 3 to 8 decoder notes 74LS138 pin configuration 74LS138 pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
Text: Signetics 74LS138 , S138 Decoders/Demultiplexers 1-Of- 8 Decoder /Demultiplexer Product , -of-32 (5 lines to 32 lines) decoder with just four '138s and one inverter. The device can be used as an , , Hl °2 33 ° 3 HIÖ 4 70)05 I]0 8 C D 0 4 6 1 0 S *2 OE È, [T È2 U E stl Ö 7Ü S N D []r December , .) 74LS 7.0 -0 .5 to +7.0 - 3 0 to +1 -0 .5 to + V (X 0 to 70 74S 7.0 -0 .5 to +5 .5 - 3 0 to + 5 - 0 .5 , expansion · Ideal for memory chip select decoding · Direct replacement for Intel 3205 TYPE 74LS138 74S138


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PDF 74LS138, 74LS138 74S138 N74S138N, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns LOGIC OF 74LS138 74LS138 3 to 8 decoder notes 74LS138 pin configuration pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
FUNCTIONAL APPLICATION OF 74LS138

Abstract: 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 pin diagram 74ls138 function 74LS138 pin for 74LS138 LOGIC DESCRIPTION OF 74LS138 74LS138 application note
Text: Am25LS138 • Am54LS/ 74LS138 3 -Line To 8 -Line Decoder /Demultiplexer DISTINCTIVE , DIAGRAM FUNCTIONAL DESCRIPTION The Am25LS138 is a 3 -line to 8 -line decoder /demultiplexer fabricated , VCC Y0 Y1 Y2 y3 y4 v5 y6 nnnnnnnn 15 14 13 12 >1 10 9 1 2 3 4 5 6 7 8 UUUUUUUU ABC G2A G2B G1 V7 , Ground Potential 0>inJ6 to Pin 8 ) Continuous DC Voltage Applied to Outputs for HIG HO ut p ut^State , . DEFINITION OF FUNCTIONAL TERMS A, B, C Select. The three select inputs to the decoder . G1 The active-HIGH


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PDF Am25LS138 Am54LS/74LS138 Am25LS MIL-STD-883 LS/54 LS/74LS138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 pin diagram 74ls138 function 74LS138 pin for 74LS138 LOGIC DESCRIPTION OF 74LS138 74LS138 application note
74LS138 3 to 8 decoder notes

Abstract: 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola 74ls138
Text: SN54/ 74LS138 1-OF- 8 DECODER / DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of- 8 , / 74LS138 FUNCTIONAL DESCRIPTION The LS138 is a high speed 1-of- 8 Decoder /Demultiplexer fabricated with , decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32 decoder using four LS138s and one inverter. The LS138 is fabricated with the , . · · · · · 1-OF- 8 DECODER / DEMULTIPLEXER LOW POWER SCHOTTKY Demultiplexing Capability


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PDF SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder notes 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola
CI 74LS138

Abstract: 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74ls138 configuration
Text: HIGH or active LOW state. 74LS138 , S138 Decoders/Demultiplexers 1-Of- 8 Decoder /Demultiplexer Product , to 32 lines) decoder with just four '138s and one inverter. The device can be used as an eight , delay Address to output Waveform 1 3 logic levels 27 39 12 12 ns •PLH tpHL Propagation delay Enable to output Waveform 2 2 logic levels 18 32 8 11 ns tPLH •PHL Propagation delay Enable to output , DESCRIPTION The '138 decoder accepts three binary weighted inputs (A0, A, A2) and when enabled, provides


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PDF -of-32 1N916, 1N3064, 500ns CI 74LS138 74LS138 pin configuration TTL 74ls138 74ls138 function 74 LS 138 DECODER intel 3205 74ls138 74l5138 of 74LS138 3 to 8 decoder 74ls138 configuration
1998 - block diagram of 74LS138 3 to 8 decoder

Abstract: 74LS138 3 to 8 decoder notes 12C508 74LS138 DATASHEET block diagram of 74LS138 1 line to 16 line 74LS138 application note PIC12C508 of 74LS138 3 to 8 decoder 74LS138 pin diagram 74LS138 data sheet
Text: TSL230 and a 74LS138 3 line to 8 line decoder tied to some LED's, we can construct a UV monitor. This , pins to a 74LS138 to display the suggesed SPF on the 8 LED's. Block Diagram: Display TSL230 , battery 16 6 7 9 10 11 12 13 14 15 74LS138 3 +5 1 7 +5 2 6 5 1 1 5 4 MHz 8 33 pF 2 0.1 pF 8 2 4 7 3 TSL230 4 GP3 input 8 freq. out 3 6 4 5 33 pF +5 PIC12C508 0.1 pF © 1998 Microchip


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PDF PIC12C508. PIC12C508 TSL230 74LS138 DS40160A/5 016-page NJM78L05A 74LS138 block diagram of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 12C508 74LS138 DATASHEET block diagram of 74LS138 1 line to 16 line application note PIC12C508 of 74LS138 3 to 8 decoder 74LS138 pin diagram 74LS138 data sheet
1987 - intel 8085 microprocessor

Abstract: 8085 memory organization 8085 microprocessor 74LS373 Decoder latch used for 8085 8085 clock circuit ic 74ls138 8085 hardware reset 8085 microprocessor application 74LS138 decoder
Text: a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual Chip , Character Interface to 6808 Microprocessor 2 74LS04 74LS138 DECODER G-1 G-2A G-2B Y4 C Y5 B Y6 A Y7 11 10 9 , the addition of a 74LS138 decoder . The 74LS138 is used to generate individual Chip Enables for each of , an eight byte Character RAM, an 8 bit Flash RAM, a 128 character ASCII decoder , a 16 symbol , from the 74LS138 decoder . The display system can be shortened by removing HDSP-211X displays from the


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PDF HDSP-211X HDSP-211X, intel 8085 microprocessor 8085 memory organization 8085 microprocessor 74LS373 Decoder latch used for 8085 8085 clock circuit ic 74ls138 8085 hardware reset 8085 microprocessor application 74LS138 decoder
2006 - 8085 microprocessor

Abstract: intel 8085 microprocessor IC 74ls138 8085 memory organization 74LS373 Decoder 8085 microprocessor Datasheet 8085 microprocesor ic 74ls138 information intel 8085 interfacing of ram with 8085
Text: addition of a 74LS138 decoder and a 74LS373 transparent latch. The 74LS138 is used to generate individual , to ensure that valid address information is stored in the latch. 1 74LS00 3 14 13 8 7 4 3 11 4 6 4 5 3 2 1 D6 D5 D4 D3 D2 D1 74LS04 2 74LS138 , be connected to an unused output from the 74LS138 decoder . The display system can be shortened by , CMOS IC consists of an eight byte Character RAM, an 8 bit Flash RAM, a 128 character ASCII decoder , a


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PDF HDSP-211x HDSP-211x, HDSP-211x 5988-5632EN 8085 microprocessor intel 8085 microprocessor IC 74ls138 8085 memory organization 74LS373 Decoder 8085 microprocessor Datasheet 8085 microprocesor ic 74ls138 information intel 8085 interfacing of ram with 8085
M02S7S7

Abstract: No abstract text available
Text: GD54/ 74LS138 3-TO-8 -LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to , . ~ 6 5 ° C to 1 5 0 ° C 2-78 M02S7S7 00DM2E3 03G GD54/ 74LS138 Application Example 4-LINE TO 16-LINE DECORDER/DEMULTIPLEXER OUTPUTS V 0 V, y 2 y 3 7, y 5 y 6 , high-performance memory systems this decode can be used to minimize the effects of system decoding. When


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PDF GD54/74LS138 Q004225 M02S7S7
Not Available

Abstract: No abstract text available
Text: Am25LS138 • Am54LS/ 74LS138 3 -Line To 8 -Line Decoder /Demultiplexer D IS T IN C T IV E C H A R , €¢ 100% product assurance screening to M IL-ST D - 8 8 3 requirements F U N C T IO N A L D E S C R IP T IO N The A m 2 5 L S l3 8 is a 3 -line to 8 -line decoder /demultiplexer fabricated using advanced , inputs. The A m 5 4 LS/7 4 LS1 3 8 is a standard performance version of the A m 2 5 LS1 3 8 . See , bient) Under Bias —5 5 °C to +125° C S upply Voltage to Ground Potential (Pin 16 to Pin 8


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PDF Am25LS138 Am54LS/74LS138 54/74LS Am25LS/54 LS/74LS138
Not Available

Abstract: No abstract text available
Text: GD54/ 74LS138 3-TO-8 -LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception Schottky Clamped for High Performance DATA O , . - 6 5 ° C to 1 5 0 ° C 4 -9 8 GD54/ 74LS138 Application Example 4-LINE TO 16 , G1 A This schottky-clamped TTL MSI circuit.is design­ ed to be used in high-performance


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PDF GD54/74LS138
block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
Text: GD54/ 74LS138 3-TO-8 -LINE DECODERS/DEMULTIPLEXERS Feature • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to Simplify , to 150°C 4-98 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS138 Application , schottky-clamped TTL MSI circuit is designed to be used in high-performance memorydecoding or data-routing , used to minimize the effects of system decoding. When employed with high-speed memories utilizing a


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PDF GD54/74LS138 block diagram of 74LS138 3 to 8 decoder block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA HCTL1100
Text: such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s. Read , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 , .7 R×D T×D PSEN ALE/P INT0 INT1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 21 22 23 24 , ;* RD1100: SETB P2.0 ; SET R/W LINE TO READ MOV CLR SETB MOV P1,B P2. 3 P2. 3 P1,#0FFH ; LATCH , HCTL-1100 P2.4 ; BRING RESET LINE HIGH RET 2-243 1 2 3 4 5 6 7 8 9 AD0


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL1100 HCTL1100. HCTL-1100s 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA
connection diagram of ic 74ls138

Abstract: ic 74ls138 pin diagram of ic 74ls138 74LS138 3 to 8 decoder notes 74ls138 truth table
Text: allow parallel expansion to a 1 -of-2 4 decoder u sing just three L S 1 3 8 devices or to a 1-of-32 decoder u sin g four L S 1 3 8 s and one inverter. The L S 1 3 8 is fabricated with the Schottky barrier , MOTOROLA < 8 > S N S N 5 4 L S 1 3 8 7 4 L S 1 3 8 D E S C R I P T I O N - The L S T T L / M S IS N 5 4 L S / 7 4 L S 1 3 8 is a high speed 1-of- 8 Decoder /Demultiplexer. This device is , DEVICES SN54LS/ 74LS138 F U N C T IO N A L D E S C R I P T I O N - T he L S 1 3 8 is a high speed l


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PDF 1-of-32 connection diagram of ic 74ls138 ic 74ls138 pin diagram of ic 74ls138 74LS138 3 to 8 decoder notes 74ls138 truth table
ic 74 LS 138 DECODER

Abstract: IC 74ls138 74LS138 3 to 8 decoder notes 74LS138 1 to 8 decoder notes ic 74 138 DECODER
Text: expansion to a 1-o f-2 4 decoder using ju st three LS 138 devices or to a l-o f- 3 2 decoder using fo u r , th e device to a 1-of-32 <5 lines to 3 2 lines) decoder w ith ju s t fo u r L S I 38s and one , (g) M OTOROLA SN 5 4 /7 4 L S 1 3 8 D E S C R IP T IO N - The L S T T L /M S IS N 5 4 L S , / 74LS138 F U N C T IO N A L D E S C R IP T IO N - The LS138 is a high speed 1-of- 8 D eco d e r/D em u , AND LS TTL DATA 5 -9 8 SN54/ 74LS138 GUARANTEED OPERATING RANGES SYMBOL PARAMETER Supply


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PDF LS138s ic 74 LS 138 DECODER IC 74ls138 74LS138 3 to 8 decoder notes 74LS138 1 to 8 decoder notes ic 74 138 DECODER
2007 - 3 to 8 line decoder using 8051

Abstract: 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET HCTL-1100 74LS138 HCTL-1100 M-015 HCTL-1100s
Text: chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 , 4 5 6 7 8 9 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 SIGN PULSE 37 40 , ;* RD1100: SETB P2.0 ; SET R/W LINE TO READ MOV CLR SETB MOV P1,B P2. 3 P2. 3 P1,#0FFH ; LATCH , HCTL-1100 P2.4 ; BRING RESET LINE HIGH RET 3 1 2 3 4 5 6 7 8 9 AD0 AD1


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL-1100. WR1100: CS1100 3 to 8 line decoder using 8051 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET 74LS138 HCTL-1100 M-015 HCTL-1100s
transistor d133

Abstract: ttl 7442 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 74LS247 74155 pin diagram of 74LS247 ttl 74191 75491
Text: Pin 16 GND = Pin 8 1 2 3 1 1 1 15 14 13 A 1 1 E Ao Ai E Ao Ai DECODER a DECODER b Oo Ol O2 O3 , 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/ 74LS138 1 2 3 4 5C ■Iii- e , D135 4L,6B,9B 5 1 -of- 8 54LS/74LS42 3 1 8 — 17 17 35 5.0 D135 4L,6B,9B 6 1-of- 8 54LS/ 74LS138 3 3 8 , 12 11 10 9 3 4 5 6 7 Vcc Pin 16 GND = Pin 8 A I 15 4 5 6 7 9 10 11 12 Vcc = Pin 16 GND = Pin 8 , = Pin 8 D137 93S137 4 1 2 3 5 6 Ä El Ao At Ä2 Ei E2 93S137 Oo Oi 02 O3 Ol O5 06 O7 TTTTTTTT


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PDF 74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 transistor d133 ttl 7442 Decoder BCD 7 seg transistor 6B 7-seg ANODE COMMON 74LS247 74155 pin diagram of 74LS247 ttl 74191 75491
pin diagram of ic 74ls138

Abstract: connection diagram of ic 74ls138 pin for 74LS138 74ls138 function SN54LS13B sn54ls138 ic 74ls138 74ls138 74S138A 74LS138 function table
Text: SN54LS13B, SN54S138, SN74LS138, SN74S13BA 3 LINE TO 8 UNE DECODERSjDEMULTIPLEXERS DECEMBER 1 9 7 2 , Schottky-clamped system decoder is negligible. The 'L S 1 3 8 , S N 5 4 S 1 3 8 , and S N 7 4 S 1 3 8 A decode one , diodes to suppress line-ringing and to simplify system design. The S N 5 4 L S 1 3 8 and S N 5 4 S 1 3 8 , The SN 7 4 LS 1 3 8 and S N 7 4 S 1 3 8 A are characterized for operation from 0 ° C to 7 0 ° C . C , . Texas SN54LS138, SN54S138, SN74LS138, SN74S138A 3 UNE TO 8 -LINE DECODERS/DEMULTIPLEXERS


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PDF SN54LS13B, SN54S138, SN74LS138, SN74S13BA 74LS138, 74S138A SN74S138A 54S138 74S138A pin diagram of ic 74ls138 connection diagram of ic 74ls138 pin for 74LS138 74ls138 function SN54LS13B sn54ls138 ic 74ls138 74ls138 74LS138 function table
64LS138

Abstract: No abstract text available
Text: S N 5 4 LS 13 8 , SN 54S138, S N 74 LS 13 8 , S N 74 S 13 8 A 3 -LINE TO 8 -LINE D EC OD ERS/DEM U , , SN54S138, SN74LS138, SN74S138A 3 -LINE TO 8 LINE DECODERSfDEMULTIPLEXERS TTL Devices schematics of , , S N 74 LS 13 8 3 -LIME TO 8 -LINE D EC O D ER S fD EM U LTIPLEXER S recommended operating , N 74 S 13 8 A 3 LIN E TO 8 -LINE D EC O D ER S fD EM U LTIPLEXER S absolute maximum ratings over , Data Transmission Systems I I 3 Enable Inputs to Simplify Cascading and/or Data Reception â


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PDF 54S138, 64LS138
1983 - 74LS138 decoder

Abstract: pin for 74LS138
Text: converters be updated simultaneously. The interface shown in Figure 12 uses a 74LS138 decoder to decode a set , 6 Y3 11 Y4 10 A2 A1 A0 3 2 1 Y5 C B A Y6 Y7 FIGURE 12. Interfacing Multiple DAC811s to an 8 , permit interfacing to 4-, 8 -, 12-, or 16-bit buses and to handle right-or left-justified data. The 12 , SETTLING TIME(6) ( to within ±0.01% of FSR of Final Value; 2k load) For Full Scale Range Change, 20V Range 3 10V Range 3 For 1LSB Change at Major Carry(7) 1 Slew Rate(6) 8 12 ANALOG OUTPUT Voltage Range (±VCC =


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PDF DAC811 12-BIT 74LS138 decoder pin for 74LS138
74LS80

Abstract: 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
Text: Active Lo 2 to 4 Decoder , G ated O u tp u t Active 2 to 4 Decoder , G ated O u tp u t Active 3 to 8 Decoder , O u tp u t Active Hi 3 to 8 Decoder , O u tp u t Active Lo 3 to 8 Decoder , G ated O u tp u t Active 3 to 8 Decoder , G ated O u tp u t Active G ated 3 to 8 Decoder ( 74LS138 ) G ated 3 to 8 Decoder ( 74LS138 ) 4 to 10 Decoder , Output.A ctive Hi 4 to 10 Decoder , O u tp u t Active Lo 4 to 16 Decoder (74LS1S4 , * 3 to Decimal Decoder (7443) Excess- 3 Gray to Decimal Decoder (74LS44) Bed to 7 Segment Decoders


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PDF 77MLjbc 0001L3M TEK-044-9004 RSC-15 TBF368 M390C M393C CM16BR* M540C M541C 74LS80 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
pin diagram of ic 74ls138

Abstract: ic 74ls138 motorola sn74ls138 o7ad motorola 74ls138 EM 5103
Text: address decoding. The multiple input enables allow parallel expansion to a 1 -of-24 decoder using just three L S 1 3 8 devices or to a 1-of-32 decoder using four L S 1 3 8 s and one inverter. Th e L S 1 3 8 , parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder w ith just four L S 1 3 8 s and , ith all Motorola T T L fam ilies. SN54LS138 SN74LS138 1-OF- 8-DECODER / DEMULTIPLEXER LOW POWER S C , . MOTOROLA SCHOTTKY TTL DEVICES SN54LS/ 74LS138 F U N C T IO N A L D E S C R IP T IO N - T h e L S 1 3


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PDF -of-24 1-of-32 SN54LS138 SN74LS138 pin diagram of ic 74ls138 ic 74ls138 motorola sn74ls138 o7ad motorola 74ls138 EM 5103
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