The Datasheet Archive

SF Impression Pixel

Search Stock (25)

  You can filter table by choosing multiple options from dropdownShowing 25 results of 25
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
74LS113AD Rochester Electronics - - -
74LS113AN Rochester Electronics - - -
74LS113N Signetics Bristol Electronics 925 $0.75 $0.21
HD74LS113P Hitachi Ltd Bristol Electronics 1,000 $0.75 $0.21
N74LS113N Signetics High Technology Bristol Electronics 7 - -
NTE74LS113 NTE Electronics Inc Master Electronics 1 $1.16 $0.77
SN74LS113AD Rochester Electronics - - -
SN74LS113AD3 Rochester Electronics - - -
SN74LS113ADR Texas Instruments Rochester Electronics 2,500 $0.16 $0.13
SN74LS113AFN Rochester Electronics - - -
SN74LS113AFN3 Rochester Electronics - - -
SN74LS113AJ Rochester Electronics - - -
SN74LS113AJP4 Rochester Electronics - - -
SN74LS113AN Rochester Electronics - - -
SN74LS113AN Motorola Semiconductor Products Bristol Electronics 135 - -
SN74LS113AN Motorola Semiconductor Products Bristol Electronics 107 $0.94 $0.35
SN74LS113AN Texas Instruments Bristol Electronics 175 - -
SN74LS113AN Texas Instruments Bristol Electronics 325 $0.94 $0.30
SN74LS113AN Motorola Semiconductor Products Bristol Electronics 75 - -
SN74LS113AN3 Rochester Electronics - - -
SN74LS113ANP1 Rochester Electronics - - -
SN74LS113ANP3 Rochester Electronics - - -
SN74LS113N Rochester Electronics - - -
T74LS113AB1 STMicroelectronics Bristol Electronics 300 - -
UPB74LS113C NEC Electronics Group Bristol Electronics 50 $0.94 $0.61

No Results Found

74LS113 datasheet (9)

Part Manufacturer Description Type PDF
74LS113 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
74LS113 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
74LS113 Signetics Dual J-K Edge-Triggered Flip-Flop Scan PDF
74LS113 Signetics Dual J-K Edge Triggered Flip-Flop Scan PDF
74LS113 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
74LS113C Others TTL Data Book 1980 Scan PDF
74LS113DC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
74LS113FC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
74LS113PC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF

74LS113 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74LS113

Abstract: No abstract text available
Text: S ig n e tics 74LS113 , S113 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , 74LS113 74S113 TYPICAL f, AX 45MHz 125MHz TYPICAL SUPPLY CURRENT (TOTAL) 4mA 15mA ORDERING CODE , Flip-Flops 74LS113 , S113 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE Sd Asynchronous set , 5-184 Signetics Logic Products Product Specification Flip-Flops 74LS113 , S113 DC , .) 74LS113 PARAMETER T E S T C U N U I 1 lU N o 74S113 UNIT Max Min 2.7 0.5 0.4 -1.5 -1.2 1.0 Typ2 3.4


OCR Scan
PDF 74LS113, 500ns 500ns 1N916, 1N3064, 74LS113
74LS113

Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Text: Signetics 74LS113 , S113 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , ) 74LS113 45MHz 4mA 74S113 125MHz 15mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0 , Specification Flip-Flops 74LS113 , S113 LOGIC DIAGRAM FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD , Signetics Logic Products Product Specification Flip-Flops 74LS113 , S113 DC ELECTRICAL CHARACTERISTICS , CONDITIONS1 74LS113 74S113 UNIT Min Typ2 Max Min Typ2 Max Voh HIGH-level output voltage Vcc =


OCR Scan
PDF 74LS113, tr113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
74LS113

Abstract: No abstract text available
Text: Signetics 74LS113 , S113 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , state chang es are initiated by the HIGH-to-LOW transition of ÜP. TYPE 74LS113 74S113 TYPICAL fMAx , Signetics Logic Products Product Specification Flip-Flops 74LS113 , S113 LOGIC DIAGRAM , Products Product Specification Flip-Flops 74LS113 , S113 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) 74LS113 PARAMETER ESI I^IN U IIIU N


OCR Scan
PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113
74LS113

Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
Text: Signetics 74LS113 , S113 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , ) 74LS113 45MHz 4mA 74S113 125MHz 15mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; Ta = 0°C to , Flip-Flops 74LS113 , S113 LOGIC DIAGRAM FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS So CP J K Q Q , Products Product Specification Flip-Flops 74LS113 , S113 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 74LS113


OCR Scan
PDF 74LS113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
74LS113

Abstract: S113 equivalent
Text: Signetics 74LS113 , S113 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , are initiated by the HIGH-to-LOW transition of CP. TYPE 74LS113 74S113 TYPICAL fMAX 45MHz 125MHz , Logic Products Product Specification Flip-Flops 74LS113 , S113 LOGIC DIAGRAM FUNCTION , 5-184 Slgnetlcs Logic Products Product Specification Flip-Flops 74LS113 , S113 DC , .) 74LS113 PARAMETER ic s i w n u n iu in Min VOH HIGH-level output voltage Vcc » MIN, VIH - MIN, V,L - MAX


OCR Scan
PDF 74LS113, WF08450S 1N916, 1N3064, 500ns 500ns 74LS113 S113 equivalent
74LS113

Abstract: C0056
Text: Signetics 74LS113 , S113 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification , observed. Output state chang es are initiated by the H IG H -to-LO W transition of CP. TYPE 74LS113 74S113 , 853-0453 81502 Signetics Logic Products P roduct S pecification Flip-Flops 74LS113 , S113 , Logic Products Product S pecification Flip-Flops 74LS113 , S113 DC ELECTRICAL CHARACTERISTICS PARAMETER (Over recommended operating free-air temperature range unless otherwise noted.) 74LS113 Ik S I


OCR Scan
PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113 C0056
7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram 74LS112 74LS74 TTL 74107 7476 CI 7473 7473 pin diagram Jk 7476 74h106
Text: 0-3 8_ K Cd 0 D63 54S/74S113, 54LS/ 74LS113 3 — 0 -5 11 a 1-0 CP 13-0 CP 2— K 0 0—6 12 , 20 Dual JK 54LS/ 74LS113 J, K ~L X — 60 12 20 D63 3I, 6A, 9A 21 Dual JK 54/7476 J, K J L X X 20 25


OCR Scan
PDF 54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54H/74H73 54H/74H103 54S/74S113 7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 74LS74 TTL 74107 7476 CI 7473 7473 pin diagram Jk 7476 74h106
74LS183

Abstract: 74LS275 74LS97 74LS04 74LS00 74ls series 74LS356 74LS93 74LS396 74LS55
Text: CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151


OCR Scan
PDF LZ93/LZ95/LZ96/LZ97 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS183 74LS275 74LS97 74ls series 74LS356 74LS93 74LS396 74LS55
54S113

Abstract: 74S113PC 54LS113DM 74LS113PC 74LS113 74LS113FC 74LS113DC 74S113DC 74S113FC 54S113FM
Text: 74S113PC, 74LS113PC 9A Ceramic DIP (D) A 74S113DC, 74LS113DC 54S113DM, 54LS113DM 6A Flatpak (F) A 74S113FC, 74LS113FC 54S113FM, 54LS113FM 31 3 — Q -5 II Q 1 —o CP 13—0 CP 2 — K Q o— s 12 , 113 54S/74S113 // 54LS/ 74LS113 / « 7 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The'113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and


OCR Scan
PDF 54S/74S113 54LS/74LS113 54/74S 54/74LS 54/74LS 54S113 74S113PC 54LS113DM 74LS113PC 74LS113 74LS113FC 74LS113DC 74S113DC 74S113FC 54S113FM
Not Available

Abstract: No abstract text available
Text: OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V to 6 V ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS113 ORDER


OCR Scan
PDF M54HC113 M74HC113 54/74LS113 113F1R 113B1R 74HC113C1R M54/74HC113 0D54414 M54/M74HC113 005441S
54HC

Abstract: 74HC C113 M54HC113 M74HC113 74HC113
Text: Vcc (°Pr) - 2V to 6V Pin and Function compatible with 54/ 74LS113 TRUTH TABLE INPUTS OUTPUT


OCR Scan
PDF M54HC113 M74HC113. M54/74HC113 54HC 74HC C113 M54HC113 M74HC113 74HC113
TC74HC113

Abstract: No abstract text available
Text: 74LS113 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Range DC Input Voltage DC Output Voltage


OCR Scan
PDF TC74HC113P/F TC74HC113
74S113PC

Abstract: 54S113DM
Text: 0 °C to +70° C 74S113PC, 74LS113PC 74S113DC, 74LS113DC 74S113FC, 74LS113FC 54S113DM, 54LS113DM , 1 NATIONAL SEfHCOND -CLOGIO DEE D I tiSGllSE DGbBTfii T T ~ *f¿ - 0 7 -0 7 Fl3 CO N N ECTIO N DIAGRAM PINO UT A 54S /74S 113 54LS / 74LS113 D UA L JK E D G E -T R IG G E R E D FLIP-FLOP D ESC R IP TIO N - T h e '1 13offers individual J , K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be


OCR Scan
PDF /74LS113 13offers S/74LS 54/74S 54/74LS fl-07 74S113PC 54S113DM
7472 PIN DIAGRAM

Abstract: 74574 74LS112 74LS74 7473 dual JK 7472 ttl TTL 7472 7472 ci pin diagram of ttl 7476 CI 7473
Text: , 6A, 9A 19 Dual JK 54S/74S113 J, K X — 125 5.0 150 D63 3I, 6A, 9A 20 Dual JK 54LS/ 74LS113 J, K ~L


OCR Scan
PDF 19-olâ 54H/74H71 54H/74H101 54H/74H72 54H/74H102 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 54H/74H76 7472 PIN DIAGRAM 74574 74LS112 74LS74 7473 dual JK 7472 ttl TTL 7472 7472 ci pin diagram of ttl 7476 CI 7473
d146

Abstract: RS latch 74LS114 74LS78 d147 7475 D latch CI 74196 74LS112 7475 data latch 74LS113
Text: 0-3 8_ K Cd 0 D63 54S/74S113, 54LS/ 74LS113 3 — 0 -5 11 a 1-0 CP 13-0 CP 2— K 0 0—6 12


OCR Scan
PDF 54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54LS/74LS279 93L14 54LS/74LS196 d146 RS latch 74LS114 74LS78 d147 7475 D latch CI 74196 74LS112 7475 data latch 74LS113
TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Text: JK 54S/74S113 J, K X — 125 5.0 150 D63 3I, 6A, 9A 20 Dual JK 54LS/ 74LS113 J, K ~L X — 60 12 20


OCR Scan
PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
JK flip flop IC

Abstract: J-K Flip flops 4000B 74LS113 M74HC113 M74HC113P "J-K Flip flops"
Text: series while giving high-speed performance equivalent to the 74LS113. The M74HC113 contains two


OCR Scan
PDF M74HC113P M74HC113 50MHz 10/zW/package JK flip flop IC J-K Flip flops 4000B 74LS113 M74HC113P "J-K Flip flops"
FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Text: 7496 74LS96 74104 74LS104 74107 74LS107 74HC107 74LS109 74LS112 74HC112 74LS113 74121 74LS122 , 74LS113 74LS122 74LS123 74LS125 74LS126 74LS13 74LS132 74LS138 74LS139 74LS14 74LS148 74LS151


Original
PDF 74INTEGRATED Line-to-10 150ns 16-DIL 150ns 18-pin 250ns 300ns FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
74S113D

Abstract: 74LS113D
Text: 113 C O N N E C T IO N DIAGRAM P IN O U T A * 548/748113 54LS/ 74LS113 ö / / « 7 DUAL JK EDGE-TRIGGERED FLIP-FLOP D ESCRIPTION - T h e ' 113 o ffe rs in d iv id u a l J, K, Set an d C lo c k inputs. W hen the c lo c k g o e s H IG H the in p u ts are e n a b le d and data m ay be entered. T h e lo , P C 74S113D C, 74LS113D C 54 S 1 1 3 D M , 5 4 L S 1 1 3 D M MILITARY G R AD E V c c = +5.0 V ±10% , G N D = P in 7 A 6A A 74S113FC, 74LS113FC 5 4 S 1 1 3 FM , 5 4 L S 1 1 3 F M 3I


OCR Scan
PDF 54LS/74LS113 54/74LS 54/74S 74S113D 74LS113D
74HC113

Abstract: M54HC113 M54HC113F1R M74HC113 M74HC113B1R M74HC113C1R M74HC113M1R
Text: M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS113 B1R (Plastic Package) F1R


Original
PDF M54HC113 M74HC113 54/74LS113 M54HC113F1R M74HC113M1R M74HC113B1R M74HC113C1R M54/74HC113 74HC113 M54HC113 M54HC113F1R M74HC113 M74HC113B1R M74HC113C1R M74HC113M1R
Not Available

Abstract: No abstract text available
Text: €¢ Pin and Function C om patible with 74LS113 1CK 1 [ ] 1« v cc ] 13 2CK IK 2 [ 1J î [ J


OCR Scan
PDF TC74HC113AP/AF TC74HC113A 71MHz TC74HC113AP/AF-4
74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Text: 74LS97 74LS99 74LS107 74LS107A 74LS109 74LS109A 74LS112 74LS112A 74LS113 74LS113A 74LS114 74LS114A


OCR Scan
PDF
Not Available

Abstract: No abstract text available
Text: OPERATING VOLTAGE RANGE Vcc (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS113 DESCRIPTION The


OCR Scan
PDF 113F1R 113B1R 113C1R 54/74LS113 M54/74HC113 FLIP190 M54/M74HC113
or gate thruth table

Abstract: No abstract text available
Text: Carrier WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 to 6V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS113


OCR Scan
PDF M54HC113 M74HC113 54/74LS113 M74HC113 M74HC113B1N 54/7AHC113 or gate thruth table
74hc113

Abstract: 74HCT113 GD74HCT11 74HC 74LS113 GD54HC113 GD74HC113
Text: GD54/74HC113, GD54/74HCT113 DUAL J-K FLIP-FLOPS WITH PRESET General Description These devices are identical in pinout to the 54/ 74LS113. They consist of two J-K flip-flops with individual J, K, Clock, and Preset inputs. These flip-flops are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Both Q and Q outputs are available from each flip-flop. Preset is independent of the Clock and accomplished by a Low level on the input. These devices are


OCR Scan
PDF GD54/74HC113, GD54/74HCT113 54/74LS113. 74hc113 74HCT113 GD74HCT11 74HC 74LS113 GD54HC113 GD74HC113
Supplyframe Tracking Pixel