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Part Manufacturer Description Datasheet Download Buy Part
SN74LS107ANSR Texas Instruments Dual J-K Flip-Flops With Clear 14-SO 0 to 70
SN74LS107AD Texas Instruments Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70
SN74LS107ANSRE4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14
SN74LS107ADE4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOIC-14
SN74LS107ANSRG4 Texas Instruments LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14
SN74LS107ADG4 Texas Instruments Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70
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Search Stock (29)

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Part Manufacturer Supplier Stock Best Price Price Each Buy Part
74LS107A NTE Electronics Inc Master Electronics 80 $2.12 $1.87
74LS107AD Rochester Electronics - - -
74LS107AFPEL-E Renesas Electronics Corporation Rochester Electronics 4,000 $0.31 $0.25
74LS107ALYDP Chip One Exchange 1,000 - -
74LS107AN Rochester Electronics - - -
74LS107N NXP Semiconductors Bristol Electronics 12 - -
CD74LS107AD Texas Instruments Bristol Electronics 50 - -
DM74LS107AN National Semiconductor Corporation Chip One Exchange 103 - -
DM74LS107AN National Semiconductor Corporation Bristol Electronics 15 - -
HD74LS107P Renesas Electronics Corporation Chip1Stop 4 $4.41 $4.41
N74LS107N NXP Semiconductors Bristol Electronics 12 - -
NTE74LS107 NTE Electronics Inc Newark element14 320 $3.95 $3.31
SN74LS107AD Texas Instruments Avnet - - -
SN74LS107AD Texas Instruments Rochester Electronics 12,482 $1.36 $1.10
SN74LS107AD ON Semiconductor Rochester Electronics 3,140 $0.13 $0.10
SN74LS107ADBR Texas Instruments Rochester Electronics 2,000 $0.49 $0.40
SN74LS107ADR Texas Instruments Rochester Electronics 2,253 $1.56 $1.27
SN74LS107ADR Texas Instruments Avnet - - -
SN74LS107AN Texas Instruments Bristol Electronics 136 - -
SN74LS107AN Texas Instruments Rochester Electronics 14,587 $1.23 $1.00
SN74LS107AN Texas Instruments Newark element14 110 $1.99 $0.88
SN74LS107AN Texas Instruments Avnet - - -
SN74LS107AN Texas Instruments Chip1Stop 50 $3.95 $1.65
SN74LS107AN Texas Instruments Farnell element14 357 £1.28 £0.96
SN74LS107AN Texas Instruments Chip1Stop 142 $1.27 $1.10
SN74LS107AN Texas Instruments element14 Asia-Pacific 4 $2.44 $1.04
SN74LS107ANS Texas Instruments Rochester Electronics 6,168 $1.52 $1.24
SN74LS107ANSR Texas Instruments Rochester Electronics 30,000 $1.23 $1.00
SN74LS107ANSR Texas Instruments Avnet - - -

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74LS107 datasheet (9)

Part Manufacturer Description Type PDF
74LS107 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
74LS107 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
74LS107 Signetics Dual J-K Flip-Flop Scan PDF
74LS107 Signetics Dual J-K Flip-Flop Scan PDF
74LS107 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
74LS107DC Fairchild Semiconductor Dual J-K Flip-Flop Scan PDF
74LS107FC Fairchild Semiconductor Dual J-K Flip-Flop Scan PDF
74LS107M Others TTL Data Book 1980 Scan PDF
74LS107PC Fairchild Semiconductor Dual J-K Flip-Flop Scan PDF

74LS107 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
pin configuration 74LS107

Abstract: 74LS107 LS107 LS-107 74107 AN ttl 74107 74107 pin configuration N74107
Text: stable while the Clock is HIGH for conventional oper ation. The 74LS107 is a negative edge-trig gered , output LOW and HIGH. asynchronous LOW, it over inputs, forcing the <3 output TYPE 74107 74LS107 TYPICAL , inputs of the 74107 must be stable while the Clock is HIG H for conventional operation. The 74LS107 is , all outputs open, Ice is measured with the O and (5 outputs HIGH in turn. 74LS107 UNIT Max Min 2.7


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PDF LS107 74LS107 1N916, 1N3064, 500ns 500ns pin configuration 74LS107 LS107 LS-107 74107 AN ttl 74107 74107 pin configuration N74107
CI 7474

Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
Text: o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 •54/74107, *54LS/ 74LS107 14 — J 0 -12 I- J , /74LS76 J,K "L X X 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/ 74LS107 J,K "L — X 60 12 20 D57a 3I,6A,9A 8


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PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
74107 pin diagram

Abstract: CI 74107 74ls107 pin configuration 74LS107 TTL 74107 2RD22 74107 LS107 74LS 1N916
Text: stable while the Clock is HIGH for conventional operation. The 74LS107 is a negative edge-triggered , CURRENT (TOTAL) 74107 20MHz 20mA 74LS107 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5 , must be stable while the Clock is HIGH for conventional operation. 2. The 74LS107 is edge-triggered , 0.2 Max 74LS107 Min 0.4 -1.5 1.0 -18 40 80 80 2.7 Typ2 Max UNIT 3.4 0.35 0.25 -1.6


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PDF LS107 74LS107 1N916, 1N3064, 500ns 74107 pin diagram CI 74107 pin configuration 74LS107 TTL 74107 2RD22 74107 LS107 74LS 1N916
74107 pin diagram

Abstract: 74107 74LS107 74107 flip flop pin configuration 74LS107 H/CI 74107 N74LS107D N74107N 74LS 1N916
Text: operation. The 74LS107 Is a negative edge-triggered flip-flop. The J and K inputs must be stable one set-up , . The 74LS107 is edge-triggered. Data must be stable one set-up time prior to the negative edge of the , operating free-air temperature range unless otherwise noted.) PARAMETER TEST CONDITIONS1 74107 74LS107


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PDF 74LS107 1N916, 1N3064, 500ns 74107 pin diagram 74107 74107 flip flop pin configuration 74LS107 H/CI 74107 N74LS107D N74107N 74LS 1N916
IC 74107

Abstract: IC 74LS107 74LS107 LS107
Text: over inputs, forcing the Q output NOTE: TYPE 74107 74LS107 TYPICAL f MAX 20MHz 45MHz TYPICAL , stable while the Clock is HIGH for conventional operation. The 74LS107 is edge-triggered. Data must be , ma 74LS107 UNIT V qh HIGH-level output voltage Vcc = MIN, V|H = MIN, V|L = MAX, Ioh = MAX


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PDF LS107 1N916, 1N3064, 500ns 500ns IC 74107 IC 74LS107 74LS107 LS107
logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram 74LS107 ic 74109 74109 dual JK IC 74196 7476 Connection diagram 74LS109 jk 7474 7474 D latch
Text: /74109 54LS/74LS114 54LS/ 74LS107 c_ >; r 1 54S/74S114 DEVICE NO. c_ c_ c_ c , 54/7473, 54H/74H73, 54LS/74LS73 *54/74107, ` 54LS/ 74LS107 14 - J 1 - 0 CP 3- K Q -1 2 2- J 5 -0 CP


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PDF 54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279 54H/74H73, 54LS/74LS73 54LS/74LS107 logic ic 7476 pin diagram logic ic 74LS76 pin diagram 74LS107 ic 74109 74109 dual JK IC 74196 7476 Connection diagram 74LS109 jk 7474 7474 D latch
74LS183

Abstract: 74LS275 74LS97 74LS04 74LS00 74ls series 74LS356 74LS93 74LS396 74LS55
Text: CM O S/BiCM O S Gate Array LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries (LZ93/LZ95/LZ96/LZ97 Series) Model No. 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS27 74LS28 74LS30 74LS32 74LS37 74LS40 74LS42 7443 7444 74LS48 Model No. 74LS51 74LS54 74LS55 74LS73 74LS74 74LS75 74LS76 7447 74LS78 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 74LS97 Model No. 74LS107 74LS109 74LS112 74LS113 74LS114 74LS125 74LS126 74LS137 74LS138 74LS139 74LS147 74LS148 74LS151


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PDF LZ93/LZ95/LZ96/LZ97 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS183 74LS275 74LS97 74ls series 74LS356 74LS93 74LS396 74LS55
TTL 74ls74

Abstract: 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS73 74LS107 74ls74 TTL 74ls76 74LS109
Text: o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 •54/74107, *54LS/ 74LS107 14 — J 0 -12 I- J


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PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54L15 TTL 74ls74 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS73 74LS107 74ls74 TTL 74ls76 74LS109
74LS107

Abstract: No abstract text available
Text: pin-out com patible w ith LS · TTL ( 74LS107 ) and uses silicon gate process technology to achieve operating speeds and drivability sim ilar to LS · TTL ( 74LS107 ). · All inputs are protected from dam age. A b s o


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PDF MLC74HC107 MLC74HC107 74LS107) 74LS107
7475 D latch

Abstract: D146 D147 ci 7475 74LS109 rs latch 74LS78 74LS107 7475 data latch 74LS114
Text: 60 12 20 D58 4L,6B,9B 7 Dual JK 54LS/ 74LS107 J,K "L — X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS


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PDF 54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS279 93L14 7475 D latch D146 D147 ci 7475 74LS109 rs latch 74LS78 74LS107 7475 data latch 74LS114
IC 74LS107

Abstract: 74LS107 DIP14-P-300-2 TC74HC107AF TC74HC107AP
Text: TC74HC107AP/AF CMOS TC74HC107AP,TC74HC107AF Dual J-K Flip-Flop with Clear TC74HC107A CMOS CMOS JK CMOS LSTTL J K "L" · TC74HC107AP : fmax = 75 MHz () (VCC = 5 V) · : ICC = 2 A () (Ta = 25°C) · : VNIH = VNIL = 28% VCC () · : LSTTL 10 · TC74HC107AF · : |IOH| = IOL = 4 mA () : tpLH - tpHL · · LSTTL ( 74LS107 ) : VCC (opr) = 2~6 V DIP14-P-300-2.54 : 0.96 g () SOP14-P-300-1.27A : 0.18


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PDF TC74HC107AP/AF TC74HC107AP TC74HC107AF TC74HC107A TC74HC107AP 74LS107) DIP14-P-300-2 OP14-P-300-1 IC 74LS107 74LS107 TC74HC107AF
IC 74107

Abstract: H/IC 74107 LS-107 LS107 pin configuration 74LS107
Text: e r inp u ts, fo rcin g th e O o u tp u t NOTE: TYPE 74107 74LS107 TYPICAL fMAX 20MHz 45MHz , -3 .2 -1 8 -5 7 40 re c o m m e n d e d o p e ra tin g c o n d itio n s fo r th e 74LS107 UNIT


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PDF LS107 500ns 500ns IC 74107 H/IC 74107 LS-107 LS107 pin configuration 74LS107
d146

Abstract: RS latch 74LS114 74LS78 d147 7475 D latch CI 74196 74LS112 7475 data latch 74LS113
Text: Dual JK 54LS/ 74LS107 J,K "L — X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S X X 45 16 20 D82


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PDF 54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54LS/74LS279 93L14 54LS/74LS196 d146 RS latch 74LS114 74LS78 d147 7475 D latch CI 74196 74LS112 7475 data latch 74LS113
74107PC

Abstract: 74ls107 74LS107DC 74107 pin diagram 54LS107DM 54107FM 74107DC 74107FC cpn0 74LS107FC
Text: = +5.0 V ±5%, Ta = 0°C to +125°C 74107PC, 74LS107PC 74107DC, 74LS107DC 74107FC, 74LS107FC , 107 54/74107 '54LS/ 74LS107 e> DUAL JK FLIP-FLOP (With Separate Clears and Clocks) DESCRIPTION—The '107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows


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PDF 54LS/74LS107 54/74LS CLS107) 74107PC 74ls107 74LS107DC 74107 pin diagram 54LS107DM 54107FM 74107DC 74107FC cpn0 74LS107FC
74LS107n

Abstract: 74107PC IC 74LS107
Text: = 0 °C to +125°C 74107PC, 74LS107PC 74107DC, 74LS107DC 74107FC, 74LS107FC 54107DM, 54LS107DM 54107FM , 107 54/74107 O ' 54LS/ 74LS107^ n o r D UAL JK FLIP-FLO P (With Separate Clears and Clocks) DESCRIPTION - T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the clo ck pulse. The clo ck pulse also regulates the state of the co upling transi stors w hich connect the master and slave sections. The sequence of opera tion is


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PDF 54LS/74LS107^ 54/74LS CLS107) 74LS107n 74107PC IC 74LS107
ci 7475

Abstract: D147 74LS109 74L576 TTL 7475 74LS78 rs latch fairchild 9314 pin diagram 7475 74LS279
Text: D58 4L,6B,9B 7 Dual JK 54LS/ 74LS107 J,K "L — X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S


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PDF 93L14 54LS/74LS279 54LS/74LS75 93L08, 54LS/74LS77 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 54LS/74LS75 ci 7475 D147 74LS109 74L576 TTL 7475 74LS78 rs latch fairchild 9314 pin diagram 7475 74LS279
TTL 74ls74

Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
Text: o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 •54/74107, *54LS/ 74LS107 14 — J 0 -12 I- J


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PDF 54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
CI 74LS90

Abstract: ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 74LS93 TTL 74293 TTL 7493A sn 7492 ttl
Text: D58 4L,6B,9B 7 Dual JK 54LS/ 74LS107 J,K "L — X 60 12 20 D57a 3I,6A,9A 8 Dual JK 54LS/74LS78 J.K S


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PDF 54/7490A, 54LS/74LS90 74LS92 S4/74293, 54LS/74LS293 S4/7493A, 54LS/74LS93 93L10, 93S10, 93L16, CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 74LS93 TTL 74293 TTL 7493A sn 7492 ttl
IC 7408

Abstract: IC 7812 REGULATOR IC 7812 IC TTL 7400 NEC d446c d446c data sheet IC 7408 ic 74151 IC 74153 REGULATOR IC 7912
Text: 74S38 1820-1453 STTL IC 74S163 1820-1469 LSTTL IC 74LS107 1820-1470 LSTTL IC


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PDF HP1350 82S126 1818-0373B MK34127N D446C-2 NEC/AMNE592 IC 7408 IC 7812 REGULATOR IC 7812 IC TTL 7400 NEC d446c d446c data sheet IC 7408 ic 74151 IC 74153 REGULATOR IC 7912
of 74HC107 ic

Abstract: 74hc107 IC 74LS107 j-k flip flop clock toggle 54HC M74HC107B1N M74HC107 M54HC107 74HC M74HC107B1
Text: I T/ SGS-mOMSON RÄlD(g[S®IIL[i(gTns®R!lD(gi M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR i HIGH SPEED 'max = 58 MHz (TYP.) at VCc= 5V i LOW POWER DISSIPATION Ice = 2 iiA (MAX.) at TA = 25°C i HIGH NOISE IMMUNITY Vnih = VN|L = 28% Vcc (MIN.) i OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS i SYMMETRICAL OUTPUT IMPEDANCE I'OHi = lOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tpHL WIDE OPERATING VOLTAGE RANGE Vcc (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS107 DESCRIPTION The M54


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PDF M54HC107 M74HC107 54/74LS107 M54/74HC107 M54/74HC107 of 74HC107 ic 74hc107 IC 74LS107 j-k flip flop clock toggle 54HC M74HC107B1N M74HC107 74HC M74HC107B1
IC 74LS107

Abstract: 74LS107 "pin compatible"
Text: Operating Voltage Range: Vcc(opr) = 2V · 6V Pin and Function Compatible with 74LS107 1J IQ IQ IK 2Q 20 GND


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PDF TC74HC107AP/AF/AFN TC74HC107A 75MHz TC74HC/HCT IC 74LS107 74LS107 "pin compatible"
IC 74LS107

Abstract: 54HC 74HC M54HC107 M74HC107 M74HC 74LS107 74LS107 "pin compatible"
Text: Voltage Range VCc (oPr) = 2V to 6V • Pin and Function compatible with 54/ 74LS107 TRUHT TABLE INPUTS


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PDF M54/74HC107 IC 74LS107 54HC 74HC M54HC107 M74HC107 M74HC 74LS107 74LS107 "pin compatible"
74LS107* pin and application

Abstract: No abstract text available
Text: CLR* Q * 74LS107 Q K • MISSING CODE +5V (0)AB (0)A=B 1M J & > K 7-20 CLR* -W 74LS107 1M Q A V - VIN OF BT208


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PDF Bt208 24-pin 28-pin Bt208 74F269 74LS85 BT206 74LS107 74LS107* pin and application
HC224

Abstract: HC-225 HC-224
Text: Range ··· V 74LS107 TRUTH TABLE INPUTS J K CLR L X


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PDF TC74HC107AP/AF/AFN TC74HC107A 75MHi HC-224 HC-225 HC224 HC-225 HC-224
TC74HC107P

Abstract: TC74HC107
Text: Wide Operating Voltage Range . Pin and Function Compatible with 74LS107 tpLFHtpHL (Opr.)= 2


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PDF TC74HC107P/F TC74HC107P TC74HC107F TC74HC107 TC74HC107P/F
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