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Part Manufacturer Description Datasheet Download Buy Part
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938HMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939IMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC2938HDE#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

74LS00 pin configuration Datasheets Context Search

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74LS00 pin configuration

Abstract: gd74ls04 74LS00 function table 74LS00 pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD74LSOO 74LS00 clock frequency pin configuration 74LS04
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates, jt^ performs the Boolean functions Y = A B or Y=A+B in positive logic. Function Table (each gate) INPUTS OUTPUT A B Y H H L L X H X L H Pin Configuration Vcc 4B 4 A 4 Y 3B , to 150°C 4-3 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS00 Recommended , 4-4 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS00 Application Example


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PDF GD54/74LS00 GD74LSOO GD74LS04 74LS04 74LS00 pin configuration gd74ls04 74LS00 function table 74LS00 pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD74LSOO 74LS00 clock frequency pin configuration 74LS04
74LS00 clock frequency

Abstract: 74LS00 function table pin configuration 74LS00
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. K performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 4B 4A 4Y 3B 3A 14 13 12 11 10 9 3Y 8 , . - 6 5 ° C to 1 5 0 ° C 4-3 GD54/ 74LS00 Recommended Operating Conditions SYMBOL MIN , -1 1 . 4-4 GD54/ 74LS00 Application Example Crystal Clock Generator (1) G D74LS00 c


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PDF GD54/74LS00 D74LS00 D74LS04 74LS00 clock frequency 74LS00 function table pin configuration 74LS00
IC 74LS00

Abstract: 74LS00 74LS00 pin configuration 74LS00 function table pin configuration 74LS00 74LS00 clock frequency NAND 74LS00 74LS00 Electrical and Switching characteristics 74LS00 application 74ls00 NAND gate
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 14 4B 13 4A 12 4Y 11 3B 10 3A 9 3Y 8 Function Table (each gate) INPUTS A H , . - 6 5 CC to 1 5 0 ° C 2-45 40HÖ7S7 OOGHnO fib4 GD54/ 74LS00 Recommended Operating , GD54/ 74LS00 Application Example Crystal Clock Generator (1) G D 7 4 L S 0 0 c, Frequency (MHz) 1


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PDF GD54/74LS00 402B757 IC 74LS00 74LS00 74LS00 pin configuration 74LS00 function table pin configuration 74LS00 74LS00 clock frequency NAND 74LS00 74LS00 Electrical and Switching characteristics 74LS00 application 74ls00 NAND gate
1998 - pin diagram of 74ls00

Abstract: 74LS00 74ls00 datasheet 74HC74 motorola 74LS00 memory card circuit diagram 74HC74 decoder inverter wait 74LS00 impedance 74LS00 application
Text: B B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 , only one chip select used. TITLE AUTHOR COMPANY DATE REVISION PATTERN CHIP ; PIN ; PIN


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PDF 74HC04 0xfff44b 0xfff449 0xfff448 0xfff443 0xfff441 0xfff440 pin diagram of 74ls00 74LS00 74ls00 datasheet 74HC74 motorola 74LS00 memory card circuit diagram 74HC74 decoder inverter wait 74LS00 impedance 74LS00 application
ls 7400

Abstract: 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
Text: -0.4mA l|L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) _1 2 & v. 3 _4 _S ^ 6 10 _9 , Signetìcs I 7400, LSOO, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA 74SOO 3ns 15mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0°C to + 70°C Plastic , .) PARAMETER TEST CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max


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PDF 74LS00 74SOO N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul WF07570S ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
7400 signetics

Abstract: 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
Text: Signetics I 7400, LS00, SOO Gates Logic Products Quad Two-Input NAND Gate Product Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , load (Sul) Is 50^A l|H and -2.0mA l|L, and 74LS unit load (LSul) is 20/iA l|H and -0.4mA l,L. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 1 2 & ^ 3 _« _5 10 IT 12 ^ 11 13 , CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul 7400 signetics 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
74LS00 function table

Abstract: ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
Text: 1Sul 10Sul 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC , Signelics | 7400, LS00, S00 Gates Quad Two-Input NAND Gate Product Specification Logic Products TYPE 7400 74LS00 74S00 TYPICAL PROPAGATION DELAY 9ns 9.5ns 3ns TYPICAL SUPPLY CURRENT (TOTAL) 8mA 1.6mA 15mA ORDERING CODE PACKAGES Plastic DIP Plastic SO COMMERCIAL RANGE VCC = 5 V ± 5 % , 74LS00 Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max Min 2.7 74S00 UNIT Min Typ2 3.4 0.2


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74SOOD 74LS00 function table ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
pin diagram of 74ls00

Abstract: 74HC04 74HC74 74LS00 74HC74 decoder motorola 74LS00 74LS00 application 74LS00 impedance 74ls00 circuit diagram inverter wait
Text: 74HC04 U2A 2 B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 , AUTHOR COMPANY DATE REVISION PATTERN CHIP ; PIN ; PIN PCMCIA VER 2.01 DECODER JACKY LI


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PDF Informatfff448 0xfff443 0xfff441 0xfff440 0xfff44b 0xfff449 0xfff448 pin diagram of 74ls00 74HC04 74HC74 74LS00 74HC74 decoder motorola 74LS00 74LS00 application 74LS00 impedance 74ls00 circuit diagram inverter wait
74LS00

Abstract: motorola 74LS00 datasheet of ic 74ls00 74LS00 impedance pin diagram of ic 74ls00 pin diagram of 74ls00 74ls00 circuit diagram 74HC74 decoder 74HC74 inverter wait
Text: Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 Q , CHIP ; PIN ; PIN PCMCIA VER 2.01 DECODER JACKY LI MOTOROLA INC. 23/11/98 1 CLK U1


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PDF 0fff448 0xfff443 0xfff441 0xfff440 0xfff44b 0xfff449 0xfff448 74LS00 motorola 74LS00 datasheet of ic 74ls00 74LS00 impedance pin diagram of ic 74ls00 pin diagram of 74ls00 74ls00 circuit diagram 74HC74 decoder 74HC74 inverter wait
datasheet of ic 74ls00

Abstract: pin diagram of ic 74ls00 pin diagram of 74ls00 motorola 74LS00 74LS00 74HC74 74HC74 decoder 74LS00 impedance 74LS00 application 74HC74 application
Text: Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 Q , COMPANY DATE REVISION PATTERN CHIP ; PIN ; PIN PCMCIA VER 2.01 DECODER JACKY LI MOTOROLA INC


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PDF 0xfff44b 0xfff449 0xfff448 0xfff443 0xfff441 0xfff440 datasheet of ic 74ls00 pin diagram of ic 74ls00 pin diagram of 74ls00 motorola 74LS00 74LS00 74HC74 74HC74 decoder 74LS00 impedance 74LS00 application 74HC74 application
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA HCTL1100
Text: AD1 AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW , 74LS00 13 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 6 74LS00 A8 A9 A10 PHA PHB PHC


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL1100 HCTL1100. HCTL-1100s 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA
2007 - 3 to 8 line decoder using 8051

Abstract: 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET HCTL-1100 74LS138 HCTL-1100 M-015 HCTL-1100s
Text: AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 Y3 , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW SIGNAL , 39 38 38 34 1 A 2 B 3 C 11 MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 3 74LS00 13 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 6 74LS00 A8 A9 A10 PHA PHB PHC PHD


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL-1100. WR1100: CS1100 3 to 8 line decoder using 8051 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET 74LS138 HCTL-1100 M-015 HCTL-1100s
1995 - 74LS688

Abstract: s1d13502 isa bus 74LS00 DATA AB-019
Text: Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.1 Configuration Options . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.1 Configuration Options . . . . . . . . , Configuration Options) 2. 128Kbytes of display memory occupying $C and $D segments (see Configuration Options) Note This memory configuration will conflict with a VGA card installed on the same bus , the IOCS16# and MEMCS16# signals. 1.4 S1D13502 Default Setup 1.4.1 Configuration Options 1


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PDF S5U13502 X16-AN-003-06 1100000000b 1100000001b MC68K 16-bit S1D13502 74LS688 s1d13502 isa bus 74LS00 DATA AB-019
1999 - schematic diagram brushless motor control

Abstract: schematic diagram Permanent Magnet brushless DC m permanent magnet synchronous machine ST52X301 schematic diagram Permanent Magnet brushless DC Speed Control Of DC Motor Using Fuzzy Logic code jps inverter stepping motor japan servo brushless motor control inverter schematic diagram speed control of dc motor using fuzzy logic controller
Text: 5 9 10 74LS00 74LS00 74LS00 IN2 IN3 8 3 6 8 IN1 IN2 IN3 , application. SOFTWARE DESCRIPTION Before to discuss about ST52x301 software configuration , it is important to note some HW connections in the schematic. Bit "0" ( pin 9) of the parallel port is used to enable , analog input AIN0 ( pin 43) is used to read the voltage reference. A voltage between 0 + 2.5 V present on this pin , is converted in the range 0 + 255. External INTerrupt pin (27) is used to read one Hall


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PDF AN1113 ST52x301 schematic diagram brushless motor control schematic diagram Permanent Magnet brushless DC m permanent magnet synchronous machine ST52X301 schematic diagram Permanent Magnet brushless DC Speed Control Of DC Motor Using Fuzzy Logic code jps inverter stepping motor japan servo brushless motor control inverter schematic diagram speed control of dc motor using fuzzy logic controller
1996 - 74l500

Abstract: 74LS00 UF 407 Diode 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 datasheet of ic 74ls00 LOGIC OF 74L500 diode u1d ON u1d diode
Text: 1 R1 10 IN1 L6203 1 IN2 3.6 A MOTOR 3 8 1 12 U1B 74LS00 9 U1C 74LS00 6 GND U1D 74L500 C2 22 nF 2 1 U1A 74LS00 2 4 1 2 7 FROM


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PDF HCTL-1100 M-024 DAC08 REF-01 74l500 74LS00 UF 407 Diode 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 datasheet of ic 74ls00 LOGIC OF 74L500 diode u1d ON u1d diode
TTL 74HC00

Abstract: 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
Text: €¢ High noise immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration 1A [T , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for opération over Wide temperature ranges to meet in-dustry and military spécifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
74LS00 pinout

Abstract: TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
Text: €¢ High noise immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration 1A , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74LS00 pinout TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74LS00 74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 74LS00 DATA
Text: SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC , Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74LS00 74LS00 TTL TTL 74LS00 74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 74LS00 DATA
74LS00 TTL

Abstract: TTL 74LS00 74LS00 74ls00 NAND gate 74LS00 DATA 74LS00 QUAD 2-INPUT NAND GATE 74LS00 truth table NAND 74LS00 74LS00DC 74ls00 tphl tplh
Text: SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC , Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74IOL 74LS00 TTL TTL 74LS00 74LS00 74ls00 NAND gate 74LS00 DATA 74LS00 QUAD 2-INPUT NAND GATE 74LS00 truth table NAND 74LS00 74LS00DC 74ls00 tphl tplh
2007 - of ic 74ls00

Abstract: 74l500 74LS00 datasheet of ic 74ls00 motorola byw 21 bridge rectifier 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 diode u1d ON UF 407 Diode
Text: 3.6 A MOTOR 2 7 L6203 1 IN2 3 8 1 2 12 U1B 74LS00 4 2 1 U1A 74LS00 1 FROM HCTL-1100 D1 DIODE BYW 98 C3 15 nF 2 9 U1C 74LS00 6 GND U1D


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PDF HCTL-1100 M-024 REF-01 5964-9816E 5965-3476E of ic 74ls00 74l500 74LS00 datasheet of ic 74ls00 motorola byw 21 bridge rectifier 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 diode u1d ON UF 407 Diode
74LS00 TTL

Abstract: 74LS00 truth table IC TTL 74LS00 74LS00 74LS00 QUAD 2-INPUT NAND GATE TTL 74ls00 74LS00DC motorola 74LS00 74ls00 NAND gate 74LS00 gate
Text: MOTOROLA SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE fn l [ïïl fïïl [Til fïïl ITI 171 J SUFFIX CERAMIC CASE 632-08 VCC LOW POWER SCHOTTKY Lü Ll I Ll I L±l Ll I Ll I LzJ GND N SUFFIX ,r p îïï , 'S :. D SUFFIX SOIC CASE 751A-02 5 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES , Output Current - High Output Current - Low mA mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD SN54/74LS00 74LS00 TTL 74LS00 truth table IC TTL 74LS00 74LS00 74LS00 QUAD 2-INPUT NAND GATE TTL 74ls00 74LS00DC motorola 74LS00 74ls00 NAND gate 74LS00 gate
74HCoo

Abstract: TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74LS00 gate diagram logic symbol 74LS00 74hc00 and gates 74HC00 pin configuration logic symbol 74LS00 GD74HC00
Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features , . (74HC) • High noise immunity characteristic of CMOS • Diode protection on all inputs Pin Configuration 1A EE u 23 vcc 1B Dl 13 4B 1Y IZ HI 4 A 2 A Cl 00 4Y 2B (Z 3B 2 Y [I 3A GMD [I


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74HCoo TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74LS00 gate diagram logic symbol 74LS00 74hc00 and gates 74HC00 pin configuration logic symbol 74LS00 GD74HC00
TTL 74ls00

Abstract: 74LS00 74LS00 TTL motorola 74LS00 74LS00 truth table NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 DATA 74ls00 NAND gate 74LS00DC
Text: (g) MOTOROLA QUAD 2-INPUT NAND GATE • ESD > 3500 Volts vcc nn [ïïi ra m ra m m LlI LLI LLI LLI LiJ LLI LLI gnd SN54/ 74LS00 QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES f0 1 J SUFFIX CERAMIC CASE 632-08 Jfllffi 1 N SUFFIX PLASTIC CASE 646-06 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC Symbol Parameter Min , Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC CHARACTERISTICS OVER


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD TTL 74ls00 74LS00 74LS00 TTL motorola 74LS00 74LS00 truth table NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 DATA 74ls00 NAND gate 74LS00DC
7404 TTL CMOS

Abstract: TTL 74h04 TTL 7400 fairchild 7404 ttl inverter CI 74LS00 TTL 7404 fairchild 9016 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/ 74LS00 , 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , > 111 Q 2 o o c 3 u. Companion Receiver Input Compatibility Type Output Output Configuration c £ -* P , 54LS/74LS14 54/74114 — — D1 3I,6A,9A 6 Quad 2-lnput 9002 54LS/ 74LS00 54/7400 54H/74H00 54S/74S00


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PDF 54H/74H04, 54S/74S04, 54LS/74LS04, 9S05A, 54H/74H05, 54S/74S05, 54L8/74LS05, 54LS/74LS14, 54H/74H00, 54S/74S00, 7404 TTL CMOS TTL 74h04 TTL 7400 fairchild 7404 ttl inverter CI 74LS00 TTL 7404 fairchild 9016 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
t74ls157

Abstract: 74LS00E 74LS00 fan out T74LS74 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate 74ls00 series T74LS367 NAND 74LS00
Text: LOW POWER SCHOTTKY TTL-54/74 LS SERIES DESIGN CONSIDERATIONS SUPPLY VOLTAGE — +5V ± 10% T54 SERIES +5V ±5% T74 SERIES NOISE MARGIN — VIL 0.7V, VIH 2.0V, VOL 0.4V, VOH 2.5V T54 SERIES Vil 0.8V, VIH 2.0V, Vol 0.5V, VOH 2.7V T74 SERIES INPUT LOADING — THE 74LS00 INPUT LOADING IS Iil 0.36mA (LOW INPUT) AND I IH 20MA (HIGH INPUT) OUTPUT DRIVE — THE 74LS00 OUTPUT DRIVE IS Iol 8.0mA (SINK) AND I oh , DEVICES WITHIN THE FAMILY AND IS NORMALIZED AROUND THE INPUT REQUIREMENTS OF THE 74LS00 .E.G. THE 74LS00


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PDF TTL-54/74 74LS00 400/u 400mA SO-14. t74ls157 74LS00E 74LS00 fan out T74LS74 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate 74ls00 series T74LS367 NAND 74LS00
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