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Part Manufacturer Description Datasheet Download Buy Part
LT3466EDD#TR Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3466EDD#PBF Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3466EDD Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3466EDD#TRPBF Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3497EDDB#TRPBF Linear Technology LT3497 - Dual Full Function White LED Driver with Integrated Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3497EDDB#PBF Linear Technology LT3497 - Dual Full Function White LED Driver with Integrated Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C

74LS00 function table Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74LS00 pin configuration

Abstract: gd74ls04 74LS00 function table 74LS00 pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD74LSOO 74LS00 clock frequency pin configuration 74LS04
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates, jt^ performs the Boolean functions Y = A B or Y=A+B in positive logic. Function Table (each gate) INPUTS OUTPUT A B Y H H L L X H X L H Pin Configuration Vcc 4B 4 A 4 Y 3B , to 150°C 4-3 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS00 Recommended , 4-4 This Material Copyrighted By Its Respective Manufacturer GD54/ 74LS00 Application Example


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PDF GD54/74LS00 GD74LSOO GD74LS04 74LS04 74LS00 pin configuration gd74ls04 74LS00 function table 74LS00 pin configuration 74LS00 74LS00 Electrical and Switching characteristics 74LS04 NOT gate GD74LSOO 74LS00 clock frequency pin configuration 74LS04
74LS00 clock frequency

Abstract: 74LS00 function table pin configuration 74LS00
Text: lIoJ lioJ Function Table (each gate) OUTPUT INPUTS 1 2 A B V 1A 1B 3 H , GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. K performs the Boolean functions Y = A B or Y = A + B in positive logic , . - 6 5 ° C to 1 5 0 ° C 4-3 GD54/ 74LS00 Recommended Operating Conditions SYMBOL MIN , -1 1 . 4-4 GD54/ 74LS00 Application Example Crystal Clock Generator (1) G D74LS00 c


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PDF GD54/74LS00 D74LS00 D74LS04 74LS00 clock frequency 74LS00 function table pin configuration 74LS00
IC 74LS00

Abstract: 74LS00 74LS00 pin configuration 74LS00 function table pin configuration 74LS00 74LS00 clock frequency NAND 74LS00 74LS00 Electrical and Switching characteristics 74LS00 application 74ls00 NAND gate
Text: GD54/ 74LS00 QUADRUPLE 2-INPUT POSITIVE NAND GATES Description This device contains four independent 2-input NAND gates. It performs the Boolean functions Y = A B or Y = A + B in positive logic. Pin Configuration V cc 14 4B 13 4A 12 4Y 11 3B 10 3A 9 3Y 8 Function Table (each gate) INPUTS A H , . - 6 5 CC to 1 5 0 ° C 2-45 40HÖ7S7 OOGHnO fib4 GD54/ 74LS00 Recommended Operating , GD54/ 74LS00 Application Example Crystal Clock Generator (1) G D 7 4 L S 0 0 c, Frequency (MHz) 1


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PDF GD54/74LS00 402B757 IC 74LS00 74LS00 74LS00 pin configuration 74LS00 function table pin configuration 74LS00 74LS00 clock frequency NAND 74LS00 74LS00 Electrical and Switching characteristics 74LS00 application 74ls00 NAND gate
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA HCTL1100
Text: these routines are listed in Table 1. These execution times do not include stack operations and , current design is utilizing the 8051's bus structure. If your 8051 design is Table 1. Execution Times , AD1 AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL1100 HCTL1100. HCTL-1100s 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA
ls 7400

Abstract: 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
Text: DIP N7400N, N74LS00N, N74S00N Plastic SO N74LS00D, N74S00D FUNCTION TABLE INPUTS OUTPUT A B Y L , Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , . INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74S , 74LS A, B Inputs 1ul 1Sul 1 LSul , , 1N3064, or equivalent. tTLH. t-rHL Values should be less than or equal to the table entries. VM = 1.3V , .) PARAMETER TEST CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max


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PDF 74LS00 74SOO N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul WF07570S ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74LS00 signetics 74l500 74ls00 tr tf 74LS00 function table
2007 - 3 to 8 line decoder using 8051

Abstract: 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET HCTL-1100 74LS138 HCTL-1100 M-015 HCTL-1100s
Text: difference between the two approaches. The execution times for these routines are listed in Table 1. These , HCTL-1100s. Table 1. Execution Times Read Operation I/O Port Interface 15 ms at 12 MHz 180 Clock , AD2 AD3 AD4 AD5 AD6 AD7 1 2 OE CHIP 1\ CS CHIP 1\ 74LS00 5 4 6 Y0 Y1 Y2 Y3 , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 8 11 HCTL-1100 74LS00 74LS138 35 14 18 Vcc \ DENOTES AN ACTIVE LOW SIGNAL


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL-1100. WR1100: CS1100 3 to 8 line decoder using 8051 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET 74LS138 HCTL-1100 M-015 HCTL-1100s
74LS00 function table

Abstract: ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
Text: ; TA = 0°C to + 70°C N7400N, N74LS00N, N74S00N N74LS00D, N74SOOD FUNCTION TABLE INPUTS A L L H H H , Products TYPE 7400 74LS00 74S00 TYPICAL PROPAGATION DELAY 9ns 9.5ns 3ns TYPICAL SUPPLY CURRENT , . INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A, B Y MOTE: Where a 74 unit load (ul) is understood , equivalent. triH , tTHL Values should be less than or equal to the table entries. Input Pulse Definition , 74LS00 Max Min 2.7 0.4 Typ2 3.4 0.35 0.25 -1 .5 0.5 0.4 -1 .5 Max Min 2.7 74S00 UNIT Min Typ2 3.4 0.2


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74SOOD 74LS00 function table ls 7400 pin configuration logic symbol 74LS00 specification of 74ls00 74LS00 pin configuration TTL LS 7400 logic symbol 74LS00 TTL 74ls00 7400 ls pin configuration 74LS00
7400 signetics

Abstract: 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
Text: N7400N, N74LS00N, N74S00N Plastic SO N74LS00D, N74S00D FUNCTION TABLE INPUTS OUTPUT A B Y U L H L , Specification TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7400 9ns 8mA 74LS00 9.5ns 1.6mA , OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74 74S 74LS A, B Inputs 1ul 1Sul 1 LSul y Output , , 1N3064, or equivalent. tTLHi tTHL Values should be less than or equal to the table entries. 1.3V for , CONDITIONS1 7400 74LS00 74S00 UNIT Min Typ2 Max Min Typ2 Max Min Typ2 Max HIGH-level OH output


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PDF 74LS00 74S00 N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul 7400 signetics 74LS00 7400 74S00 N7400N 7400 pin configuration 74LS00 function table 7400 signetics TTL 74LS00 DATA TTL 7400 TTL 7400 propagation delay 74LS00 pin configuration
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74LS00 74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 74LS00 DATA
Text: SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 , Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC , Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table 20 VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN =


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74LS00 74LS00 TTL TTL 74LS00 74LS00 truth table 74LS00DC 74ls00 tphl tplh NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE motorola 74LS00 74LS00 DATA
74LS00 fan-out

Abstract: 74LS00 TTL 74LS00 noise immunity 7400 fan-in 74LS00 gate 74LS00 Electrical and Switching characteristics TTL 7400 rise and fall time 74ls00 applications ttl 74ls00 series logic symbol 74LS00
Text: or 10 U.L. 40nA Relative load and drive factors for the basic TTL families are given in Table 1. Table 1 Family 74LS00 7400 9000 74H00 74S00 Input Load High 0.5 U.L. 1 U.L. 1 U.L. 1.25 U.L. 1.25 U.L , +125°C. TTL families may be mixed for optimum system design. The following table specify the worst case , 3. The 74LS00 gate which has an Iil of 0.36 mA and an I ih of 20 |iA, has input LOW load factor of , the 74LS00 (Commercial Grade) will sink 8.0 mA in the LOW state and source 400 l±A in the HIGH state


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PDF 54H/74H) 74LS00 fan-out 74LS00 TTL 74LS00 noise immunity 7400 fan-in 74LS00 gate 74LS00 Electrical and Switching characteristics TTL 7400 rise and fall time 74ls00 applications ttl 74ls00 series logic symbol 74LS00
74LS00 TTL

Abstract: TTL 74LS00 74LS00 74ls00 NAND gate 74LS00 DATA 74LS00 QUAD 2-INPUT NAND GATE 74LS00 truth table NAND 74LS00 74LS00DC 74ls00 tphl tplh
Text: SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 , Output Current - Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC , 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 54, 74 0.25 0.4 V , Table 20 VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V ­ 0.4 mA VCC = MAX, VIN =


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74IOL 74LS00 TTL TTL 74LS00 74LS00 74ls00 NAND gate 74LS00 DATA 74LS00 QUAD 2-INPUT NAND GATE 74LS00 truth table NAND 74LS00 74LS00DC 74ls00 tphl tplh
74LS00 TTL

Abstract: 74LS00 truth table IC TTL 74LS00 74LS00 74LS00 QUAD 2-INPUT NAND GATE TTL 74ls00 74LS00DC motorola 74LS00 74ls00 NAND gate 74LS00 gate
Text: MOTOROLA SN54/ 74LS00 QUAD 2-INPUT NAND GATE · ESD > 3500 Volts QUAD 2-INPUT NAND GATE fn l [ïïl fïïl [Til fïïl ITI 171 J SUFFIX CERAMIC CASE 632-08 VCC LOW POWER SCHOTTKY Lü Ll I , Output Current - High Output Current - Low mA mA FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC , . IOH = MAX, V|N = V |H or V | l per Truth Table lOL - 4-0 rnA Iq l - 8 Û mA V c c = V c c MIN, V | N - , ) Power Supply Current Total, Output HIGH Total, Output LOW -2 0 per Truth Table VCc = MAX, V|N =


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD SN54/74LS00 74LS00 TTL 74LS00 truth table IC TTL 74LS00 74LS00 74LS00 QUAD 2-INPUT NAND GATE TTL 74ls00 74LS00DC motorola 74LS00 74ls00 NAND gate 74LS00 gate
TTL 74ls00

Abstract: 74LS00 74LS00 TTL motorola 74LS00 74LS00 truth table NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 DATA 74ls00 NAND gate 74LS00DC
Text: (g) MOTOROLA QUAD 2-INPUT NAND GATE • ESD > 3500 Volts vcc nn [ïïi ra m ra m m LlI LLI LLI LLI LiJ LLI LLI gnd SN54/ 74LS00 QUAD 2-INPUT NAND GATE LOW POWER SCHOTTKY GUARANTEED OPERATING , Current — Low 54 4.0 mA 74 8.0 FAST AND LS TTL DATA 5-2 SN54/ 74LS00 DC CHARACTERISTICS OVER , = WIN, IQH = MAX, V|N = V|H or V|_ per Truth Table 74 2.7 3.5 V Vol Output LOW Voltage 54, 74 0.25 0.4 V Iqu = 4.0 mA VCC = VCC m'n, V|n = V|LOr V|h per Truth Table 74 0.35 0.5 V Iql =


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PDF SN54/74LS00 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD TTL 74ls00 74LS00 74LS00 TTL motorola 74LS00 74LS00 truth table NAND 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 DATA 74ls00 NAND gate 74LS00DC
t74ls157

Abstract: 74LS00E 74LS00 fan out T74LS74 74LS00 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate 74ls00 series T74LS367 NAND 74LS00
Text: , VIH 2.0V, Vol 0.5V, VOH 2.7V T74 SERIES INPUT LOADING — THE 74LS00 INPUT LOADING IS Iil 0.36mA (LOW INPUT) AND I IH 20MA (HIGH INPUT) OUTPUT DRIVE — THE 74LS00 OUTPUT DRIVE IS Iol 8.0mA (SINK) AND I oh , DEVICES WITHIN THE FAMILY AND IS NORMALIZED AROUND THE INPUT REQUIREMENTS OF THE 74LS00 .E.G. THE 74LS00 , -54/74 LS SERIES NUMERICAL DEVICE LISTING DEVICE TYPE FUNCTION FAN OUT PINS PACKAGE* PLASTIC , NUMERICAL DEVICE LISTING (CONT.) DEVICE TYPE FUNCTION FAN OUT PINS PACKAGE' PLASTIC CERAMIC


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PDF TTL-54/74 74LS00 400/u 400mA SO-14. t74ls157 74LS00E 74LS00 fan out T74LS74 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate 74ls00 series T74LS367 NAND 74LS00
1998 - pin diagram of 74ls00

Abstract: 74LS00 74ls00 datasheet 74HC74 motorola 74LS00 memory card circuit diagram 74HC74 decoder inverter wait 74LS00 impedance 74LS00 application
Text: B B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2


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PDF 74HC04 0xfff44b 0xfff449 0xfff448 0xfff443 0xfff441 0xfff440 pin diagram of 74ls00 74LS00 74ls00 datasheet 74HC74 motorola 74LS00 memory card circuit diagram 74HC74 decoder inverter wait 74LS00 impedance 74LS00 application
TTL LS 7400

Abstract: IC TTL 74LS00 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 of ic 74ls00 74LS00 gate TTL 7400 rise and fall time
Text: families are given in Table 3.3. INPUT LOAD OUTPUT DRIVE FAMILY HIGH 74LS00 7400 9000 74H00 , . Table 3.1 lists the guaranteed logic levels for various TTL families and can be used to calculate noise margin. Table 3.2 specifies these noise margins for systems containing LS, S, ALS and/or FASTTM TTL. Note that Table 3.2 represents "worst case" limits and assumes a maximum power supply and temperature , can be achieved by designing with decreased maximum allowable operating ranges. Table 3.1 Worst


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PDF
pin diagram of 74ls00

Abstract: 74HC04 74HC74 74LS00 74HC74 decoder motorola 74LS00 74LS00 application 74LS00 impedance 74ls00 circuit diagram inverter wait
Text: 74HC04 U2A 2 B Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11


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PDF Informatfff448 0xfff443 0xfff441 0xfff440 0xfff44b 0xfff449 0xfff448 pin diagram of 74ls00 74HC04 74HC74 74LS00 74HC74 decoder motorola 74LS00 74LS00 application 74LS00 impedance 74ls00 circuit diagram inverter wait
74LS00

Abstract: motorola 74LS00 datasheet of ic 74ls00 74LS00 impedance pin diagram of ic 74ls00 pin diagram of 74ls00 74ls00 circuit diagram 74HC74 decoder 74HC74 inverter wait
Text: Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 Q


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PDF 0fff448 0xfff443 0xfff441 0xfff440 0xfff44b 0xfff449 0xfff448 74LS00 motorola 74LS00 datasheet of ic 74ls00 74LS00 impedance pin diagram of ic 74ls00 pin diagram of 74ls00 74ls00 circuit diagram 74HC74 decoder 74HC74 inverter wait
datasheet of ic 74ls00

Abstract: pin diagram of ic 74ls00 pin diagram of 74ls00 motorola 74LS00 74LS00 74HC74 74HC74 decoder 74LS00 impedance 74LS00 application 74HC74 application
Text: Q1 13 12 2 *Q1 1 74LS00 U1D 74LS00 U1A 11 3 *Q0 9 10 74LS00 U1B C 74LS00 U1C 4 5 C 8 6 D1 D1 D0 3 11 12 3 2 Q


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PDF 0xfff44b 0xfff449 0xfff448 0xfff443 0xfff441 0xfff440 datasheet of ic 74ls00 pin diagram of ic 74ls00 pin diagram of 74ls00 motorola 74LS00 74LS00 74HC74 74HC74 decoder 74LS00 impedance 74LS00 application 74HC74 application
1996 - 74l500

Abstract: 74LS00 UF 407 Diode 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 datasheet of ic 74ls00 LOGIC OF 74L500 diode u1d ON u1d diode
Text: 1 R1 10 IN1 L6203 1 IN2 3.6 A MOTOR 3 8 1 12 U1B 74LS00 9 U1C 74LS00 6 GND U1D 74L500 C2 22 nF 2 1 U1A 74LS00 2 4 1 2 7 FROM


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PDF HCTL-1100 M-024 DAC08 REF-01 74l500 74LS00 UF 407 Diode 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 datasheet of ic 74ls00 LOGIC OF 74L500 diode u1d ON u1d diode
IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Text: Support for TTL Macrofunctions Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 1 o f 3 , Page 325 PLS-EDIF Data Sheet Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 2 o , P L U S -c o m p a tib le functions. Table 1. Mentor Graphics Library Mapping File (Basic Functions) Mentor Graphics Function AND# BUF DELAY DFF INV JKFF LATCH NAND# NOR# OR# XFER XNOR2 XOR2 MAX+PLUS-Compatible Function AND# SCLK MCELL DFF2 NOT JKFF2 MLATCH NAND# NOR# OR# TRI XNOR XOR (#=2,3,4,5 6,9) (#=2,3


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PDF
74HC00M

Abstract: IC 74HC00 74hc00 equivalent 74LS00 PIN 54HC00 74HC00 74HC00 quad CMOS nand gate 14 pin 74HC00 74HC00 SERIES DATA M74HC00M1R
Text: RANGE Vcc (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS00 SYMMETRICAL OUTPUT IMPEDANCE I I , 54/M 74HC00 TRUTH TABLE A L L H H B L H L H Y H H H L .A I B 2 2 A B II 2 - I Ì 2 - ^ ^ \ ( 6 ) à , , 11 7 14 3 B Ü 5 L SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND Vcc NAME AND FUNCTION Data Inputs Data


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PDF 54HC00 74HC00 54/74LS00 54HC00F1R 74HC00M 00B1R M54/74HC00 NAN95 IC 74HC00 74hc00 equivalent 74LS00 PIN 74HC00 74HC00 quad CMOS nand gate 14 pin 74HC00 74HC00 SERIES DATA M74HC00M1R
TTL 74HC00

Abstract: 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
Text: Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB nY L L H L H H H L H H H L H-HIGH , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for opération over Wide temperature ranges to meet in-dustry and military spécifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL 5V 74HC00 logic symbol 74LS00 TTL 74ls00 74LS00 gate diagram 74LS00 function table 74ls00 74hc00 and gates 74HC00
74LS00 pinout

Abstract: TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
Text: Logic Symbol and Logic Diagram Function Table INPUTS OUTPUT nA nB nY L L H L H H H L H H H L , GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/ 74LS00 . They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet industry and military specifications. Features • Low Power consumption characteristic of CMOS devices • Output drive capability: 10 LS TTL


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PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74LS00 pinout TTL 74HC00 74hc00 and gates 5V 74HC00 74HC00 logic symbol 74LS00 pin configuration logic symbol 74LS00 GD74HC00 74LS00 gate diagram GD54HC00
74LS00 integrated circuit

Abstract: No abstract text available
Text: Package) C1R (Chip Carrier) tPLH = tPHL ■PIN AND FUNCTION COMPATIBLE WITH 54/ 74LS00 â , -6946 >- 9 o >- < NZ zw O O 1/4 99 M 54/M 74HC T00 IEC LOGIC SYMBOL TRUTH TABLE A B Y , NAME AND FUNCTION 1 ,4 ,9 , 12 1A to 4A Data Inputs 2, 5, 10, 13 1B to 4B Data Inputs


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PDF M54HCT00 M74HCT00 54/74LS00 M54/74HCT00 74LS00 integrated circuit
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