74HC112PW
Philips Semiconductors
dual JK flip-flop with set and reset negative-edge trigger
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74HC112PW
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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74HC112PW,112
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax : 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Tube
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74HC112PW,118
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax : 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Reel Pack, SMD, 13"
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74HC112PW/C,118
NXP Semiconductors
74HC112PW/C - dual JK flip-flop with set and reset; negative-edge trigger, SOT403-1 Package, Standard Marking, Reel Pack, SMD, 13"
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74HC112PW-T
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax : 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V
Original
PDF
74HC112PW-T
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
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PDF