74HC112DB-T Search Results
74HC112DB-T Datasheets (2)
Part | ECAD Model | Manufacturer | Description | Curated | Type | |
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74HC112DB-T |
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dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V | Original | |||
74HC112DB-T |
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Scan |