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Part Manufacturer Description Datasheet Download Buy Part
LTC4150CMS#TR Linear Technology LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
LTC4150CMS Linear Technology LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
LTC4150IMS Linear Technology LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4150CMS#PBF Linear Technology LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
LTC4150IMS#TR Linear Technology LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC4150CMS#TRPBF Linear Technology LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C

7476 up down counter Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: trigger ) Dual 2-Input NAND Gate Up / Down Decade Counter Hex D-Type Flip-Flop 4520 4018 4516 74121 , ( Presetable ) Dual BCD Counter Dual Binary Counter 8-Stage Counter Up / Down Decade Counter 74390 / 4017 , CMOS chips that are readily available over the counter ( from such places as Maplin Electronics in the , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2 , -Bit Magnitude Comparator Quad 2-Input XOR Gate Decade Counter 4-Bit Binary Counter Monostable Multivibrator


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FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Text: Quad D-type flip flops Synchronous up / down counter binary 74191 Synchronous up / down counter BCD with clear Syn. up / down dual clock counter bin. with clear 74193 4-bit redirectional universal , register 8-bit synchronous binary down counter Hex Schmitt trigger Strobed hex inverter/buffer BCD up / down counter BCD to 7-segment latch/decoder/driver 1 of 16 decod/demult. with input latches Binary up / down counter Dual BCD counter Dual binary counter Programmable 4-bit BCD down counter


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PDF 74INTEGRATED Line-to-10 150ns 16-DIL 150ns 18-pin 250ns 300ns FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
74LS80

Abstract: 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
Text: , Individual Reset B & S et B MODULO UP / DOWN COUNTER CUD41 CUD42 Modulo 16, Up / Down Counter , Expandable Enable G e a r Direct Modulo 16, Up / Down Counter , Expandable w ith Asynchronous Load and G ear , M odulo 16, Binary Up Counter , Expandable Enable Sync G ear M odulo 16, Binary Up C ounter Fast , 4 Bit Bed C ounter (74 L S I6 2 ) Synchronous 4 Bit Bed Counter (74LS162) Synchronous 4 Bit Up /Dow n , Bit Binary Couner Decade Counter /D river (4017) Dual Binary Up C ounter ROgiCO 4-77 4AE » ' 1


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PDF 77MLjbc 0001L3M TEK-044-9004 RSC-15 TBF368 M390C M393C CM16BR* M540C M541C 74LS80 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
7476 up down counter

Abstract: 7476 counter CD4029BCN CD4029BCSJ CD4029BCWM CD4029BC M16D MS-001 MS-013 N16E
Text: /Decade Up / Down Counter General Description The CD4029BC is a presettable up / down counter which counts , binary/ decade is at logical "1", the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up / down input is at logical "1" and vice versa. A logical "1" preset , logical "0" state when the counter reaches its maximum count in the " up " mode or the minimum count in the , 74LS ■Parallel jam inputs ■Binary or BCD decade up / down counting o o -fi o IO CO 00 O CD CO


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PDF CD4029BC CD4029BC 7476 up down counter 7476 counter CD4029BCN CD4029BCSJ CD4029BCWM M16D MS-001 MS-013 N16E
7476 counter

Abstract: 7476 counter down ci 7476 7476 up down counter CD4029BCWM CD4029BCN M16D MS-001 MS-013 N16E
Text: /Decade Up / Down Counter General Description The CD4029BC is a presettable up / down counter which counts , binary/ decade is at logical "1", the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up / down input is at logical "1" and vice versa. A logical "1" preset , logical "0" state when the counter reaches its maximum count in the " up " mode or the minimum count in the , 74LS ■Parallel jam inputs ■Binary or BCD decade up / down counting Ordering Code: Order Number


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PDF CD4029BC CD4029BC 7476 counter 7476 counter down ci 7476 7476 up down counter CD4029BCWM CD4029BCN M16D MS-001 MS-013 N16E
2007 - IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
Text: Analog Inputs and 2 Analog Outputs AUTOMATIONWORX Data Sheet 7476 _en_02 © PHOENIX CONTACT - 10/2007 , disregard of information contained in this data sheet. 7476 _en_02 PHOENIX CONTACT 2 ILB BT , 7476 _en_02 MODE 16 dBm 12 dBm 8 dBm 4 dBm 0 dBm DIP switches for setting the , antenna cable are available on request. 7476 _en_02 PHOENIX CONTACT 4 ILB BT ADIO 2/2/16/16 , vehicle. Air pressure (operation) 80 kPa to 108 kPa ( up to 2000 m above sea level) Air pressure


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PDF Bm/39 IC 7476 INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
INTERNAL DIAGRAM OF IC 7476

Abstract: 4029bc D4029BC 7476 up down counter cd4029bcn 7476 counter CD4029BC UP DOWN COUNTER LD 7476 PS
Text: Presettable Binary/Decade Up / Down Counter General Description The C D 4029BC is a presettable up / down , both V qq and Vgs- Presettable Binary/Decade Up / Down Counter Features W ide supply voltage , Presettable Binary/Decade Up / Down Counter Physical Dimensions in c h e s (m illim e te rs ) u n le s s o , counts in decade. Sim ilarly, th e coun ter counts up w hen the up / down input is at logical " 1 " and , L com patibility: o r 1 driving 74LS Parallel jam inputs Binary or BCD decade up / down counting


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PDF CD4029BC CD4029BC 4029BC INTERNAL DIAGRAM OF IC 7476 D4029BC 7476 up down counter cd4029bcn 7476 counter CD4029BC UP DOWN COUNTER LD 7476 PS
T510S

Abstract: T691S
Text: /dt)cr A/ps DIN IEC 747-6 MS (dv/dt)cr V/ps DINIEC 747-6 typ. V gt I gt R th J C T v j , Tvj = T V| max T , j max + 100V up to 1400\ ' continued T 408 F 1000. 1300* 750 6,40 2,20/1,4 1 , C*£12 ^ 2,2 300 0,0180 125 TS27 up to 2000V T 468 S 1600.2000* 1300 8,30 3,35 , M* = 1000 2,2 250 0,0210 125 TS27 N = 1000 2,0 300 0,0373 125 TS25 2,2 250 0,0400 125 TS22 up to , Asymetrische Thyristoren (d i/d t)* O ps typ. (dv/dt)cr V/ps DIN IEC 747-6 V gt Ig t RthJC


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PDF T510S T510S T691S
ts26

Abstract: DIODE ED 11 T188F TS18 25G30
Text: (TO) V T ,= rT m Q Tv¡ = (di/dt) cr A /ps MS (d v /d t)cr V/|js DIN IEC 747-6 ! V gt V , T vj m a x DIN IEC 747-6 25°C 25°C 180° el sin 100V(50Hz) 1 1 u p to 80 ) V T 72 F , VT/ I T V /k A T v j max V (TO) rT (d i/d t)c A/| js DIN IEC 747-6 A kA 10 ms, T vj max V T ,= T v j max m fi Tvi `q MS (d v /d t)or V / ms DIN IEC 747-6 V gt Ig t , , Vrsm =Vrrm+ 100 V = T v j max 25°C up to 1400 V cont. T 599 F T 600 F 1200.1300* 1500


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TS2422

Abstract: GS12 TS20 TS22 TS24 TS27 T510S
Text: m Tvj = Tvj max (di/dt)cr A/µs DIN IEC +100V up to 1400V continued T 408 F 1000.1300 , (dv/dt)cr V/µs DINIEC 747-6 VGT V Tvj = 25°C IGT mA Tvj = 25°C RthJC Tvj max outline , ,0160 = B or C 120 125 120 TS26 TS26 GS12 747-6 T 600 F T 1052 S tq µs typ. 1000.1200 TS24 2200 20 2,70/4,0 1,45 0,3 400 up to 2000V T 468 S 1600.2000 , . DIN IEC Tvj = Tvj = 180° el 747-6 25°C 25°C sin C = 500 F = 1000 2,7


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74LS324

Abstract: 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74LS324 equivalent 74C08 equivalent 74C923 equivalent Flip-Flop 7473
Text: 256-Bit PROM, Open Collector Output 64-Bit RAM, 3-State Outputs Synchronous Up / Down BCD Counter Synchronous Up / Down BCD Counter Synchronous Up / Down Binary Counter Synchronous Up / Down Binary Counter Synchronous Up / Down BCD Counter (Dual Clock with Gear) / Synchronous Up / Down BCD Counter (Dual Clock with Clear) Synchronous Up / Down BCD Counter (Dual Clock with Clear) Synchronous Up / Down Binary Counter (Dual Clock with Clear) Synchronous Up / Down Binary Counter , (Dual Clock with Clear) Synchronous Up / Down


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PDF G0G513S 74C00 74H00 74LS00 74S00 74H01 74LS01 74C02 74LS02 74S02 74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74LS324 equivalent 74C08 equivalent 74C923 equivalent Flip-Flop 7473
pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , Flip-Flops 7476 , LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIG


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , Table. 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , Manufacturer 853-0568 81501 Signetics Logic Products _Product Specificotion Flip-Flops 7476 , LS76 LOGIC , inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1985


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PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: Sjgnetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476 , the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock


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PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , 81501 Signetics Logic Products Product Specification Flip-Flops 7476 , LS76 LOGIC DIAGRAM , inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1965


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Not Available

Abstract: No abstract text available
Text: spaces. 80-inch 70-inch 1,538.9 mm 1,329.1 mm 747.6 mm 1,771.2 mm 60-inch 865.6 mm , locationappropriate background music. Power Consumption Comparison (W) 500 400 300 400W Approx. 32% down Approx. 40% down 270W 200 240W 170W 100 0 Approx. 58% down Conventional , then distributed via the network to up to 100 clients* according to a set schedule. Note: Networked , PN-E602 1,329.1 x 747.6 mm (52 5/16" x 29 7/16") Max. Resolution Max. Display Colours (approx


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PDF PN-E802 PN-E702 PN-E602 PN-E802/E702/E602 80-inch 100th Sizes00 PN-ZH802* PN-ZH702*
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Flip-Flops 7476 , LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIGH for


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PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
2011 - TS820600T

Abstract: TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
Text: Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820, TYN608 1 , 200 0.8 0.1 8 5 6 5 1.6 0.85 46 5 Unit µA V V V mA mA V/µs V V m µA 2/13 Doc ID 7476 Rev 7 , 6 IT(AV)(A) 1 0 0 25 Tcase(°C) 50 75 100 125 Doc ID 7476 Rev 7 3/13 , 1.5 Tj(°C) 1.0 0.5 0.0 1E-2 1E-1 RGK(k) 1E+0 1E+1 4/13 Doc ID 7476 Rev 7 TN805 , 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 S(cm²) 0 0 2 4 6 8 10 12 14 16 18 20 Doc ID 7476 Rev 7 5/13


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PDF TN805, TN815 TS820, TYN608 TS820-6d TS820600T TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
2011 - TS820 600T

Abstract: No abstract text available
Text: -220AB October 2011 X Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820 , 220 Ω Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 7 MAX. TN805, TN815, TS820, TYN608 , ) 0 0 0 1 2 3 4 5 6 0 Doc ID 7476 Rev 7 25 50 75 100 125 , Doc ID 7476 Rev 7 RGK(kΩ) 1E-1 1E+0 1E+1 TN805, TN815, TS820, TYN608 Figure 9 , ID 7476 Rev 7 2 4 6 8 10 12 14 16 18 20 5/13 Ordering information


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PDF TN805, TN815 TS820, TYN608 TS820-600H TN805-600B TN815-x00B TS820-600B TS820 600T
2010 - TYN608

Abstract: TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Text: ID 7476 Rev 6 X 1/12 www.st.com 12 Characteristics TN805, TN815, TS820, TYN608 , VRRM, RGK = 220 Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 6 MAX. TN805, TN815, TS820 , ID 7476 Rev 6 25 50 75 100 125 3/12 Characteristics Figure 3. TN805 , ) 0.5 0.0 60 80 100 120 140 0.0 1E-2 Doc ID 7476 Rev 6 1E-1 1E+0 1E+1 , 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 Doc ID 7476 Rev 6 2 4 6 8


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PDF TN805, TN815, TS820 TYN608, TYN808, TYN1008 TN805-xxxB TN815-xxxB TS820-xxxB TN805-xxxH TYN608 TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Not Available

Abstract: No abstract text available
Text: fully synchronous 8-stage up / down counter with m ultiplexed 3-STATE I/O ports for bus-oriented a pplica­ tions. All control functions (hold, count up , count dow n, syn­ chronous load) are controlled , R C H II_ D E M IC O N D U C T O R t 74F779 8-Bit Bidirectional Binary Counter with , e m i.c o m 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs February 1998 F /M , utputs A ppear on I/O Lines Parallel Load All Flip-Flops H L L X C ount Up L H L


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PDF 74F779
7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Text: TEXAS 75 26 5 TTL SN 5476, SN 7476 DUAL J-K FLIP FLOPS WITH PRESET AND CLEAR logic diagrams , 75 26 5 SN 5476, SN 54LS 76A , SN 7476 , S N 74 LS7 6A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR , D e v ic e s logic sym bols* SN 5476, SN 54LS76A , SN 7476 , SN 74 LS 7 6A DUAL J-K FLIP-FLOPS , 75 26 5 SN 5476, SN 7476 DUAL J K FLIP FLOPS WITH PRESET AND CLEAR recommended operating conditions S N 5476 M IN Vcc V |H V |l Iq h Iq l S N 7476 MAX 5.5 M IN 4 .7 5 2 0.8 -0 .4 16 0.8 -0 .4


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PDF SN547G, SN54LS76A, SN7476, SN74LS76A 7476 ic specifications ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
logic ic 7476 pin diagram

Abstract: INTERNAL DIAGRAM OF IC 7476 ic 7476 pin diagram display TABLET 40 pin TR88L804 and pin diagram of IC 7476 pin diagram for IC 7476 "Tritech Microelectronics" CQ 10.000 crystal oscillator TR88L803
Text: Current Power up PD_RST=Logic 0 1.7 3 mA 'vDDPD Digital Supply Current Power down PD_RST=Logic 1 0.1 1 , 15 PDRST TTL Schmitt Input Active-High Power down /Reset input. Assert Logic 1 for a 10ns to reset , . 18 PDRST TTL Schmitt Input Active-Hi Power down /Reset input. Assert Logic 1 for a 10ns to reset. Hold , on the display as "ink". Resistive Digitizers A resistive digitizer is made up of a multi-layer , -) and sense the voltages picked up by the Y-plane resistive film (via Y+, Y-). The current drive to the


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PDF TR88L803/804 10-Bit TR88L804) TR88L803) TR88L803/804 app06 28-pin TR88L803CS 16-pin logic ic 7476 pin diagram INTERNAL DIAGRAM OF IC 7476 ic 7476 pin diagram display TABLET 40 pin TR88L804 and pin diagram of IC 7476 pin diagram for IC 7476 "Tritech Microelectronics" CQ 10.000 crystal oscillator TR88L803
ts21

Abstract: ITRMSM TS17 TS18 TS20 TS-21 TS21C T188F
Text: Click on outline no. Fast Thyristors Type ITRMSM I/TSM VDRM VRRM V A kA VDSM = VDRM 10 ms VRSM = VRRM Tvj max VT/IT V/kA Tvj max V(TO) V(TO) Tvj = Tvj max rT m Tvj = Tvj max +100V(50V)1) (di/dt)cr A/µs DIN IEC tq µs typ. (dv/dt)cr V/µs DINIEC 747-6 B = 50 C* = 500 L = 500 M* = 1000 B = 50 C* = 500 L = 500 M* = 1000 C = 500 747-6 up , 2) E 20 D 15 C* 12 2) S 18 D 15 C* 12 T 1078 F up to 1400V T 80 F 1200.1400


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LM 4017 decade counter driver

Abstract: 74HC7244A 74HCT7007A 74HC11A 74HC147 decimal to binary encoder 74HC85A cmos 4008 74HC21A 74HC07A 74HC283A
Text: WITH ASYNC. CLEAR SYNC. BINARY COUNTER WITH SYNC. CLEAR 4-BIT BINARY UP / DOWN COUNTER SYNC. UP / DOWN , -BIT BINARY COUNTER SYNC. DECADE COUNTER WITH ASYNC. CLEAR SYNC. DECADE COUNTER WITH SYNC. CLEAR BCD UP / DOWN COUNTER SYNC. UP / DOWN DECADE COUNTER DUAL DECADE COUNTER DECADE COUNTER REGISTER (3-STATE) DECADE COUNTER , /_ VCC A O D ® / / LOAD C D SYN. 4-BIT UP / DOWN COUNTER 190 191 BCD BINARY V cc \ CA CB , -STAGE BINARY COUNTER 14-STAGE BINARY COUNTER /OSCILLATOR DUAL BCD PROGRAMMABLE DOWN COUNTER 8-BIT BINARY


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PDF 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30 71HC132A 74HC133A 74HC02A 74HCT02A LM 4017 decade counter driver 74HC7244A 74HCT7007A 74HC11A 74HC147 decimal to binary encoder 74HC85A cmos 4008 74HC21A 74HC07A 74HC283A
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