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Part Manufacturer Description Datasheet Download Buy Part
SN7476N-00 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
SN7476N-10 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
SN7476J Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch
SN7476J-00 Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch
ADCS7476AISDX Texas Instruments 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, DSO6, LLP-6
ADCS7476AIMFX Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125

7476 ttl Datasheets Context Search

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ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , Table. 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , Manufacturer 853-0568 81501 Signetics Logic Products _Product Specificotion Flip-Flops 7476 , LS76 LOGIC , inputs of the 7476 must be stable while the Clock is HIGH for conventional operation. December 4, 1985


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PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: Sjgnetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476 , the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock


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PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: Flip-Flops 7476 , LS76 TEST CIRCUITS AND WAVEFORMS VM = 1.3V for 74LS; V m = 1-5V for all other TTL , Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , 81501 Signetics Logic Products Product Specification Flip-Flops 7476 , LS76 LOGIC DIAGRAM


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Flip-Flops 7476 , LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIGH for


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PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
IC 7476

Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
Text: FAIRCHILD TTL /SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL /SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks. Inputs to the master section are controlled by the clock , FAIRCHILD TTL /SSI • 9N76/5476, 7476 RECOMMENDED OPERATING CONDITIONS PARAMETER 9N76XM/5476XM 9N76XC , MAX- V|N = OV 51 -18 -57 mA 9N76/ 7476 'CC Supply Current 20 40 mA Vcc = MU- 49 SWITCHING


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PDF 9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together. The following tables are available . TTL Device Summary CMOS Device , device is suitable for your purposes. 1 of 12 E&OE. TTL Device Summary Please click on a , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2


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7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Text: TEXAS 75 26 5 TTL SN 5476, SN 7476 DUAL J-K FLIP FLOPS WITH PRESET AND CLEAR logic diagrams (positive logic) TTL D e v ic e s 2 248 INSTTOJMENTS POST OFPICE BOX 6 5 5 0 1 2 · D ALLAS. TEXAS 75 26 5 SN 5476, SN 54LS 76A , SN 7476 , S N 74 LS7 6A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR , Te x a s ^ In s t r u m e n t s POST OFFICE BOX 6 5 5 0 1 2 · D ALLAS . TEXAS 75 26 5 249 TTL D e v ic e s logic sym bols* SN 5476, SN 54LS76A , SN 7476 , SN 74 LS 7 6A DUAL J-K FLIP-FLOPS


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PDF SN547G, SN54LS76A, SN7476, SN74LS76A 7476 ic specifications ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
7476 truth table

Abstract: No abstract text available
Text: purpose use. This device has TTL compatible inputs and outputs and requires+5V and -12 V power supplies , next column to right. 2. Underlined addresses result In all outputs going low ( TTL "0"). 3. Black , ASCII in next column to right. 2. Undefined addresses result in all outputs going low ( TTL “0"). 3. Black squares in character font are high { TTL “V ). 130 CUSTOM CODING INFORMATION 2526 , € Blank Name 2 Data Cards Card No. 1 Column 1-9 10 11-19 20 21-29 73 74-76 77


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PDF 2526-N, 184-bit 64x9x9 512x9 0I0I00I0I 0I00I0T0T NQISM3AN03 S33dWVX3 N-92Se 7476 truth table
2526N

Abstract: signetics 2526 7476 truth table pin diagram of 7476 pin diagram of ttl 7476 PIN CONFIGURATION 7476 7x9 decoder 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram decoder 7476
Text: , or as a 512x9 ROM for general purpose use. This device has TTL compatible inputs and outputs and , ORGANIZATION > 625m TYPICAL ACCESS TIME • STATIC OPERATION • OUTPUT LATCHES • TTL /DTL COMPATIBLE INPUTS • TTL /DTL COMPATIBLE TRI-STATE OUTPUTS • Vcc"+5V,Vgq = -12V • 24-PIN SILICONE DIP â , integrated circuits ( TTL , DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA to drive one standard TTL load. STANDARD CODES The 2526 is available with ASCII-addressed characters


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PDF 184-bit 64x9x9 512x9 2526N signetics 2526 7476 truth table pin diagram of 7476 pin diagram of ttl 7476 PIN CONFIGURATION 7476 7x9 decoder 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram decoder 7476
pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , Flip-Flops 7476 , LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock is HIG


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
2007 - IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
Text: Analog Inputs and 2 Analog Outputs AUTOMATIONWORX Data Sheet 7476 _en_02 © PHOENIX CONTACT - 10/2007 , disregard of information contained in this data sheet. 7476 _en_02 PHOENIX CONTACT 2 ILB BT , 7476 _en_02 MODE 16 dBm 12 dBm 8 dBm 4 dBm 0 dBm DIP switches for setting the , antenna cable are available on request. 7476 _en_02 PHOENIX CONTACT 4 ILB BT ADIO 2/2/16/16 , : 1988-05 7476 _en_02 PHOENIX CONTACT 5 ILB BT ADIO 2/2/16/16 Ambient Conditions (Continued


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PDF Bm/39 IC 7476 INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
2011 - TS820600T

Abstract: TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
Text: Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820, TYN608 1 , 200 0.8 0.1 8 5 6 5 1.6 0.85 46 5 Unit µA V V V mA mA V/µs V V m µA 2/13 Doc ID 7476 Rev 7 , 6 IT(AV)(A) 1 0 0 25 Tcase(°C) 50 75 100 125 Doc ID 7476 Rev 7 3/13 , 1.5 Tj(°C) 1.0 0.5 0.0 1E-2 1E-1 RGK(k) 1E+0 1E+1 4/13 Doc ID 7476 Rev 7 TN805 , 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 S(cm²) 0 0 2 4 6 8 10 12 14 16 18 20 Doc ID 7476 Rev 7 5/13


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PDF TN805, TN815 TS820, TYN608 TS820-6d TS820600T TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
2011 - TS820 600T

Abstract: No abstract text available
Text: -220AB October 2011 X Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820 , 220 Ω Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 7 MAX. TN805, TN815, TS820, TYN608 , ) 0 0 0 1 2 3 4 5 6 0 Doc ID 7476 Rev 7 25 50 75 100 125 , Doc ID 7476 Rev 7 RGK(kΩ) 1E-1 1E+0 1E+1 TN805, TN815, TS820, TYN608 Figure 9 , ID 7476 Rev 7 2 4 6 8 10 12 14 16 18 20 5/13 Ordering information


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PDF TN805, TN815 TS820, TYN608 TS820-600H TN805-600B TN815-x00B TS820-600B TS820 600T
pin diagram for jk flip flop 7476

Abstract: jk flip flop 7476 7476 J-K Flip-Flop J-K Flip-Flop 7476 7476 PIN DIAGRAM ci 7476 DN74LS76 7476 PIN DIAGRAM input and output
Text: LS TTL DN74LS Series DN74LS76 DN74LS76 £>ivJ 74^76 Dual J-K Flip-Flops (with Set and Reset) I Description DN74LS76 contains two negative-edge triggered J-K flip-flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. ■Features • Negative-edge , Electronic-Library Service CopyRight 2003 k LS TTL DN74LS Series DN74LS76 DC characteristics (Ta = — 20 â , Electronic-Library Service CopyRight 2003 LS TTL DN74LS Series DN74LS76 [2] tphi . tpLH(Reset, Set —» Q, Q) 1


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PDF DN74LS DN74LS76 DN74LS76 16-pin SO-16D) pin diagram for jk flip flop 7476 jk flip flop 7476 7476 J-K Flip-Flop J-K Flip-Flop 7476 7476 PIN DIAGRAM ci 7476 7476 PIN DIAGRAM input and output
jk flip flop 7476

Abstract: pin diagram for jk flip flop 7476 ci 7476 7476 J-K Flip-Flop J-K Flip-Flop 7476 pin diagram of 7476 PIN CONFIGURATION 7476 DN74LS76 7476 PIN DIAGRAM input and output
Text: LS TTL DN74LS Series DN74LS76 DN74LS76 £>ivJ 74^76 Dual J-K Flip-Flops (with Set and Reset) I Description DN74LS76 contains two negative-edge triggered J-K flip-flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. ■Features • Negative-edge , Copyrighted By Its Respective Manufacturer ;„:• k LS TTL DN74LS Series DN74LS76 DC characteristics (Ta , €ž _ V„H — V„r -118— This Material Copyrighted By Its Respective Manufacturer LS TTL DN74LS


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PDF DN74LS DN74LS76 DN74LS76 16-pin SO-16D) jk flip flop 7476 pin diagram for jk flip flop 7476 ci 7476 7476 J-K Flip-Flop J-K Flip-Flop 7476 pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output
2010 - TYN608

Abstract: TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Text: ID 7476 Rev 6 X 1/12 www.st.com 12 Characteristics TN805, TN815, TS820, TYN608 , VRRM, RGK = 220 Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 6 MAX. TN805, TN815, TS820 , ID 7476 Rev 6 25 50 75 100 125 3/12 Characteristics Figure 3. TN805 , ) 0.5 0.0 60 80 100 120 140 0.0 1E-2 Doc ID 7476 Rev 6 1E-1 1E+0 1E+1 , 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 Doc ID 7476 Rev 6 2 4 6 8


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PDF TN805, TN815, TS820 TYN608, TYN808, TYN1008 TN805-xxxB TN815-xxxB TS820-xxxB TN805-xxxH TYN608 TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
74LS80

Abstract: 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
Text: ( TTL ) "L " Input voltage ( TTL ) " H " Input voltage (CMOS) " L " Input voltage (CMOS) "H " Output , pull-up INT1U1 INT2U1 INTSU1 INC1U1 INC2U1 INCSU1 INTID1 INT2DI INTSD1 INCIDI INC2D1 INCSD1 FUNCTION TTL Compatible TTL TTL CMOS Compatible CMOS CMOS TTL Compatible TTL TTL CMOS Compatible CMOS CMOS TTL Compatible TTL TTL CMOS Compatible CMOS CMOS Inverter Buffer Schmitt Trigger Inverter Buffer Schmitt Trigger , IOCSCH IOCSH IOTI Ul lOTUl 10T2UI I0CIU1 I0CUI I0C2U1 IOTI Dl lOTDl IOC1D1 IOCD1 XIN01 XOUT XIO TTL


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PDF 77MLjbc 0001L3M TEK-044-9004 RSC-15 TBF368 M390C M393C CM16BR* M540C M541C 74LS80 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
co-600v

Abstract: CO-624VD 12KHZ CO-624V-D CO624V
Text: of the 3048A. The equivalent sideband level of the integrated phase noise was ­ 74.76 dBc. Per the , to degrees: X 74.76 dB Equivalent sideband level or the integrated phase noise X , degrees 13 RMS jitter in seconds The sideband level of ­ 74.76 dBc for the integration of the


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PDF CO-600V 12KHz CO-624V-D CO-624VD CO-624V-D CO624V
Not Available

Abstract: No abstract text available
Text: spaces. 80-inch 70-inch 1,538.9 mm 1,329.1 mm 747.6 mm 1,771.2 mm 60-inch 865.6 mm , PN-E602 1,329.1 x 747.6 mm (52 5/16" x 29 7/16") Max. Resolution Max. Display Colours (approx , ) Synchronisation Horizontal/vertical separation ( TTL : positive/negative), Sync on green, Composite sync ( TTL


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PDF PN-E802 PN-E702 PN-E602 PN-E802/E702/E602 80-inch 100th Sizes00 PN-ZH802* PN-ZH702*
1996 - cr 6850 t

Abstract: T 698 DIN 1445 l 0380 T188F
Text: typ. tvj max 747-6 DIN IEC 747-6 tvj = 25°C tvj = 25°C 180° el sin 2,60 F = , tvj max 747-6 max *10³ 24 2880 1200/85 1,05 0,185 200 280 (dv/dt)cr V/µs VGT V IGT mA RthJC tvj max °C/W °C DIN IEC 747-6 tvj = 25°C tvj = 25°C 180° el sin F = , max 72/85 1,25 tq µs VGT IGT RthJC tvj max V mA °C/W °C DIN IEC 747-6 tvj = DIN IEC 747-6 tvj max (dv/dt)cr V/µs tvj = tvj = 180° 25°C 25°C el sin 200 E 20 B =


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ts26

Abstract: DIODE ED 11 T188F TS18 25G30
Text: (TO) V T ,= rT m Q Tv¡ = (di/dt) cr A /ps MS (d v /d t)cr V/|js DIN IEC 747-6 ! V gt V , T vj m a x DIN IEC 747-6 25°C 25°C 180° el sin 100V(50Hz) 1 1 u p to 80 ) V T 72 F , VT/ I T V /k A T v j max V (TO) rT (d i/d t)c A/| js DIN IEC 747-6 A kA 10 ms, T vj max V T ,= T v j max m fi Tvi `q MS (d v /d t)or V / ms DIN IEC 747-6 V gt Ig t , x T v jm a x Tv,= T vj m a x (di/dt) cr t lq 1) A / ms MS DIN IEC 747-6 400 D < 15 C <12 B


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PDF
T510S

Abstract: T691S
Text: Fast Thyristors Type V d rm V rrm V V d s m = ^ drm V r s m = V RRM continued/ Fortsetzung It r m s m l/TSM Schnelle Thyristoren V(TO) V{TO) V T /I t V/kA rT mw Tvj = T v max (di/dt)cr A/ps DIN IEC 747-6 MS (dv/dt)cr V/ps DINIEC 747-6 typ. V gt I gt R th J C T v j , Asymetrische Thyristoren (d i/d t)* O ps typ. (dv/dt)cr V/ps DIN IEC 747-6 V gt Ig t RthJC Tvj m ax °c outline A kA 10 ms Tvj max V/kA A/ps DIN IEC 747-6 V Tvj = 25°C mA


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PDF T510S T510S T691S
thyristor TT 46 N 1200

Abstract: thyristor tt 162 n 12 thyristor tt 142 n 12 thyristor TT 31 N 12 TD25N TT 93 N 08 thyristor TT 46 N 12 thyristor tt 425 thyristor TD 25 N PHASE CONTROL THYRISTOR MODULE TT 56 N
Text: tsm / i2dt IfA V M ^C V(TO) (di/dt)ci D IN IEC 747-6 A / j iS tq (dv/dt)C F D IN IEC 747-6 RlhJC R|hCK tv) max 10 ms, 10 ms, tvj max 180 °el sin. A /° C 'v, = , IN typ D IN IEC 747-6 IEC 747-6 V A /°C V A/|iS MS V/ns °c/w °C/W , V A t ., m a, 10 ms, 180 "el sin t»l = t,l V tv I = DIN IEC 747-6 A /|is typ DIN IEC 747-6 tv, ilia , 180 "el sm. V A k A 2s A /° C mQ (IS V/(JS °c/w


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PDF TD18N DT18N TD25N N2600 N1200 N2400* thyristor TT 46 N 1200 thyristor tt 162 n 12 thyristor tt 142 n 12 thyristor TT 31 N 12 TT 93 N 08 thyristor TT 46 N 12 thyristor tt 425 thyristor TD 25 N PHASE CONTROL THYRISTOR MODULE TT 56 N
Not Available

Abstract: No abstract text available
Text: sin tv¡ = ^vj max ^vj max ^vj max DIN IEC 747-6 72/85 1,25 1,8 200 V , IEC 747-6 200 2,05 21 B C* = L = 200 2,45 30 80/85 1,30 2,4 160 , V rsm = V rrm + lvj max tvj max 180° el sin ^vj max ^vj max DIN IEC 747-6 6.40 205 340/85 0,90 0,7 200 i i2dt tvj = MS DIN IEC 747-6 RthJC


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PDF DDQ217S
7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
Text: 54/ 7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK information is loaded into the master while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW Clock transition. The J and K inputs must be stable while the Clock is HIGH for conventional operation , operation. e. The J and K inputs of the 7476 and 74H76 must be stable while the Clock is HIGH for


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PDF 54H/74H76 54LS/74LS76 74H76 74LS76 7476 truth table 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
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