The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC2938HMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939IMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC2938HDE#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C

7476 pin configuration Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: 1LSul 10LSul PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 E ®D 1OE *01 GE , Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f HAX , Flip-Flops 7476 , LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , Table. 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , understood tobe40*iA l,H and-1.6mA l|L, and a74LS unit load (LSul) is20/uA lIH and -0.4mA l(L. PIN CONFIGURATION cp, [T 13 «i Soi Œ Do, »01 Œ 13 5, ■ME jUsno VccŒ j3k2 cpj [T mo2 SoîE ]Ã


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: l|H and -0 .4 m A lIL. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP , Sjgnetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: . PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEE/IEC) 76 LS76 CP, U 33*1 D o , 1J , Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 TYPICAL f MAx , 81501 Signetics Logic Products Product Specification Flip-Flops 7476 , LS76 LOGIC DIAGRAM


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: : PIN CONFIGURATION cp, [T 33*1 «di Œ Do, «oí E 5, JilZ ï3]qnd VccE cp2 (T mos SoîŠ, , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the , understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Flip-Flops 7476 , LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd


OCR Scan
PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
Text: €”1, > CP 6 —O >CP 16- Û -14 12 - K "O 0 -10 Vcc = Pin 5 GND = Pin 13 PIN CONFIGURATION CP, [T , 54/ 7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK , Information) PACKAGES PIN CONF. COMMERCIAL RANGES VCC = 5V ± 5%; TA = 0°C to *70°C MILITARY RANGES VCC = , operation. e. The J and K inputs of the 7476 and 74H76 must be stable while the Clock is HIGH for


OCR Scan
PDF 54H/74H76 54LS/74LS76 74H76 74LS76 7476 truth table 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
Text: N7476F PIN CONFIGURATION Flatpak S5476W [T H ]o , m q i INPUT AND OUTPUT LOADING AND , 54/ 7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK inform ation , PACKAGES PIN CONF. Fig A Fig A Fig A Fig A Fig A Fig A (See Section 9 for further Package and Ordering , V ± 1 0 % ; T a = - 5 5 ° C to *1 2 5 ° C V cc = Pin 5 GND = Pin 13 Plastic DIP N7476N ·


OCR Scan
PDF 54H/74H76 54LS/74LS76 74H76 74LS76 54H/74H 54S/74S 54LS/74LS logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
2007 - IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
Text: Analog Inputs and 2 Analog Outputs AUTOMATIONWORX Data Sheet 7476 _en_02 © PHOENIX CONTACT - 10/2007 , disregard of information contained in this data sheet. 7476 _en_02 PHOENIX CONTACT 2 ILB BT , 7476 _en_02 MODE 16 dBm 12 dBm 8 dBm 4 dBm 0 dBm DIP switches for setting the , antenna cable are available on request. 7476 _en_02 PHOENIX CONTACT 4 ILB BT ADIO 2/2/16/16 , : 1988-05 7476 _en_02 PHOENIX CONTACT 5 ILB BT ADIO 2/2/16/16 Ambient Conditions (Continued


Original
PDF Bm/39 IC 7476 INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
2011 - TS820600T

Abstract: TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
Text: Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820, TYN608 1 , 200 0.8 0.1 8 5 6 5 1.6 0.85 46 5 Unit µA V V V mA mA V/µs V V m µA 2/13 Doc ID 7476 Rev 7 , 6 IT(AV)(A) 1 0 0 25 Tcase(°C) 50 75 100 125 Doc ID 7476 Rev 7 3/13 , 1.5 Tj(°C) 1.0 0.5 0.0 1E-2 1E-1 RGK(k) 1E+0 1E+1 4/13 Doc ID 7476 Rev 7 TN805 , 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 S(cm²) 0 0 2 4 6 8 10 12 14 16 18 20 Doc ID 7476 Rev 7 5/13


Original
PDF TN805, TN815 TS820, TYN608 TS820-6d TS820600T TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
2011 - TS820 600T

Abstract: No abstract text available
Text: -220AB October 2011 X Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820 , 220 Ω Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 7 MAX. TN805, TN815, TS820, TYN608 , ) 0 0 0 1 2 3 4 5 6 0 Doc ID 7476 Rev 7 25 50 75 100 125 , Doc ID 7476 Rev 7 RGK(kΩ) 1E-1 1E+0 1E+1 TN805, TN815, TS820, TYN608 Figure 9 , ID 7476 Rev 7 2 4 6 8 10 12 14 16 18 20 5/13 Ordering information


Original
PDF TN805, TN815 TS820, TYN608 TS820-600H TN805-600B TN815-x00B TS820-600B TS820 600T
PIN CONFIGURATION 7476

Abstract: dc to dc chopper by thyristor DIODE D180 thyristor control ic with current sense thyristor thyristor bridge circuit Thyristor PIN CONFIGURATION Half-Controlled single phase bridge rectifier pin configuration
Text: solder pin flat base cable TO 220 case disc B C E F T 4.Letter maximum turn-off time 8 µs , after to DIN IEC turn-off: 747-6 : 50 V/µs 50 V/µs 500 V/µs 500 V/µs 1000 V/µs 1000 V/µs 500 V , pin flat-base cable press-pack FF 200 R 12 K F FF FZ FS dual version single version six , Module 100 current rating IC G technology: G = IGBT-technology B Configuration : A = single switch


Original
PDF
2526N

Abstract: signetics 2526 7476 truth table pin diagram of 7476 pin diagram of ttl 7476 PIN CONFIGURATION 7476 7x9 decoder 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram decoder 7476
Text: SILICON GATE MOS 2500 SERES PIN CONFIGURATION (Top View) n/l packages 1. Output 6 2. Output 7 3 , INPUTS • TTL/DTL COMPATIBLE TRI-STATE OUTPUTS • Vcc"+5V,Vgq = -12V • 24- PIN SILICONE DIP â , scan. PART IDENTIFICATION PART OP. TEMP. RANGE PACKAGE 2526N 0-70°C 24- Pin Silicone DIP 25261 0-70°C 24- Pin Ceramic DIP 88 SIGNETfCS 64 X 9 X 9 ROM STATIC CHARACTER GENERATOR ■2526 MAXIMUM , . The 9x9 dot configuration for each character allows the 2526 to be used as a 7x9 character generator


OCR Scan
PDF 184-bit 64x9x9 512x9 2526N signetics 2526 7476 truth table pin diagram of 7476 pin diagram of ttl 7476 PIN CONFIGURATION 7476 7x9 decoder 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram decoder 7476
2010 - TYN608

Abstract: TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Text: ID 7476 Rev 6 X 1/12 www.st.com 12 Characteristics TN805, TN815, TS820, TYN608 , VRRM, RGK = 220 Tj = 25 °C Tj = 125 °C Doc ID 7476 Rev 6 MAX. TN805, TN815, TS820 , ID 7476 Rev 6 25 50 75 100 125 3/12 Characteristics Figure 3. TN805 , ) 0.5 0.0 60 80 100 120 140 0.0 1E-2 Doc ID 7476 Rev 6 1E-1 1E+0 1E+1 , 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 Doc ID 7476 Rev 6 2 4 6 8


Original
PDF TN805, TN815, TS820 TYN608, TYN808, TYN1008 TN805-xxxB TN815-xxxB TS820-xxxB TN805-xxxH TYN608 TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
7476 truth table

Abstract: No abstract text available
Text: 2526-N,! DESCRIPTION PIN CONFIGURATION The 2526 is a high speed 5 184-bit Static Read-Only Memory. It may be organized as 64x9x9 tor use as a character generator, or as a 512x9 ROM tor general purpose use. This device has TTL compatible inputs and outputs and requires+5V and -12 V power supplies , € Blank Name 2 Data Cards Card No. 1 Column 1-9 10 11-19 20 21-29 73 74-76 77 , 11-19 20-70 71 72 73 74-76 77 78-80 Information Binary outputs of rows 9 through 1, (MSB at


OCR Scan
PDF 2526-N, 184-bit 64x9x9 512x9 0I0I00I0I 0I00I0T0T NQISM3AN03 S33dWVX3 N-92Se 7476 truth table
co-600v

Abstract: CO-624VD 12KHZ CO-624V-D CO624V
Text: of the 3048A. The equivalent sideband level of the integrated phase noise was ­ 74.76 dBc. Per the , to degrees: X 74.76 dB Equivalent sideband level or the integrated phase noise X , degrees 13 RMS jitter in seconds The sideband level of ­ 74.76 dBc for the integration of the


Original
PDF CO-600V 12KHz CO-624V-D CO-624VD CO-624V-D CO624V
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2 , / 4009 / 4049 / 4069 4012 4082 4025 4068 4071 7448 / 4056 / 4511 7447 / 4056 / 4511 7476 / 4027 , / 4015 74161 / 74164 / 4014 4052 7490 / 74390 / 4510 4518 4094 7410 7427 4033 7473 / 7476 , 4018 4516 Latches and Flip-Flops Device 7473 7474 7476 74175 74273 74279 74373 74374 , Flip-Flop Similar Devices 7476 / 4027 74175 / 74273 / 4013 / 40174 7473 / 4027 7474 / 74273 / 4013


Original
PDF
1996 - cr 6850 t

Abstract: T 698 DIN 1445 l 0380 T188F
Text: typ. tvj max 747-6 DIN IEC 747-6 tvj = 25°C tvj = 25°C 180° el sin 2,60 F = , tvj max 747-6 max *10³ 24 2880 1200/85 1,05 0,185 200 280 (dv/dt)cr V/µs VGT V IGT mA RthJC tvj max °C/W °C DIN IEC 747-6 tvj = 25°C tvj = 25°C 180° el sin F = , max 72/85 1,25 tq µs VGT IGT RthJC tvj max V mA °C/W °C DIN IEC 747-6 tvj = DIN IEC 747-6 tvj max (dv/dt)cr V/µs tvj = tvj = 180° 25°C 25°C el sin 200 E 20 B =


Original
PDF
IC 7476

Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
Text: FAIRCHILD TTL/SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks. Inputs to the master section are controlled by the clock , FAIRCHILD TTL/SSI • 9N76/5476, 7476 RECOMMENDED OPERATING CONDITIONS PARAMETER 9N76XM/5476XM 9N76XC , MAX- V|N = OV 51 -18 -57 mA 9N76/ 7476 'CC Supply Current 20 40 mA Vcc = MU- 49 SWITCHING


OCR Scan
PDF 9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
ts26

Abstract: DIODE ED 11 T188F TS18 25G30
Text: (TO) V T ,= rT m Q Tv¡ = (di/dt) cr A /ps MS (d v /d t)cr V/|js DIN IEC 747-6 ! V gt V , T vj m a x DIN IEC 747-6 25°C 25°C 180° el sin 100V(50Hz) 1 1 u p to 80 ) V T 72 F , VT/ I T V /k A T v j max V (TO) rT (d i/d t)c A/| js DIN IEC 747-6 A kA 10 ms, T vj max V T ,= T v j max m fi Tvi `q MS (d v /d t)or V / ms DIN IEC 747-6 V gt Ig t , x T v jm a x Tv,= T vj m a x (di/dt) cr t lq 1) A / ms MS DIN IEC 747-6 400 D < 15 C <12 B


OCR Scan
PDF
T510S

Abstract: T691S
Text: Fast Thyristors Type V d rm V rrm V V d s m = ^ drm V r s m = V RRM continued/ Fortsetzung It r m s m l/TSM Schnelle Thyristoren V(TO) V{TO) V T /I t V/kA rT mw Tvj = T v max (di/dt)cr A/ps DIN IEC 747-6 MS (dv/dt)cr V/ps DINIEC 747-6 typ. V gt I gt R th J C T v j , Asymetrische Thyristoren (d i/d t)* O ps typ. (dv/dt)cr V/ps DIN IEC 747-6 V gt Ig t RthJC Tvj m ax °c outline A kA 10 ms Tvj max V/kA A/ps DIN IEC 747-6 V Tvj = 25°C mA


OCR Scan
PDF T510S T510S T691S
thyristor TT 46 N 1200

Abstract: thyristor tt 162 n 12 thyristor tt 142 n 12 thyristor TT 31 N 12 TD25N TT 93 N 08 thyristor TT 46 N 12 thyristor tt 425 thyristor TD 25 N PHASE CONTROL THYRISTOR MODULE TT 56 N
Text: tsm / i2dt IfA V M ^C V(TO) (di/dt)ci D IN IEC 747-6 A / j iS tq (dv/dt)C F D IN IEC 747-6 RlhJC R|hCK tv) max 10 ms, 10 ms, tvj max 180 °el sin. A /° C 'v, = , IN typ D IN IEC 747-6 IEC 747-6 V A /°C V A/|iS MS V/ns °c/w °C/W , V A t ., m a, 10 ms, 180 "el sin t»l = t,l V tv I = DIN IEC 747-6 A /|is typ DIN IEC 747-6 tv, ilia , 180 "el sm. V A k A 2s A /° C mQ (IS V/(JS °c/w


OCR Scan
PDF TD18N DT18N TD25N N2600 N1200 N2400* thyristor TT 46 N 1200 thyristor tt 162 n 12 thyristor tt 142 n 12 thyristor TT 31 N 12 TT 93 N 08 thyristor TT 46 N 12 thyristor tt 425 thyristor TD 25 N PHASE CONTROL THYRISTOR MODULE TT 56 N
Not Available

Abstract: No abstract text available
Text: sin tv¡ = ^vj max ^vj max ^vj max DIN IEC 747-6 72/85 1,25 1,8 200 V , IEC 747-6 200 2,05 21 B C* = L = 200 2,45 30 80/85 1,30 2,4 160 , V rsm = V rrm + lvj max tvj max 180° el sin ^vj max ^vj max DIN IEC 747-6 6.40 205 340/85 0,90 0,7 200 i i2dt tvj = MS DIN IEC 747-6 RthJC


OCR Scan
PDF DDQ217S
TS2422

Abstract: GS12 TS20 TS22 TS24 TS27 T510S
Text: (dv/dt)cr V/µs DINIEC 747-6 VGT V Tvj = 25°C IGT mA Tvj = 25°C RthJC Tvj max outline , ,0160 = B or C 120 125 120 TS26 TS26 GS12 747-6 T 600 F T 1052 S tq µs typ , . DIN IEC Tvj = Tvj = 180° el 747-6 25°C 25°C sin C = 500 F = 1000 2,7 , ) 10 ms Tvj max tp = 1 µs Tvj max Tvj max IEC 1,3/2 747-6 400 A 158 S


Original
PDF
T308

Abstract: T930S C122B T188F
Text: Fast Thyristors Type VDRM 'trmsm Itsm Í i2dt ITAVM^C V(TO) It (di/dt)cr tq (dv/dt) cr VGT Igt RthJC tvj max outline VRRM V A kA A2s A/°C V mil A/ps MS V/|js V mA °C/W °c VDSM=VDRM, 10 ms, 10ms, 180° el 747-6 747-6 25°C 25°C el sin 100 V *103 T 72 F 200. 800 200 2,05 , + tv, max fvj max sin tyj max ^vj max 747-6 747-6 25°C 25°C el sin 100 V T 340 F


OCR Scan
PDF F4/61 0QQ2175 000517b T308 T930S C122B T188F
1999 - TT46N

Abstract: No abstract text available
Text: /dt = 0,75 A/µs, tg = 20 tvj = tvj max vD = VDRM , vR = VRRM DIN IEC 747-6 , tvj = 25°C iGM = 0,75 , , tp = 10 ms tvj = 25°C, tp = 10 ms tvj = tvj max , tp = 10 ms DIN IEC 747-6 , f = 50 Hz, vL = 10 V , / 1300V on demand Werte nach DIN IEC 747-6 (ohne vorrausgehende Kommutierung). / Values to DIN IEC 747-6


Original
PDF
Supplyframe Tracking Pixel