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Part Manufacturer Description Datasheet Download Buy Part
LT3466EDD#TR Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3466EDD#PBF Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3466EDD Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3466EDD#TRPBF Linear Technology LT3466 - Dual Full Function White LED Step-Up Converter with Built-In Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3497EDDB#TRMPBF Linear Technology LT3497 - Dual Full Function White LED Driver with Integrated Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
LT3497EDDB#PBF Linear Technology LT3497 - Dual Full Function White LED Driver with Integrated Schottky Diodes; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C

7476 FUNCTION TABLE Datasheets Context Search

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pin diagram of 7476

Abstract: 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out 74LS76 flip-flop 74ls76 7476 PIN DIAGRAM input and output
Text: the outputs to the steady state levels as shown in the Function Table . TYPE 7476 74LS76 TYPICAL f HAX , Flip-Flops 7476 , LS76 LOGIC DIAGRAM FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set , Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is , LOADING AND FAN-OUT TABLE PINS CP Rd> Sd J, K Q, Q NOTE: Where a 74 unit load (ul) is understood to be


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 FUNCTION TABLE 7476 7476 PIN DIAGRAM Jk 74ls76 pin out flip-flop 74ls76 7476 PIN DIAGRAM input and output
ci 7476

Abstract: 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
Text: override the Clock and Data inputs, forcing the outputs to the steady state levels as shown in the Function Table . 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = , DIAGRAM cp ldoz800s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS So RD CRP) J K Q Q , , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the


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PDF 74LS76 1N916, 1N3064, 500ris 500ns ci 7476 7476 PIN DIAGRAM pin diagram of 7476 jk flip flop 7476 pin diagram of ttl 7476 7476 7476 PIN DIAGRAM input and output 7476 ttl 7476 J-K Flip-Flop LS 7476
PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Text: , forcing the outputs to the steady state levels as shown in the Function Table . TYPE 7476 74LS76 TYPICAL f , , LS76 LOGIC DIAGRAM S 0 - y xC " Q K - -J CP LD0280GS FUNCTION TABLE INPUTS , Sjgnetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , AND OUTPUT LOADING AND FAN-OUT TABLE PINS CP R d. S q J, K DESCRIPTION Clock input Reset and Set


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PDF 74LS76 1N916, 1N3064, 500ns 500ns PIN CONFIGURATION 7476 pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
pin diagram of 7476

Abstract: PIN CONFIGURATION 7476 74LS76 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Text: the outputs to the steady state levels as shown in the Function Table . TYPE 7476 74LS76 TYPICAL f MAx , CP FUNCTION TABLE INPUTS OPERATING MODE SD Asynchronous set Asynchronous reset (Clear , Signetics 7476 , LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , LOADING AND FAN-OUT TABLE PINS CP Ro. So J, K Q, a DESCRIPTION Clock input Reset and Set inputs Data


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PDF 74LS76 1N916, 1N3064, 500ns 500ns pin diagram of 7476 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output 7476 FUNCTION TABLE Jk 74ls76 pin out 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
Text: Flip-Flops 7476 , LS76 LOGIC DIAGRAM ld02900s FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD Rd , TABLE chronous active LOW inputs. When LOW, they override the Clock and Data inputs, forcing the outputs to the steady state levels as shown in the Function Table . Where a 74 unit load (ul) is understood to be 40>iA l,H and -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476 , , Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the


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PDF 74LS76 1N916, 1N3064, 500ns jk flip flop 7476 7476 PIN DIAGRAM 7476 7476 ttl TTL 74ls76 7476 PIN DIAGRAM input and output pin diagram of 7476 PIN CONFIGURATION 7476 pin diagram of ttl 7476 7476 J-K Flip-Flop
2007 - IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
Text: Analog Inputs and 2 Analog Outputs AUTOMATIONWORX Data Sheet 7476 _en_02 © PHOENIX CONTACT - 10/2007 , can be downloaded at www.download.phoenixcontact.com. A conversion table is available on the Internet , disregard of information contained in this data sheet. 7476 _en_02 PHOENIX CONTACT 2 ILB BT , 7476 _en_02 MODE 16 dBm 12 dBm 8 dBm 4 dBm 0 dBm DIP switches for setting the , antenna cable are available on request. 7476 _en_02 PHOENIX CONTACT 4 ILB BT ADIO 2/2/16/16


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PDF Bm/39 IC 7476 INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 circuit diagram with IC 7476 assignment on bluetooth 7476 IC 7476 Connection diagram PVH071902 of IC 7476 in file
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2 , device number to see the table of devices that belong to the same group. Device 7400 7402 7403 , / 4009 / 4049 / 4069 4012 4082 4025 4068 4071 7448 / 4056 / 4511 7447 / 4056 / 4511 7476 / 4027 , Device Summary Please click on a device number to see the table of devices that belong to the same group , 4022 4023 4024 4025 4026 4027 4028 4029 4030 4033 4035 4 of 12 Function Quad 2


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2011 - TS820600T

Abstract: TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
Text: 7476 Rev 7 TN805, TN815, TS820, TYN608 Table 8. TO-220AB dimensions (for TS820-xxxT) Package , Table 5. Added TO-220FPAB package. Removed 700 V and 1000 V products. Changes 12/13 Doc ID 7476 , -600FP Table 1. Device summary Voltage (x00) VDRM/VRRM Sensitivity IGT 0.2 mA 0.2 mA 0.2 mA 0.2 mA 5 mA X , Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820, TYN608 1 Table 2. Characteristics Absolute ratings (limiting values) Value Symbol Parameter TN805


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PDF TN805, TN815 TS820, TYN608 TS820-6d TS820600T TYN608RG TS820-600B TS8206 TS820-600BTR TS820-600T TS820-600 TYN608 scr TYN608 ts820600b
2011 - TS820 600T

Abstract: No abstract text available
Text: ID 7476 Rev 7 7/13 Package information TN805, TN815, TS820, TYN608 Table 7. IPAK , -600T K A G TO-220FPAB TS820-600FP Table 1. Device summary Order code Voltage (x00 , -220AB October 2011 X Doc ID 7476 Rev 7 1/13 www.st.com 13 Characteristics TN805, TN815, TS820, TYN608 1 Characteristics Table 2. Absolute ratings (limiting values) Value Symbol , to + 125 °C 5 V I2t PG(AV) Tstg Tj VRGM Table 3. Average gate power


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PDF TN805, TN815 TS820, TYN608 TS820-600H TN805-600B TN815-x00B TS820-600B TS820 600T
2010 - TYN608

Abstract: TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
Text: to case, updated in Table 5. Last update. Doc ID 7476 Rev 6 11/12 TN805, TN815, TS820 , in a limited space. Table 1. K Device summary Voltage (xxx) VDRM/VRRM Sensitivity Order , ID 7476 Rev 6 X 1/12 www.st.com 12 Characteristics TN805, TN815, TS820, TYN608, TYN808, TYN1008 1 Characteristics Table 2. Absolute ratings (limiting values) Value , Table 3. Average gate power dissipation Storage junction temperature range Operating junction


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PDF TN805, TN815, TS820 TYN608, TYN808, TYN1008 TN805-xxxB TN815-xxxB TS820-xxxB TN805-xxxH TYN608 TYN808 SCR 600V, 8A, 15mA Igt 7476 TN805 TN815 TS820 TYN08 TYN1008
co-600v

Abstract: CO-624VD 12KHZ CO-624V-D CO624V
Text: System. The phase noise was then integrated from 12 kHz to 20 MHz using the Trace Integration function of the 3048A. The equivalent sideband level of the integrated phase noise was ­ 74.76 dBc. Per the , to degrees: X 74.76 dB Equivalent sideband level or the integrated phase noise X , degrees 13 RMS jitter in seconds The sideband level of ­ 74.76 dBc for the integration of the


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PDF CO-600V 12KHz CO-624V-D CO-624VD CO-624V-D CO624V
7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
Text: 54/ 7476 54H/74H76 54LS/74LS76 LOGIC SYMBOL DESCRIPTION The "76" is a DualJK Flip-Flop with individual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK , levels as shown in the Truth Table . ORDERING CODE (See Section 9 for further Package and Ordering , €¢ S54H76W S54LS76W INPUT AND OUTPUT LOADING AND FAN-OUT TABLE (a) PINS 54/74 54H/74H 54S/74S 54LS/74LS CP , TABLE CP OPERATING MODE INPUTS OUTPUTS ®D rD CP(d) j K Q Q Asynchronous Set L H X X X H L


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PDF 54H/74H76 54LS/74LS76 74H76 74LS76 7476 truth table 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM pin diagram of 7476 7476 PIN DIAGRAM input and output S5476F PIN CONFIGURATION 7476 7476 pin configuration 7476
IC 7476

Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
Text: FAIRCHILD TTL/SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate , level Clear and preset are independent of clock TRUTH TABLE t n tn+1 J K Q L L On L H L H L H H H Qn , FAIRCHILD TTL/SSI • 9N76/5476, 7476 RECOMMENDED OPERATING CONDITIONS PARAMETER 9N76XM/5476XM 9N76XC , MAX- V|N = OV 51 -18 -57 mA 9N76/ 7476 'CC Supply Current 20 40 mA Vcc = MU- 49 SWITCHING


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PDF 9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
Text: 54/ 7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76'' is a Dual JK Flip-Flop w ith individ ual J, K, Clock, Set and Reset inputs. The 7476 and 74H76 are positive pulse triggered flip-flops. JK inform ation , levels as shown in the Truth Table . LOGIC SYMBOL 2 7 4- J SD Q -15 9 , FAN-OUT TABLE (a) PINS CP Rd Sd JK Clock input Reset input Set input Data inputs IlH 1/iAI Iil (mAI IlH , FLIP-FLOP LOGIC DIAGRAM MODE SELECT- TRUTH TABLE OPERATING MODE ®D Asynchronous Set Asynchronous


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PDF 54H/74H76 54LS/74LS76 74H76 74LS76 54H/74H 54S/74S 54LS/74LS logic ic 7476 pin diagram and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
1999 - TT46N

Abstract: No abstract text available
Text: /dt = 0,75 A/µs, tg = 20 tvj = tvj max vD = VDRM , vR = VRRM DIN IEC 747-6 , tvj = 25°C iGM = 0,75 , , tp = 10 ms tvj = 25°C, tp = 10 ms tvj = tvj max , tp = 10 ms DIN IEC 747-6 , f = 50 Hz, vL = 10 V , / 1300V on demand Werte nach DIN IEC 747-6 (ohne vorrausgehende Kommutierung). / Values to DIN IEC 747-6 , Analytische Funktion / Analytical function : 120 25 80 10 40 5 0 TT 46 N/1 40 80 120


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500 Series VCXO

Abstract: VC-400 XO-400 applications vectron xo jduglmep jduglmep15552 vectron CO-400
Text: requiring a PECL or ECL VCXO having X:=- 74.76 dB Equivalent sideband level or an RMS jitter of < 1.0 ps , kHz to 20 MHz using the Trace peak to peak. Integration function of the 3048A. The equivalent sideband level of the integrated phase noise was - 74.76 The sideband level of - 74.76 dBc for the , 12 kHz to 20 MHz using the Trace Integration function of the 3048A. The equivalent sideband level of , the Trace Integration function of the 3048A. The equivalent sideband level of the integrated phase


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PDF VCO600A/VS500 50kHz inteVCO600A/VS500 Jrms/360 Jrms/360) XO400 1-88-VECTRON-1 500 Series VCXO VC-400 XO-400 applications vectron xo jduglmep jduglmep15552 vectron CO-400
1999 - tt46n

Abstract: No abstract text available
Text: tvj = 25°C, tp = 10 ms tvj = tvj max , tp = 10 ms DIN IEC 747-6 , f = 50 Hz, vL = 10 V IGM = 0,75 A , IEC 747-6 , tvj = 25°C iGM = 0,75 A, diG/dt = 0,75 A/µs tvj = tvj max , iTM = ITAVM vRM = 100 V, vDM = , demand Werte nach DIN IEC 747-6 (ohne vorrausgehende Kommutierung). / Values to DIN IEC 747-6 (without , Funktion / Analytical function : 25 10 5 40 80 120 160 -diT/dt [A/µs] 200 nmax ZthJC = n=1 R t


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2000 - Not Available

Abstract: No abstract text available
Text: max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A/µs Kritische Spannungssteilheit , currents T vj = Tvj max Zündverzug gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 (without prior commutation). 2) Unmittelbar nach der Freiwerdezeit , Analytische Funktion / analytical function : ZthJC = Rthn ( 1 - EXP ( - t / n ) n=1 SZ-M


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2000 - thyristor fast

Abstract: No abstract text available
Text: (diT/dt)cr 200 A/µs T vj = Tvj max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A , gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 , ,0169 0,005 2,8 0,0128 0,0117 36 n max Analytische Funktion / analytical function : ZthJC


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2000 - Not Available

Abstract: No abstract text available
Text: (diT/dt)cr 200 A/µs T vj = Tvj max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A , gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 , ,0169 0,005 2,8 0,0128 0,0117 36 n max Analytische Funktion / analytical function : ZthJC


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2000 - Not Available

Abstract: No abstract text available
Text: max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A/µs Kritische Spannungssteilheit , currents T vj = Tvj max Zündverzug gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 (without prior commutation). 2) Unmittelbar nach der Freiwerdezeit , Analytische Funktion / analytical function : ZthJC = Rthn ( 1 - EXP ( - t / n ) n=1 SZ-M


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2000 - Not Available

Abstract: No abstract text available
Text: (diT/dt)cr 200 A/µs T vj = Tvj max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A , gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 , ,0169 0,005 2,8 0,0128 0,0117 36 n max Analytische Funktion / analytical function : ZthJC


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2000 - Not Available

Abstract: No abstract text available
Text: (diT/dt)cr 200 A/µs T vj = Tvj max, tp = 10ms DIN IEC 747-6 f=50 Hz, iGM = 1 A diG/dt = 1 A , gate controlled delay time DIN IEC 747-6 vD = VDRM, vR = VRRM T vj = 25°C iGM = 1 A, diG/dt = 1 A/µs 1) Werte nach DIN IEC 747-6 (ohne vorausgehende Kommutierung). / Values to DIN IEC 747-6 , ,0169 0,005 2,8 0,0128 0,0117 36 n max Analytische Funktion / analytical function : ZthJC


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Not Available

Abstract: No abstract text available
Text: °C, t p = 10 ms tvj = t vj max , tp = 10 ms critical rate of rise of on-state currentDIN IEC 747-6 , f , currentsvj = t vj max t vD = V DRM, vR = V RRM Zündverzug gate controlled delay time DIN IEC 747-6 , t vj , IEC 747-6 (ohne vorausgehende Kommutierung) / Values according to DIN IEC 747-6 (without prior , ,00824 0,108 0,57 3 Analytische Funktion / Analytical function : 0.6 0.2 0.1 0.06


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1999 - F1035

Abstract: No abstract text available
Text: °C, t p = 10 ms tvj = t vj max , tp = 10 ms critical rate of rise of on-state currentDIN IEC 747-6 , f , currentsvj = t vj max t vD = V DRM, vR = V RRM Zündverzug gate controlled delay time DIN IEC 747-6 , t vj , IEC 747-6 (ohne vorausgehende Kommutierung) / Values according to DIN IEC 747-6 (without prior , ,00824 0,108 0,57 3 Analytische Funktion / Analytical function : 0.6 0.2 0.1 0.06


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