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LTC1540CS8#PBF Linear Technology LTC1540 - Nanopower Comparator with Reference; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LTC1558CS8-3.3#TRPBF Linear Technology LTC1558 - Backup Battery Controller with Programmable Output; Package: SO; Pins: 8; Temperature: Commercial
LTC1540CS8 Linear Technology LTC1540 - Nanopower Comparator with Reference; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LTC6703IDC-3#PBF Linear Technology LT6703 - Micropower, Low Voltage Comparator with 400mV Reference; Package: DFN; Pins: 3; Temperature: Industrial
LTC2915HTS8-1#TRA1PBF Linear Technology LTC2915 - Voltage Supervisor with 27 Selectable Thresholds; Package: SOT; Pins: 8; Temperature: High
LTC1540CS8#TRPBF Linear Technology LTC1540 - Nanopower Comparator with Reference; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C

74164 with ic PIN DIAGRAM Datasheets Context Search

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IC 74164

Abstract: 74164 with ic PIN DIAGRAM pin diagram of ic 74164 ic 74ls164 AND SPECIFICATIONS 74164 truth table 74164 shift register IC LS164 and pin diagram of IC 74164 74164 14 PIN DIAGRAM IC 74164 PIN DIAGRAM
Text: Registers 74164 , LS164 LOGIC DIAGRAM '" = C H _C>fl MR <·) - c £ > 0 - j- >F IS) |°K J_ 3 i , Specification 74164 , Logic Products FEATURES · · · · Gated serial Data inputs Typical shift frequency of 36MHz Asynchronous Master Reset Fully buffered Clock and Data inputs TYPE 74164 74LS164 TYPICAL f , with serial data entry and an output from each of the eight stages. Data is entered serially through , (LSul) DESCRIPTION Inputs Outputs 74 1ul 5ul 74LS 1LSul 10LSul PIN CONFIGURATION LOGIC


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PDF 36MHz 74LS164 36MHz 1N916, 1N3064, 500ns 500ns IC 74164 74164 with ic PIN DIAGRAM pin diagram of ic 74164 ic 74ls164 AND SPECIFICATIONS 74164 truth table 74164 shift register IC LS164 and pin diagram of IC 74164 74164 14 PIN DIAGRAM IC 74164 PIN DIAGRAM
74164 with ic PIN DIAGRAM

Abstract: IC 74164 LS164 ic 74ls164 AND SPECIFICATIONS pin diagram of ic 74164
Text: Specification Shift Registers 74164 , LS164 LOGIC DIAGRAM INPUTS OPERATING MODE MR Reset (clear) L H , Asynchronous Master Reset Fully buffered Clock and Data inputs TYPE 74164 74LS164 TYPICAL fMAx 36MHz 36MHz , -bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered , _, and a 74LS unit load (LSul) is 20/iA lIH and -0.4m A l|i_. PIN CONFIGURATION LOGIC SYMBOL , ) cp 7 II II II II 9 3 4 5 6 10 11 1 2 13 L S 0 4 0 4 0 S C O Ô 4 T O O S Vcc = Pin 14


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PDF LS164 36MHz 74LS164 36MHz LS164 1N916, 1N3064, 500ns 74164 with ic PIN DIAGRAM IC 74164 ic 74ls164 AND SPECIFICATIONS pin diagram of ic 74164
74164 truth table

Abstract: LS164 74164 two 74164 74LS164 N74164N ttl 74164 74164 14 PIN DIAGRAM 74LS 74164 SIGNETICS
Text: Shift Registers 74164 , LS164 LOGIC DIAGRAM <2» ft-l I -<£>0- pK ft pK jO'R jT"d Ml (5 , 164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the , all other inputs and clears the register asynchronously, forcing all outputs LOW. 74164 , LSI64 Shift , CURRENT TYPE (TOTAL) 74164 36MHz 37mA 74LS164 36MHz 16mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc , |L> and a 74LS unit load (LSul) is 20pA l|H and -0.4mA l|L. PIN CONFIGURATION LOGIC SYMBOL LOGIC


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PDF 36MHz 1N916, 1N3064, 500ns 74164 truth table LS164 74164 two 74164 74LS164 N74164N ttl 74164 74164 14 PIN DIAGRAM 74LS 74164 SIGNETICS
ttl 74164

Abstract: 74164 14 PIN DIAGRAM two 74164 74164 74LS164 af02000s 74164 ttl 74LS 74164 equivalent N74164N
Text: Signetics Logic Products Product Specification Shift Registers 74164 , LS 164 LOGIC DIAGRAM <•»> 0â , Signetics 74164 , 13164 Shift Registers 8-Bit Serial-ln Parallel-Out Shift Register Product , -bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered , (TOTAL) 74164 36MHz 37mA 74LS164 36MHz 16mA ORDERING CODE PACKAGES COMMERCIAL RANGE Vcc = 5V ±5%; TA , unit load (LSul) is 20mA l|H and -0.4mA l|i_. PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC


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PDF 36MHz 1N916, 1N3064, 500ns ttl 74164 74164 14 PIN DIAGRAM two 74164 74164 74LS164 af02000s 74164 ttl 74LS 74164 equivalent N74164N
74164 14 PIN DIAGRAM

Abstract: 74164 truth table 74164 ttl 74164 74164 ttl two 74164 msi 74164 93164 54164 ScansUX986
Text: TTL/MSI 93164/54164, 74164 8-BIT SERIAL TO PARALLEL CONVERTER • 1 BE ANNOUNCED description - The 93164/54164, 74164 are 8-Bit Shift Registers with gated serial inputs and an asynchronous clear facility , present one TTL load. pin names CP C|_ A, B QA to Oh 1 Unit Load (U.L.) Clock Pulse Input Clear Input , serial inputs a and b INPUTS OUTPUT AT tn AT tn+1 A B" Qa H H H L H L H L L L L L logic diagram OUTPUT Qa , symbol 1 CP CL 93164/54164, 74164 QA QB QC OD QE QF QG QH 1 1 1 1 1 3 4 5 6 10 11 12 13 Vcc =


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ic 74ls164 AND SPECIFICATIONS

Abstract: IC 74164 74LS164M 54164
Text: .5 3.2 2,4 SN 74164 U N IT TYP* M AX V 0 .8 - 1 .5 3 .2 V V V V ql. l| l|H l|t_ *O S IC C , Inputs Asynchronous Clear T Y P IC A L TYPE M A X IM U M Ç LO C K FR EQ U EN CY '164 'L S 1 6 4 36 MH2 3 6 MHz T Y P IC A L P O W E R D I S S IP A T IO N 21 m W per bit 10 m W per bit SN54164, SN54LS164 . J P A C K A G E SN 74164 . N P A C K A G E SN 74LS 16 4. D O R N P A C K A G E (TOP VIEW) C 1 U , of - 5 5 ° C to 125°C. The SN 74164 and SN 74LS164 are characterized for operation from 0°C to 70


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PDF SN74164, SN74LS164, SN54164, SN54LS164 SN54LS164 LS164, ic 74ls164 AND SPECIFICATIONS IC 74164 74LS164M 54164
1998 - 74164

Abstract: MDIO MDC 74164 ttl A116 REG08 mdc 171
Text: Manager 13 5.6 LED Interface 13 6.1 Pin Diagram (MII Interface) 15 6.2 Pin Diagram (RMII Interface) 16 7.1 Pin Description (MII Interface) 17 7.2 Pin Description , display per port buffer status and LINK with RX flash. · Use three 74164 to display per port buffer , ] RXDATA5[1] 6.1 Pin Diagram (MII Interface) 157 158 159 160 161 162 163 164 165 166 167 , STRPHYID unused TXEN6 TXDATA6[0] TXDATA6[1] NC NC GND unused unused RXDATA5[1] 6.2 Pin Diagram


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PDF WCT0006 WCT-300-SP-002 74164 MDIO MDC 74164 ttl A116 REG08 mdc 171
1998 - two 74164

Abstract: 8-Port Fast Ethernet Switch Ethernet Switch Controller 74164 74164 14 PIN DIAGRAM 74164 ttl A116 Fast Ethernet Switch Controller
Text: Manager 13 5.6 LED Interface 13 6.1 Pin Diagram (MII Interface) 15 6.2 Pin Diagram (RMII Interface) 16 7.1 Pin Description (MII Interface) 17 7.2 Pin Description , display per port buffer status and LINK with RX flash. · Use three 74164 to display per port buffer , -300-SP-001 Rev.00 6/2/1999 TM WCT0008 8-Port Fast Ethernet Switch Controller 6. Pin Diagram 6.1 Pin , STRPHYID unused TXEN6 TXDATA6[0] TXDATA6[1] NC NC GND unused unused RXDATA5[1] 6.2 Pin Diagram


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PDF WCT0008 WCT-300-SP-001 two 74164 8-Port Fast Ethernet Switch Ethernet Switch Controller 74164 74164 14 PIN DIAGRAM 74164 ttl A116 Fast Ethernet Switch Controller
CI 7474

Abstract: pin diagram 7400 series hs 111-0 7400 fan-out 7474 pin out diagram TTL CI 7400 74164 CI 7400 HS5212 HS5215
Text: with a 1 MHz clock. HS 5210 Series hybrid microcircuit converters are housed in hermetically-sealed 24- pin , .670 mW, Typical ■Wide Operating Temperature Range. -55°C to + 125°C ■Small Size.24- Pin , . The HS 5210 Series provides the user with the best possible performance in systems requiring maximum , user has the option of specifying a model complete with an internal reference or for improved absolute , operation over the - 55°C to + 125°C military temperature range ("B" models) with the same operating


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PDF 12-Bit 24-Pin, MIL-STD-883 24-pin o11-o11- HS52XXC HS52XXB 12-Bits CI 7474 pin diagram 7400 series hs 111-0 7400 fan-out 7474 pin out diagram TTL CI 7400 74164 CI 7400 HS5212 HS5215
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the , 74138 74139 74154 74157 74161 74163 74161 74164 74175 74193 74221 74240 74241 74244 74245 , 4514 7493 / 74163 / 74193 / 74393 / 4029 7493 / 74161 / 74193 / 74393 / 4029 74164 / 4014 / 4015 , / 4049 / 4069 7400 / 7403 / 74132 / 4093 / 40107 7420 7474 / 74175 / 74273 / 40174 74161 / 74164 / 4015 74161 / 74164 / 4014 4052 7490 / 74390 / 4510 4518 4094 7410 7427 4033 7473 / 7476


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IC 74164

Abstract: 54164 3624m sn54164 74LS164 74LS164M
Text: REGISTERS logic diagram INSTRUMENTS POST O F F IC E BOX 225012 · D A L L A S T E X A S 7E>265 3 , Serial Inputs Asynchronous Clear T Y P IC A L " TY P E '1 6 4 'L 1 6 4 'L S 1 6 4 SN 54 164, S N 54LS 16 4 . . . J OR W PACKAGE SN 54L1 64 . . . J PACKAGE SN 74164 . . . J OR N PACKAGE S N 74LS 16 4 . , military tem perature range of - 5 5 °C to 1 2 5 °C . The SN 74164 and S N 7 4 L S 1 6 4 are , - q H 0 = t h e ,e v e l o f q A - q B- o r q H - r e s p e c t iv e ly , b e f o r e t h e in d ic


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PDF SN54164, SN54L164, SN54LS164, SN74164, SN74LS164 IC 74164 54164 3624m sn54164 74LS164 74LS164M
IC 74164

Abstract: 74164 SESCOSEM SN74164 ELEKTOR DSAGER00060
Text: SN 74164 5 V 8 -B IT -S C H IE B E R E G IS T E R o I 14 I H aus 113 I I 12 I Gaus Faus I 11 1 110 I -aus Reset Takt elektor IC -K artei © Serielle Eingabe: A e in, Bein Parallele Ausgabe: A aUs · . .H aus Reset = " 1 " : Register ist betriebsbereit Bei Bein = " 1 " w ird die Eingangsinform ation an A e in m it der nächsten positiven T a k tim p u lsfla n , : N 74164 : S F .C 4 1 6 4 A J ü J J iä lJ lT lJ iö U T l. r · CM 0 0 1 1 0, a


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54164

Abstract: IC 74164
Text: PACKAGE · Fully Buffered Clock and Serial Inputs · Asynchronous Clear T Y P IC A L TYPE M A X IM U M CLOCK FREQ UENCY '1 6 4 'L S 1 6 4 36 MHz 36 M Hz T Y P IC A L P O W E R D IS S IP A T IO N 21 m W per , h O ~ th e le ve l q A' o r q H - re s p e c tiv e ly , b e fo re th e in d ic a te d s te a d y -s , e fo r e th e m o s t-re c e n t t t r a n s itio n o f th e c lo c k . In d ic a te s a o n e - b , O P E A C H IN P U T T Y P IC A L O F A L L O U T P U T S v Cc - C le a r ,c lo c k : S e ria


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PDF SN54164, 54LS164, SN74164, 74LS164 54164 IC 74164
74164

Abstract: Si4446DY
Text: data sheet of the same number for guaranteed specification limits. Document Number: 74164 S , testing. www.vishay.com 2 Document Number: 74164 S-71509Rev. A, 23-Jul-07 SPICE Device Model Si4446DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74164 S-71509Rev. A, 23-Jul-07 www.vishay.com 3 Legal Disclaimer Notice Vishay


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PDF Si4446DY 18-Jul-08 74164
Not Available

Abstract: No abstract text available
Text: 164 CONNECTION DIAGRAM PINOUT A b V 54/ 74164 o n > lr> . 54LS/74LS164 7 SERIAL-IN , register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of , DATA INPUT FULLY SYNCHRONOUS DATA TRANSFERS ORDERING CODE: See Section 9 PIN PKGS OUT , , 54LS164FM 3I 9A INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions PIN NAMES A, B CP MR , DESCRIPTION 0.5/0.25 0.5/0.25 0.5/0.25 10/5.0 (2.5) LOGIC SYMBOL V c c = Pin 14 G N D = Pin 7 9


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PDF 54LS/74LS164 54/74LS
sn7447

Abstract: sn7447 1 sn7442 equivalent DL340M BCD seven segment SN7448 DL330M 7 segment common anode counter decoder sn7447 N SN7442 SN7493
Text: in a D.V.M. or counter of conventional design, all digits are operated in parallel, with a separate , competitive with non-multiplexed operation. It will be generally assumed that we are talking of a system using TTL type logic families, with MSI functions being used where applicable. In most production , with a common anode connection made by Siemens provide compatibility with the most widely available , is presented serially by digit to the decoder-driver, together with an enable signal to the


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74164PC

Abstract: 74164 14 PIN DIAGRAM 74LS164PC 74LS164D 74 164 14 PIN DIAGRAM 74LS164DC two 74164 74164DC 74164 54LS164DM
Text: 164 b /54/ 74164 Of 01 V54LS/74LS164- C 7 SERIAL-IN PARALLEL-OUT SHIFT REGISTER DESCRIPTIONâ , 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an , ORDERING CODE: See Section 9 PKGS Plastic DIP (P) Ceramic DIP (D) Flatpak (F) PIN OUT COMMERCIAL , ,54LS164FM PKG TYPE 9A 6A 31 CONNECTION DIAGRAM PINOUT A INPUT LOADING/FAN-OUT: See Section 3 for U.L. definitions PIN NAMES DESCRIPTION 54/74 (U.L.) HIGH/LOW 54/74LS (U.L.) HIGH/LOW A, B CP MR Qo â


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PDF V54LS/74LS164- 54/74LS 74164PC 74164 14 PIN DIAGRAM 74LS164PC 74LS164D 74 164 14 PIN DIAGRAM 74LS164DC two 74164 74164DC 74164 54LS164DM
74164PC

Abstract: 74LS164PC
Text: CONNECTION DIAGRAM PINOUT A 54/ 74164 54LS/74LS164 SERIAL-IN PARALLEL-OUT SHIFT REGISTER DESCRIPTION - , 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an , ORDERING CODE: See Section 9 PIN PKGS Plastic DIP (P) Ceramic DIP (D) Flatpak (F) OUT A A A COMMERCIAL , is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight , the LO W -to-H IG H clock transition. LOGIC DIAGRAM Qo Qi O? Qj 04 Os 06 07


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PDF -CL06IO 54LS/74LS164 54/74LS 74164PC 74LS164PC
1998 - MSM6999

Abstract: IC 74164 pin diagram of ic 74164 MSM6999AS V74161 M4520 74164 with ic PIN DIAGRAM MSM6997 IC 74161 74161
Text: this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin . This , signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. All , Connect the AG pin and the DG pin each other as close as possible. Connected to the system ground with , Hz. FEATURES · Compliance with ITU-T companding Law MSM6996H/MSM6996V/MSM6998 : A-law MSM6997H , mW to 70 mW Typ.) · Package options : 16- pin plastic DIP (DIP16-P-300-2.54) (Product name


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PDF E2U0010-28-81 MSM6996H/6996V/6997H/6997V/6998/6999 SM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM699 OP24-P-430-1 MSM6999 IC 74164 pin diagram of ic 74164 MSM6999AS V74161 M4520 74164 with ic PIN DIAGRAM MSM6997 IC 74161 74161
1998 - MSM6999

Abstract: IC 74164 74164 with ic PIN DIAGRAM IC 74161 ic 74164 data sheet pin diagram of ic 74164 V74161 MSM6999AS PLL 4049
Text: this clock pulse should be identified with the data rate of PCM input signal at the PCMIN pin . This , signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. All , Hz. FEATURES · Compliance with ITU-T companding Law MSM6996H/MSM6996V/MSM6998 : A-law MSM6997H , mW to 70 mW Typ.) · Package options : 16- pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM6996HRS/MSM6997HRS) (Product name : MSM6996VRS/MSM6997VRS) (Product name : MSM6998RS/MSM6999RS) 16- pin


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PDF E2U0010-28-81 MSM6996H/6996V/6997H/6997V/6998/6999 SM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 MSM6996H/MSM6996V/MSM699 OP24-P-430-1 MSM6999 IC 74164 74164 with ic PIN DIAGRAM IC 74161 ic 74164 data sheet pin diagram of ic 74164 V74161 MSM6999AS PLL 4049
1999 - 2SC4416

Abstract: IC 7486 Hitachi DSA002755
Text: Storage temperature Symbol VCBO VCEO VEBO IC PC Tj Tstg Ratings 25 13 3 50 150 150 ­55 to +150 Unit V V V , V, IE = 0 VCB = 13 V, RBE = VEB = 3 V, IC = 0 I C = 20 mA, IB = 4 mA VCE = 5 V, IC = 5 mA VCB = 10 V, IE = 0, f = 1 MHz VCE = 5 V, IC = 20 mA VCC = 5 V, IC = 0.8 mA, f in = 900 MHz, f OSC = 930 MHz , Common) Test Condition VCE = 5 V, IC = 5 mA, ZO = 50 Freq. (MHz) 100 200 300 400 500 600 700 800 900 , ­39.9 ­41.3 ­43.4 ­45.0 Test Condition VCE = 5 V, IC = 10 mA, ZO = 50 Freq. (MHz) 100 200 300 400


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PDF 2SC4416 2SC4416 IC 7486 Hitachi DSA002755
1998 - IC 74161

Abstract: IC 74164 PLL 02 AG M4520 6999 MSM6998 MSM6997H MSM6996H HD44277P HD44237C
Text: .7 No.2 74164 No.3 No.8 l 74161(1) QC 74161(2) QB QA 74164 QB QC QH PCM 7 , /6996V/6997H/6997V/6998/6999 l n l IC l AGDG l IC IC l IC l VDD-0.3VVSS0.3V l LSI


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PDF J2U0010-28-61 MSM6996H/6996V/6997H/6997V/6998/6999 MSM6996H/6996V/6997H/6997V/6998/6999 SM6997H/MSM6997V/MSM6998/MSM69993003400Hz MSM6996H/MSM6996V/MSM6998 MSM6997H/MSM6997V/MSM6999 HD44200C MSM6996H HD44233CHD44237CHD44277P MSM6997H IC 74161 IC 74164 PLL 02 AG M4520 6999 MSM6998 MSM6997H MSM6996H HD44277P HD44237C
2003 - ic 74163

Abstract: IC 74164 IC 74161 IC 7416 2SC5932 2SC593
Text: Voltage VCEO 800 V Emitter-to-Base Voltage VEBO 5 V IC 20 A ICP PC 40 , =1600V, RBE=0 IC =10mA, RBE= Ratings min typ max Unit 10 µA 1.0 mA 1.0 mA 800 V VEB=4V, IC =0 Continued on next page. Any and all SANYO products described or , with your SANYO representative nearest you before using any SANYO products described or contained , Base-to-Emitter Saturation Voltage VBE(sat) 4 7 IC =13.5A, IB=3.4A IC =13.5A, IB=3.4A tstg tf


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PDF ENN7416 2SC5932 2048B 2SC5932] ic 74163 IC 74164 IC 74161 IC 7416 2SC5932 2SC593
54164

Abstract: No abstract text available
Text: REVISED M AR CH 1988 • Gated Serial Inputs SN 54164, SN 54LS164 . . . J OR W PACKAG E SN 74164 . , Inputs • Asynchronous Clear (TOP VIEW) T Y P IC A L TYPE T Y P IC A L M A X IM U M C LO , -level in p u t ena b le s th e o th e r in p u t w h ic h w ill th e n d e te rm ine th e sta te o f th , OUT SERIAL SHIFT REGISTERS logic diagram (positive logic) D h 3 o O CL O *- a , com m en ded operating conditions SN 54164 NOM 4 .5 SN 74164 MAX MIN NOM 5 5.5


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PDF SN54164, SN54LS164. SN74164, SN74LS164 54LS164 LS164 54164
fc-638l

Abstract: RTL8208 GTS FC-638L 74164 pin assignment fc-638 001C two 74164 ic 74164 FC638L 100Base-FX ENC
Text: multiple functions. In those cases, the functions are separated with a "/" symbol. Refer to the Pin , . 2 2. General Description . 2 3. Block Diagram . 3 4. Pin Assignments. 4 5. Pin , -TX performance Fully compliant with IEEE 802.3/802.3u IEEE 802.3u compliant Auto-negotiation for 10/100 Mbps , Multiple driving capabilities of RMII/SMII/SS-SMII Supports 25MHz crystal as clock source for RMII with


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PDF RTL8208 100Base-FX 14x20 530-ASS-P004 fc-638l RTL8208 GTS FC-638L 74164 pin assignment fc-638 001C two 74164 ic 74164 FC638L 100Base-FX ENC
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