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X96012V14IZT1 Intersil Corporation Universal Sensor Conditioner with Dual Look Up Table Memory and DACs; Temperature Range: -40°C to 85°C; Package: 14-TSSOP T&R
LM2512ASN/NOPB Texas Instruments Mobile Pixel Link (MPL-1) 24Bit RGB Display Interf Serializer w/ Optional Dithering & Look Up Table 40-X2QFN -30 to 85
LM2512ASNX/NOPB Texas Instruments Mobile Pixel Link (MPL-1) 24Bit RGB Display Interf Serializer w/ Optional Dithering & Look Up Table 40-X2QFN -30 to 85
LM2512ASMX/NOPB Texas Instruments Mobile Pixel Link (MPL-1) 24Bit RGB Display Interf Serializer w/ Optional Dithering & Look Up Table 49-NFBGA -30 to 85
LM2512ASM/NOPB Texas Instruments Mobile Pixel Link (MPL-1) 24Bit RGB Display Interf Serializer w/ Optional Dithering & Look Up Table 49-NFBGA -30 to 85
U5B7741393 Texas Instruments Operational Amplifier 8-TO-99 0 to 70

74139 truth table Datasheets Context Search

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74139

Abstract: 74139 datasheet data sheet 74139 Si2337DS
Text: data sheet of the same number for guaranteed specification limits. Document Number: 74139 S , Document Number: 74139 S-52290Rev. A, 31-Oct-05 SPICE Device Model Si2337DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74139 S


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PDF Si2337DS 18-Jul-08 74139 74139 datasheet data sheet 74139
2014 - Not Available

Abstract: No abstract text available
Text: specification limits. S14-1808-Rev. B, 08-Sep-14 Document Number: 74139 1 For technical questions , -Sep-14 Document Number: 74139 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS , -Sep-14 Document Number: 74139 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS


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PDF Si2337DS 2002/95/EC. 2002/95/EC 2011/65/EU. JS709A 02-Oct-12
2004 - 74139 pin diagram

Abstract: decoder 74139 74139 74139 decoder 74139 pin configuration with 74139 Dual 2 to 4 line decoder r23b AD8065 AD5405 P124 FAIRCHILD
Text: . EVAL-AD5405EB TABLE OF CONTENTS Operating the Evaluation Board , ­36 P1­9 P1­8 Y3 Y2 Y1 74139 E A1 A0 Y0 U6-A P2­5 P2­6 P2­4 P1 , 1 2 3 4 5 6 7 8 9 10 11 12 DGND 74139 15 13 14 U6-B C26 0.1µF C28 , EVAL-AD5405EB ORDERING INFORMATION BILL OF MATERIALS Table 1. Qty 1 1 Reference Designator U1 U2


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PDF 12-Bit, EVAL-AD5405EB AD5405 AD5405 D05214 74139 pin diagram decoder 74139 74139 74139 decoder 74139 pin configuration with 74139 Dual 2 to 4 line decoder r23b AD8065 P124 FAIRCHILD
2005 - 74139 pin diagram

Abstract: 74139 CAPACITOR TANTALUM AD8065 AD5447 AD5440 ADR01 AD5428 FEC 240-345 4047 integrated
Text: Analog Devices, Inc. All rights reserved. EVAL-AD5428/AD5440/AD5447EB TABLE OF CONTENTS Hardware , The test point pins are connected on the evaluation board to the respective DAC, as shown in Table 1 , . Table 1. Test Point Setup Test Point AD5447 AD5440 AD5428 DB11 DB11 DB9 DB7 DB10 DB10 , ­1 P1­31 74139 E A1 Y0 U6-A P1­2 P1­5 P1­4 P1­3 P1­7 P1­6 7 6 5 4 , | Page 6 of 8 EVAL-AD5428/AD5440/AD5447EB ORDERING INFORMATION BILL OF MATERIALS Table 2. Name


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PDF 8-/10-/12-Bit, EVAL-AD5428/AD5440/AD5447EB EVAL-AD5440EB EVAL-AD5447EB EB05274 74139 pin diagram 74139 CAPACITOR TANTALUM AD8065 AD5447 AD5440 ADR01 AD5428 FEC 240-345 4047 integrated
truth table for ic 74138

Abstract: ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Text: truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , state m achine files, or directly processed by the ADP. State Machine and Truth Table Entry State m , equation, netlist, state m achine, and truth table design entry Altera Design Processor (ADP) Functional , Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , achine, tru th table , and netlist design entry. These en try m eth o d s can be com bined, allow ing the


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PDF 44-Mbyte, 386-based truth table for ic 74138 ALU IC 74183 16CUDSLR IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: device number to see the table of devices that belong to the same group. Device 7400 7402 7403 , 74138 74139 74154 74157 74161 74163 74161 74164 74175 74193 74221 74240 74241 74244 74245 , Device Summary Please click on a device number to see the table of devices that belong to the same group , 7474 / 74175 / 74273 / 4013 Decoders Device 7447 7448 74137 74138 74139 74154 74259 4026


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74139

Abstract: 1100-H14
Text: .423 _ >0.7»« ,325 !S5 .190 © ,950 74.139 .406 10 112 7-331 TYP.(4) - low Power 13


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PDF 1100-H14/ 682-J 11D0H14. 74139 1100-H14
74191, 74192, 74193 circuit diagram

Abstract: Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions 74191, 74192, 74193 counter 74168 truth table of ic 7495 A schematic diagram for the IC of 7411
Text: equations, truth tables, and arithmetic and relational operations Full Altera/M entorG raphics , acroFunction Library w ith a Library M apping File (.lmf). Table 1 shows the generic functions and Table 2 , Page 332 Altera Corporation Data Sheet PLS-WS/HP Table 1. Mentor Graphics Library Mapping , pplications for the most up-to-date list of m appings. Table 2. Mentor Graphics Library Mapping , /HP Data Sheet Table 2. Mentor Graphics Library Mapping File-Macrofunctions (Part 2 of 3


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PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram Truth Table 74161 IC 7402, 7404, 7408, 7432, 7400 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions 74191, 74192, 74193 counter 74168 truth table of ic 7495 A schematic diagram for the IC of 7411
sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor ic 74148 block diagram IC 74374
Text: softw are A H D L supporting state machines, Boolean equations, truth tables, and arithm etic and , ab le 1 sh o w s the prim itive m a p p in g s and Table 3 sh ow s the m acrofu nction m ap p in g s provided in this LMF. Table 1. Valid Logic Library Mapping File-Primitives Valid Logic Primitive , . Altera Corporation Page 343 PLS-WS/SN Data Sheet Table 2. Viewlogic Library Mapping , /SN Table 3. Valid Logic & Viewlogic Library Mapping Files-Macrofunctions (Part 1 of 3) Valid


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ic 74139 decoder pin diagram

Abstract: 74139 pin diagram ic 74139
Text: 74_139 ). SPECIFICATION DRAWING 128K D IM E N S IO N S IN X 16-FCT139 STATIC RAM MODULE


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PDF 02SM7T3 000033fl AEPSS128K16-FCT139 AEPSS128K16-FCT139 ic 74139 decoder pin diagram 74139 pin diagram ic 74139
2004 - Not Available

Abstract: No abstract text available
Text: 741.39 745.32 749.25 753.10 756.90 -0.21 -0.15 -0.12 -0.10 -0.09 -0.09 -0.08 -0.09 -0.09


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PDF UOS-EDR5377
ic 74139 decoder pin diagram

Abstract: 74139 pin diagram ic 74139 74139 decoder chip pinout decoder 74139 74139 decoder IC 74139 features of ic 74139 74139 decoder CI 74139
Text: SI HARRIS ff Pi. "-Q2C139 o> co O CM CO Programmable Chip Select Decoder (PCSD™) Features • Memory or I/O Chip Select Decoding, Replaces 2-3 ICs • Similar to Industry Standard 74139 • Architecture Optimized for "Bootstrap Decoding" • Microprocessor Bus Oriented Interface « Harris Advanced , . One may build a pro- Programming Specifications TABLE 1. SYMBOL TEST CONDITIONS LIMITS MIN , . HPL-82C139 EDIT MODE PINOUT 7-32 grammer to satisfy the specifications described in the table , or


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PDF -Q2C139 16-Pin -40OC HPL-82C139 ic 74139 decoder pin diagram 74139 pin diagram ic 74139 74139 decoder chip pinout decoder 74139 74139 decoder IC 74139 features of ic 74139 74139 decoder CI 74139
counter 74168

Abstract: 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74175 flip flops 74151 8 by 1 Multiplexer flip flop 74379
Text: packages used. Each number of N|/g, N\/DD and N\/SS m the above table shows OKI's recommendable standard specification. Conditions: J I/O + NVDD + NVSS ^ NPAD *2 In above table , the number of Vqq and Vgs means , HM70KV). • Internal basic block table (144 types) Type No. Functional block name Logic function No , basic block table (144 types) Type No. Functional block name Logic function No. of unit cell Notes 24 , Material Copyrighted By Its Respective Manufacturer • Internal basic block table (144 types) Type No


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PDF MSM70V000 MSM70V000, counter 74168 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74175 flip flops 74151 8 by 1 Multiplexer flip flop 74379
asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder 74169 SYNCHRONOUS 4-BIT BINARY COUNTER counter 74169 MH 74151
Text: simultaneous switching and the types of packages used. Each number of N|/q, N\/DD and N\/SS m the above table , table , the number of Vqd and Vgs means fixed pads which are located at four corners of the chip, and , €¢ Internal basic block table (144 types) Type No. Functional block name Logic function No. of unit cell , (To be continued) 164 • Internal basic block table (144 types) Type No. Functional block name , (To be continued) 165 • Internal basic block table (144 types) Type No. Functional block name


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PDF MSM70V000 MSM70V000, asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder 74169 SYNCHRONOUS 4-BIT BINARY COUNTER counter 74169 MH 74151
ic 74138 pin diagram

Abstract: 74138 PIN DIAGRAM 74139 pin diagram ic 74139 74138 OCTAL decoder ic 74139 decoder pin diagram ic 74138 gl520 74139 decoder 74139 ic
Text: © Harris HPL-82C339 Programmable Chip Select Decoder (PCSD™) Features • Memory or I/O Chip Select Decoding, Replaces 3-7 ICs • Superset of the Industry Standard 74138/ 74139 • Microprocessor Bus Oriented Interlace • Address "Match" Output Facilitates Bus Arbitration and "Walt-state" , in the table , or use any of the commercially available programmers which meets these specifications. Please contact Harris for a list of approved programmers. Programming Specifications TABLE 1. SYMBOL


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PDF HPL-82C339 HPL-82C339-5. HPL-82C339-9. HPL-82C339-8. 1250C ic 74138 pin diagram 74138 PIN DIAGRAM 74139 pin diagram ic 74139 74138 OCTAL decoder ic 74139 decoder pin diagram ic 74138 gl520 74139 decoder 74139 ic
74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
Text: \/DD and NVSS in the above table shows OKI's recommendable standard specification. Conditions: M I/O + NVDD + NVSS ^ NPAD *2 In above table , the number of VDD and Vss means fixed pads which are , HM70KH). • Internal basic block table (144 types) Type No. Functional block name Logic function No , basic block table (144 types) Type No. Functional block name Logic function No. of unit cell Notes AND , Material Copyrighted By Its Respective Manufacturer • Internal basic block table (144 types) Type No


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PDF MSM70H000 MSM70H000, 74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 Multiplexer 74153 bcd counter using j-k flip flop diagram CI 74138
Text: 25 30 F.O 0 50 100 150 200 CL (PF) CELL LIBRARIES The table below and on the following , 74138 74139 Logic Function BCD-to-Decimal Decoder 4-Bit Magnitude Comparator 8-Bit Shift Register


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PDF MSM60300, MSM60700, MSM61000 MSM61000 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 Multiplexer 74153 bcd counter using j-k flip flop diagram CI 74138
74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74165 block diagram 74181 74175 clock 74151 demultiplexer
Text: (BN) Propagation Delay Time vs. Load Capacitance CL (PF) CELL LIBRARIES The table below and on the , g 74139 2-line to 4-line Decoder/Demultiplexer (0139) 7 10 74148 8-line to 3-line Priority Encoder


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PDF MSM60300, MSM60700, MSM61000 MSM60300. MSM60700. MSMC0300 MSM60700 MSM61000 74139 demultiplexer 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74165 block diagram 74181 74175 clock 74151 demultiplexer
7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 CMOS 4017 series ttl 74395 74106
Text: 23 74198 92 74377 48 7452 8 74139 20 74199 85 74378 34 7453 7 74141 16 74225 450 74379 24 7454 7


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PDF KG10000 7408 CMOS TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 CMOS 4017 series ttl 74395 74106
IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Text: P L U S -c o m p a tib le functions. Table 1. Mentor Graphics Library Mapping File (Basic , (Valid Logic ED IF netlist writer) version 1.1 (SU N 4-P 1) or higher Table 2 lists the Valid Logic basic functions that are mapped to M A X + P L U S com patible functions. Table 2. Valid Logic , -IN fu n ctio n s that are m a p p e d to M A X + P L U S - c o m p a tib le functions. Table 3 , Support for TTL Macrofunctions Table 4. TTL Function Mappings in Altera-Provided LMFs (Part 1 o f 3


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ic 74138 pin diagram

Abstract: IC 74138 74138 ic diagram ic 74139 ic 74139 decoder pin diagram 74138 OCTAL decoder decoder IC 74138 of ic 74138 74138 IC decoder IC 74139 pin diagram
Text: © · · · · · · · · h a r r is H PL-Q 2C 339 Programmable Chip Select Decoder (PCSDTM) Pinouts TO P VIEW A B Features Memory or I/O Chip Select Decoding, Replaces 3-7 ICs Superset of the Industry Standard 74138/ 74139 Microprocessor Bus Oriented Interlace Address "Match" Output Facilitates Bus , satisfy the specifications described in the table , or use any of the com m ercia lly available pro gram m , . Programming Specifications TABLE 1. LIMITS SYMBOL VCCP PARAMETER VCC Voltage During Program m ing VCC


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PDF HPL-82C339-5. PL-82C339-9. HPL-82C339-8. 1250C HPL-82C339 ic 74138 pin diagram IC 74138 74138 ic diagram ic 74139 ic 74139 decoder pin diagram 74138 OCTAL decoder decoder IC 74138 of ic 74138 74138 IC decoder IC 74139 pin diagram
ic 74139

Abstract: ic 74139 decoder pin diagram decoder IC 74139 74139 ic 74139 decoder chip pinout features of ic 74139 of ic 74139 74HCxx ic 74139 decoder 74139 pin diagram
Text: 33 H a r r is Features HPL -Q2C139 Programmable Chip Select Decoder (PCSD ) Pinout T O P VIEW A C o> CO O 74139 · Architecture Optimized for "Bootstrap Decoding" · Microprocessor Bus , in the table , or use any o f the com m ercially available pro grammers w hich meets these specifications. Please contact Harris for a list o f approved programmers. Programming Specifications TABLE 1


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PDF -Q2C139 16-Pin -40OC -550C HPL-82C139 ic 74139 ic 74139 decoder pin diagram decoder IC 74139 74139 ic 74139 decoder chip pinout features of ic 74139 of ic 74139 74HCxx ic 74139 decoder 74139 pin diagram
169403

Abstract: 74687 74699 74537
Text: . -74.771 -74.699 -74.687 -74.702 0.000 0.000 0.000 0.000 0.000 0 0 Max. -74.488 -74.428 -74.389 - 74.139


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PDF MIL-STD-883 CLC400AJ-QML 169403 74687 74699 74537
1997 - 7474 D flip-flop

Abstract: vhdl code for 74154 4-to-16 decoder 7478 J-K Flip-Flop vhdl code for 74194 74138 full subtractor 3-8 decoder 74138 shift register by using D flip-flop 7474 full subtractor circuit using xor and nand gates vhdl code for 8-bit BCD adder 74823 FULL ADDER
Text: pad macro name. The bussed macros are named IPAD4, IPAD8, IPAD16, IPAD32, etc. The table below is , manner. The table provides guide lines for the use of these macros. This table is provided only as a , no frills; TFF is a T flip-flop; and JKFF is a standard JK flipflop. The table below lists the , , contain a 2-to-1 multiplexer at the input. The features of each latch macro is described in the table , and their TTL counterparts are noted in the table . TTL42q TTL74q TTL78q TTL104q TTL105q


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1996 - full subtractor circuit using xor and nand gates

Abstract: 74138 full subtractor 7474 D flip-flop vhdl code for 8-bit BCD adder 3-input-XOR 74138 decoder data sheet 74139 vhdl code for 8 bit ODD parity generator 74594 74171
Text: high-drive pad macros configured in this manner. The table provides guidelines for the use of these macros. This table is provided only as a guide. Low to medium speed designs may require fewer high-drive pads , frills; TFF is a T flip-flop; and JKFF is a standard JK flipflop. The table below lists the features of , table below. Macro DLA DLAC DLAE DLAEC DLAMUX DLAEMUX DLAD DLADE Description D-Latch , these macros and their TTL counterparts are noted in the table . TTL42q TTL74q TTL78q TTL104q


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