48-PIN
Abstract: No abstract text available
Text: LA T P A C 66-Pin P G A 48- Pin SLC C 48- Pin ° r Lead 48- Pin y Lead 48- Pin G u llw in g 50- Pin P G A , Lead 48- Pin " J " Lead 48- Pin G u llw in g 50- Pin P G A 66-Pin P G A 66-Pin P G A 66-Pin P G A 48- Pin , Lead 48- Pin " J " Lead 48- Pin G u llw in g 50- Pin P G A 66-Pin P G A 66-Pin P G A 66-Pin P G A 66-Pin P , , 2 5 0 120, 150, 170, 200, 250 100*, 120*, 150, 200, 250 40- Pin P G A 66-Pin P G A 40- Pin P G A 66-Pin P G A 66-Pin P G A 191 199 207 215 223 DPV32X16A DPV3232VA DPV128X16A D P V 12832V A DPV256X32V
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PS128M
PS3232V
DPS128X16CJ3/BJ3
PS128X16CH
DPS128X16Y3
PS128X16H
PS128X24BH
PS512S8BN
PS512S8N
48-PIN
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A273D
Abstract: 16J3 512X32 48pin
Text: llw in g 50- Pin P G A 66-Pin P G A 66-Pin P G A 32- Pin D IP 36- Pin SIP 32- Pin D IP 48- Pin SLC C 48- Pin , P G A 64- Pin S IM M 66-Pin P G A 64- Pin Z IP 64- Pin S IM M 72- Pin Z IP 72- Pin S IM M 66-Pin P G A Ì , g 66-Pin P G A 66-Pin P G A 66-Pin P G A 68- Pin SLC C 68- Pin " \ " Lead 68- Pin " 1 " Lead 68- Pin G u llw in g 66-Pin P G A 72- Pin Z IP 72- Pin S IM M 66-Pin P G A 72- Pin Z IP 72- Pin S IM M 66-Pin P G A 52- Pin S L C C 52- Pin " \ " Lead 52- Pin " 1 " Lead 52- Pin G u llw in g 66-Pin P G A ^ 459 12 M egabit
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26-Pin
72-Pin
A273D
16J3
512X32
48pin
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1990 - Not Available
Abstract: No abstract text available
Text: -megabit SRAM module · High-speed CMOS SRAMs - Access time of 25 ns · 66-pin , 1.1-inch-square PGA package · Low , HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 Package Type 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module Military Commercial
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CYM1828
66-pin,
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Not Available
Abstract: No abstract text available
Text: -megabit SRAM module ⢠High-speed CMOS SRAMs âAccess time of 25 ns ⢠66-pin , 1.1-inch-square PGA package â , Package lype Operating Range 25 CYM1828HGâ25C HG01 66-Pin PGA Module Commercial 30 CYM1828HGâ30C HG01 66-Pin PGA Module Commercial 35 CYM1828HGâ35C HG01 66-Pin PGA Module Commercial CYM1828LHG-35C HGOl 66-Pin PGA Module CYM1828HGâ35MB HG01 66-Pin PGA Module Military CYM1828LHGâ35MB HGOl 66-Pin PGA Module 45 CYM1828HGâ45C HGOl 66-Pin PGA Module Commercial CYM1828LHGâ45C HGOl 66-Pin PGA
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PDF
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CYM1828
66-pin,
CYM1828LHG-35C
66-Pin
CYM1828HGâ
CYM1828LHGâ
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32kx8 sram
Abstract: No abstract text available
Text: ¢ High-speed CMOS SRAMs âAccess time of 25 ns ⢠66-pin , 1.1-inch-square PGA package ⢠Low active power , Package Name Package lype Operating Range 25 CYM1828HGâ25C HG01 66-Pin PGA Module Commercial 30 CYM1828HGâ30C HG01 66-Pin PGA Module Commercial 35 CYM1828HGâ35C HG01 66-Pin PGA Module Commercial CYM1828LHGâ35C HG01 66-Pin PGA Module CYM1828HGâ35MB HG01 66-Pin PGA Module Military CYM1828LHGâ35MB HG01 66-Pin PGA Module 45 CYM1828HGâ45C HG01 66-Pin PGA Module Commercial CYM1828LHGâ45C HG01
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CYM1828
66-pin,
CYM1828
CYM1828LHGâ
66-Pin
CYM1828HGâ
GYM1828HG-45MB
32kx8 sram
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1996 - AN217
Abstract: 103E2 74F786 03624E-2 63e2
Text: . The 4 input pins (1, 2, 3, and 15) to the AND gate were all grounded. The output of the AND, Pin 14, was left open. The output enable EN pin (9) was grounded. The power ground pin (8) was grounded and the VCC power pin (16) was connected to VCC. The 4 input pins to the arbiter (4, 5, 6, and 7) were , (13pF). Thus each active output pin has a load of approximately 500 to ground and 50pF to ground (43pF plus 5 to 10pF wiring capacitor). In addition, the active output pin being tested was connected to the
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74F786
AN217
74F786
10E6hz)
260E2
AN217
103E2
03624E-2
63e2
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1838 t
Abstract: CYM1838 CYM1838HG-20C CYM1838HG-20M CYM1838HG-20MB CYM1838HG-25C 8 pin 4812 pin diagram static ram 2015
Text: Access time of 20 ns ⢠66-pin , 1.1-inch-square PGA package ⢠Low active power â 4.0W(max.) â , Package Type Operating Range 20 CYM1838HG-20C HG01 66-Pin PGA Module Commercial CYM1838HG-20M HG01 66-Pin PGA Module Military CYM1838HG-20MB HG01 66-Pin PGA Module 25 CYM1838HG-25C HG01 66-Pin PGA Module Commercial CYM1838HG-25M HG01 66-Pin PGA Module Military CYM1838HG-25MB HG01 66-Pin PGA Module 35 CYM1838HG-35C HG01 66-Pin PGA Module Commercial CYM1838HG-35M HG01 66-Pin PGA Module Military CYM1838HG
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66-pin,
CYM1838
CYM1838
1838 t
CYM1838HG-20C
CYM1838HG-20M
CYM1838HG-20MB
CYM1838HG-25C
8 pin 4812 pin diagram
static ram 2015
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1992 - 1838 t
Abstract: 1838 t pin diagram 1838 pin configuration 2015 static ram CYM1838 static ram 2015
Text: - Access time of 20 ns · 66-pin , 1.1-inch-square PGA package · Low active power - 4.0W (max.) · , Package Name Package Type Operating Range 66-Pin PGA Module Commercial HG01 66-Pin PGA Module Military CYM1838HG-20MB HG01 66-Pin PGA Module CYM1838HG-25C HG01 66-Pin PGA Module Commercial CYM1838HG-25M HG01 66-Pin PGA Module Military CYM1838HG-25MB HG01 66-Pin PGA Module CYM1838HG-35C HG01 66-Pin PGA Module Commercial CYM1838HG
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CYM1838
66-pin,
1838 t
1838 t pin diagram
1838 pin configuration
2015 static ram
CYM1838
static ram 2015
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Not Available
Abstract: No abstract text available
Text: and the output clocks is accomplished when one output clock is connected to the input pin FBIN. The , -07 input is 66 MHz with 66 and 33 MHz output buffers AV9172-01 is pin compatible with Gazelle GA1210E , drive, 25mA outputs Low cost 16- pin SOIC (300 mil) or 16- pin PDIP package The AV9172 is fabricated , Block Diagram IAV9172RevA093094 D-37 AV9172 Pin Configuration GND GND ÎN V Ï EN2 FBIN CLKIN , 2X 2X 02 02 IX IX IX IX 16- Pin SOIC or 16- Pin PDIP K-6, K-4 Pin Description for AV9172
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AV9172
500ps,
AV9172-01
AV9172-01CN16,
AV9172-03CN16,
AV9172-07CN16
AV9172-01CS16,
AV9172-03CS16,
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1992 - Not Available
Abstract: No abstract text available
Text: -megabit SRAM module · High-speed CMOS SRAMs - Access time of 20 ns 66-pin , 1.1-inch-square PGA package · · Low , HG01 HG01 HG01 HG01 Package Type 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module , Diagram 66-Pin PGA Module HG01 CYM1838 PIN 1 1.090MAX. 1.090MAX. 0.320 MAX. 0.180 0.050 .012 , static RAMs mounted onto Logic Block Diagram A0 - A16 OE Pin Configuration PGA Top View 1 12 I
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CYM1838
66-pin,
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static ram 2015
Abstract: No abstract text available
Text: module · High-speed CMOS SRAMs - Access tim e of 20 ns · 66-pin , 1.1-inch-square PGA package · Low , Name HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 HG01 Package Type 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module Commercial Military Commercial Military Operating Range Commercial Military 5 CYM1838 Package Diagram 66-Pin PGA Module HG01 1.090MAX. 1.090MAX. 11 22 33 44 55 66
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CYM1838
66-pin,
static ram 2015
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BCX32
Abstract: No abstract text available
Text: module · High-speed CMOS SRAMs - Access time of 25 ns · 66-pin , 1.1-inch-square PGA package · Low active , HG01 HG01 HG01 HG01 HG01 HG01 HG01 Package Type 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA Module 66-Pin PGA , Package Diagram 66-Pin PGA Module HG01 1.090MAX. 1.090MAX. 11 22 33 44 55 66 ® ® @ , static RAMs mounted onto Logic Block Diagram Pin Configuration PGA Top View 1 12 23 34 45 56
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CYM1838
66-pin,
BCX32
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Not Available
Abstract: No abstract text available
Text: hard drive, compatible with IDE/ATA 40- pin and 44- pin Introduction à High operating reliability , stand-by and sleep mode 150mA(max.) Enclosure Material Dimensions PC Mechanical Cover and UL-94 40- pin : 60.2 x 27.8 x 6.4mm (W x H x L) 44- pin : 50.3 x 27.3 x 5.8mm (W x H x L) Ordering Information , -66 40 PIN 40 PIN 40 PIN 40 PIN 40 PIN 40 PIN 40 PIN 40 PIN 44 PIN 44 PIN 44 PIN 44 PIN 44 PIN 44 PIN 44 PIN 44 PIN 128MB 256MB 512MB 1GB 2GB 4GB 8GB 16GB 128MB 256MB 512MB 1GB
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FIM-60
128MB
40-pin
44-pin
128MB
256MB
512MB
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1998 - 103e2
Abstract: AN217 03624E-2 74F786
Text: gate were all grounded. The output of the AND, Pin 14, was left open. The output enable EN pin (9) was grounded. The power ground pin (8) was grounded and the VCC power pin (16) was connected to VCC. The 4 , silvered mica capacitor, and a grounded scope probe (13pF). Thus each active output pin has a load of , output pin being tested was connected to the input of a comparator (3pF max.). The other input to this , circuit. This form of input causes only one of the two possibly active outputs to switch low. PIN 4
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AN217
74F786
74F786
103e2
AN217
03624E-2
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Not Available
Abstract: No abstract text available
Text: Operating Range 25 C Y M 1828H G â25C HG01 66-Pin P G A M odule 30 C Y M 1828H G â30C H G 01 66-Pin P G A M odule C om m ercial 35 C Y M 1828H G â35C HG01 66-Pin P G A M odule C om m ercial C Y M 1828L H G - 35C H G 01 66-Pin P G A M odule C Y M 1828H G â35M B H G 01 66-Pin PG A M odule C Y M 1828L H G â35M B H G 01 66-Pin P G A M odule C Y M 1828H G â45C HG01 66-Pin P G A M odule C Y M 1828L H G â45C 66-Pin P G A
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CYM1828
66-Pin
1828L
1828H
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AE200
Abstract: cm0016
Text: and the output clocks is accomplished when one output clock is connected to the input pin FBIN. The , -07 input is 66 MHz with 66 and 33 MHz output buffers AV9172-01 is pin compatible with Gazelle GA 210E , drive, 25mA outputs Low cost 16- pin SOIC (300 mil) or 16- pin PDIP package The AV9172 is fabricated , Block Diagram A V 9172R evB 011396 | AV9172 Pin Configuration GND GND INV1 EN2 FBIN CLKIN VDD , Q4 2X 2X 01 01 Q5 2X 2X 02 02 16- Pin SOIC or 16- Pin PDIP NOTES: 1. IX designates that the
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AV9172
AV9172
500ps,
AV9172-01
16-Pin
AV9172-xxCN16
AV9172-xxCW16
AV9172-xxCS16
V9172-XX
AE200
cm0016
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1997 - AV9172-07
Abstract: marking 2x AV9172 AV9172-01 AV9172-03 GA1210
Text: clock and the output clocks is accomplished when one output clock is connected to the input pin FBIN , MHz with 66 and 33 MHz output buffers · AV9172-01 is pin compatible with Gazelle GA1210E · ±250ps , Low cost · 16- pin SOIC (150-mil) or 16- pin PDIP package The AV9172 is fabricated using CMOS , and accurate. AV9172 Pin Configuration Functionality Table for AV9172-01 CLKIN input , . 5. Ø2 will produce a ¼ duty cycle clock delayed 180° from CLKIN. 16- Pin SOIC or 16- Pin PDIP
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AV9172
AV9172
500ps,
AV9172-01
AV9172-07
marking 2x
AV9172-01
AV9172-03
GA1210
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Not Available
Abstract: No abstract text available
Text: clock and the output clocks is accomplished when one output clock is connected to the input pin FBIN , -01 is pin compatible with Gazelle GA1210E ±250ps skew (max) between outputs ±500ps skew (max , current High drive, 25mA outputs Low cost 16- pin SOIC (150-mil) or 16- pin PDIP package The AV9172 is , n by th e c u s to m e r is c u rre n t a n d a c c u ra te . m AV9172 Pin Configuration , cycle clock delayed 180° from CLKIN. GND 16- Pin SOIC or 16- Pin PDIP Pin Description for
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AV9172
AV9172
500ps,
AV9172-01
150mil)
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IR 1838 T
Abstract: 1838 pin configuration ir IR 1838 T Pin number IR 1838 1838 T IR 1838 TO PIN DIAGRAM 1838 t pin diagram 1838 ir IR 1838 3.3 v CS40
Text: -megabit SRAM module ⢠High-speed CMOS SRAMs âAccess time of 25 ns ⢠66-pin , 1.1-inch-square PGA package , Package TVpe Operating Range 25 CYM1838HG-25C HG01 66-Pin PGA Module Commercial CYM1838HGâ25M HG01 66-Pin PGA Module Military CYM1838HGâ25MB HG01 66-Pin PGA Module 30 CYM1838HGâ30C HG01 66-Pin PGA Module Commercial CYM1838HGâ30M HG01 66-Pin PGA Module Military CYM1838HG-30MB HG01 66-Pin PGA Module 35 CYM1838HGâ35C HG01 66-Pin PGA Module Commercial CYM1838HG-35M HG01 66-Pin PGA Module
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CYM1838
66-pin,
CYM1838
CYM1838HG-25C
66-Pin
CYM1838HGâ
IR 1838 T
1838 pin configuration ir
IR 1838 T Pin number
IR 1838
1838 T
IR 1838 TO PIN DIAGRAM
1838 t pin diagram
1838 ir
IR 1838 3.3 v
CS40
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L2233C
Abstract: c0832C
Text: Power Supplies (V) 5 1+10%) 5 (±10%) Temperature Range1 C 1 M X X X Package 28- Pin DIR 28- Pin P C C 28- Pin DIR 28- Pin PCC 8- Pin DIP Comments /iP Com p, 8-CH /j P Com p, 8-CH Serial I/O, Single CH , ADC0831C 8 ±1 6.0 5 (±10%) X X X 8- Pin DIP ADC0832B 8 ±1/2 6.0 5 (±10%) X X X 8- Pin DIP AD C0832C 8 +1 6.0 5 (±10%) X X X 8- Pin DIP ADC0833B 8 ±1/2 6.0 5 (±10%) 5 (±10%) X X X 14- Pin DIP A D C0833C
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ADC08
28-Pin
ADC0809
39kHz,
L2283C
ML2284B
L2233C
c0832C
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1997 - Not Available
Abstract: No abstract text available
Text: accomplished when one output clock is connected to the input pin FBIN. The PLL circuitry matches rising edges , output buffers · AV9172-01 is pin compatible with Gazelle GA1210E · ±250ps skew (max) between outputs · , results in low power supply current · High drive, 25mA outputs · Low cost · 16- pin SOIC (150-mil) or 16- pin , information being relied upon by the customer is current and accurate. AV9172 Pin Configuration , 1X 1X Q1 1X# 1X 1X# 1X Q2 2X 2X 2X 2X Q3 2X 2X 2X 2X Q4 2X 2X 1 1 Q5 2X 2X 2 2 16- Pin SOIC or 16- Pin
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AV9172
AV9172
500ps,
AV9172-01
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1996 - marking 2x
Abstract: AV9172 AV9172-01 AV9172-03 AV9172-07 D-35
Text: the output clocks is accomplished when one output clock is connected to the input pin FBIN. The PLL , AV9172-07 input is 66 MHz with 66 and 33 MHz output buffers AV9172-01 is pin compatible with Gazelle , cost 16- pin SOIC (150-mil) or 16- pin PDIP package The AV9172 is fabricated using CMOS technology , doubler and buffer Clock buffer for 66 MHz input AV9172 Pin Configuration Configuration Table for , -01 GND GND 16- Pin PDIP or 16- Pin SOIC J-4, J-6 EN2 INV Q0 Q1 Q2 Q3 Q4 Q5
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AV9172
AV9172
500ps,
AV9172-01
AV9172-xxCC16
AV9172-xxCN16
AV9172-xxCW16
AV9172-xxCS16
AV9172-XX
marking 2x
AV9172-01
AV9172-03
AV9172-07
D-35
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2003 - transistor 257
Abstract: TO-254M transistor 254 isolated npn
Text: / _ = Straight Leads UB = Up Bend DB = Down Bend Pin Out Configuration 5/ _ = Normal R = Optional , Bend Configurations are Available for `M' (TO254) and `J' (TO-257) Packages Only. 5/ Optional Pin Out , ; SPT6235JR PIN ASSIGNMENT (Standard) Package Collector Emitter Case (1) Pin 2 TO-66 (/66) Pin 1 Pin 2 TO-254 (M) Pin 1 Pin 2 TO-257 (J) Base Pin 3 Pin 3 Pin 3 PIN ASSIGNMENT (Optional) Package Collector Emitter Base Pin 2 Pin 3 Pin 1 TO-254 (MR) Pin 2 Pin 3 Pin 1 TO-257 (JR) SOLID STATE DEVICES INC
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SPT6233
SPT6235
SPT6234
SPT6235
O-111,
2N6233
2N6235
O-254
O-257
transistor 257
TO-254M
transistor 254 isolated npn
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Not Available
Abstract: No abstract text available
Text: ¢ 16 pin SOIC (300 mil) or 16 pin PDIP package ⢠Inputs and outputs are fully TTL compatible â , ICS9175 Configuration Table - ICS9175-04 (All units in MHz) Pin Configuration GND r 1 16 , 33 â¡ qi VDD c SCLK1 XI â¡ QO HI GND Pin Descri ption for ICS9175-G 4 PIN NAME GND GND SCLK1 SCLKO XI X2 VDD VDD GND QO Ol Q2 Q3 Q4 Q5 VDD PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN TYPE _ Input Input Input Input - Output
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ICS9175
ICS9175
ICS9175-xxCN16
ICS9175-xxCS16
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Not Available
Abstract: No abstract text available
Text: one output clock is connected to the input pin FBIN. The PLL circuitry matches rising edges of the , -01 is pin compatible with Gazelle GA1210E ±250ps skew (max) between outputs ±500ps skew (max , CMOS process results in low power supply current High drive, 25mA outputs Low cost 16- pin SOIC (300 mil) or 16- pin PDIP package The AV9172 is fabricated using CMOS technology which results in much , AV9172-01 Clock doubler and buffer Clock buffer for 66 MHz input AV9172 Pin Configuration
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PDF
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AV9172
AV9172
500ps,
AV9172-01
AV9172-01CN16,
AV9172-03CN16,
AV9172-07CN16
AV9172-01CS16,
AV9172-03CS16,
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