The Datasheet Archive

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Part Manufacturer Description Datasheet Download Buy Part
LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LT1018MJ8/883 Linear Technology LT1018 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LM108AJ8 Linear Technology LM108A - Operational Amplifiers; Package: CERDIP; Pins: 8; Temperature: Military
LT1175CDWF#MILDWF Linear Technology LT1175 - 500mA Negative Low Dropout Micropower Regulator; Pins: 5
LTC1041MJ8/883 Linear Technology LTC1041 - BANG-BANG Controller; Package: CERDIP; Pins: 8; Temperature: Military
LTC2904CDDB#TRMPBF Linear Technology LTC2904 - Precision Dual Supply Monitor with Pin-Selectable Thresholds; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C

638-PIN Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ARCAP

Abstract: pin male 2,4mm d 637 r
Text: Contact resistance between pin and socket : <0.0020 1mm - <0.0015 1,6mm - <0.00102,4mm - Flashover , ,93 mm21,6mm - 3,18 mm22,4mm. Part numbers : Pin insert receptacles, socket insert plugs and cable connecting plugs, pin insert Shell size 1 1 2 2 1 1 1 2 1 1 2 Number of contacts 12 19 27 37 3 4 7 12 3 4 7 contacts circular receptacle pin insert 1mm 637 203 606 637 204 606 637 207 606 637 212 606 1.6mm 2.4mm receptacle pin insert 637 012 006 637 019 006


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2007 - "socket s1"

Abstract: socket s1 amd 638 pin AMD socket s1 638 pin micro PGA socket s1 REFLOW 638-Pin Cu-194 amd socket s1 mechanical socket s1 Advanced Micro Devices
Text: .9 2.1 Organic PGA Package ( 638-Pin , .7 Figure 2. Organic PGA Package Drawing ( 638-Pin , Introduction This document defines the requirements for a 638-pin , 1.27mm pitch, surface mount technology , mobile AMD 638-pin organic micro-pin-grid-array (µPGA) package. The Low-Profile Socket S1, shown in , family products. 1.2 Scope The specifications in this document apply to 638-pin PGA ZIF sockets


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754 PIN

Abstract: 638-Pin
Text: (3/1/03) 7-35 u Chapter 7 Trays Organic Micro Pin Grid Array: 638-Pin UOG Notes: (See , Chapter 7 Trays Organic Micro Pin Grid Array: 638-Pin UOG Notes: 1 All dimensions are in , u Chapter 7 Trays Organic Micro Pin Grid Array: 563- Pin UOG Notes: (See next page for , Organic Micro Pin Grid Array: 563- Pin UOG Notes: 1 All dimensions are in millimeters. 2 Trays can , Publication Revision A (3/1/03) 7-37 u Chapter 7 Trays Organic Micro Pin Grid Array: 754- Pin UOG


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PDF 563-Pin 638-Pin 754-Pin 754 PIN
2004 - transistor pcr 606 j

Abstract: PCR 606 J renesas 1650 pwm R5S61650 renesas h8sx 1650 pwm H8SX 1721 p35 sd h8sx 1650 pwm renesas 1650 pwm tioca PCR 406 J
Text: reset pin . During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of , ) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an , . 2 Pin Assignments. 3 1.3.1 Pin Assignments


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PDF REJ09B0029-0200Z H8SX/1650Group 32-Bit H8SX/1600 H8SX/1650 R5S61650 D-85622 H8SX/1650 transistor pcr 606 j PCR 606 J renesas 1650 pwm R5S61650 renesas h8sx 1650 pwm H8SX 1721 p35 sd h8sx 1650 pwm renesas 1650 pwm tioca PCR 406 J
2007 - HD6413008F

Abstract: HD6413008TE HD6413008VF HD6413008VTE REJ09B0213-0300 Nippon capacitors
Text: products are generally in the high-impedance state. In operation with an unused pin in the open-circuit , current flows internally, and malfunctions may occur due to the false recognition of the pin state as an , reset signal is applied to the external reset pin , the states of pins are not guaranteed from the , Block Diagram 1.3.1 Pin Arrangement 6 Table 1.2 Comparison of H8/3008 Pin Arrangements 203 , , TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel


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PDF H8/3008 REJ09B0395-0400 HD6413008F HD6413008TE HD6413008VF HD6413008VTE REJ09B0213-0300 Nippon capacitors
2007 - block diagram induction heating

Abstract: SCR IC CHIP bl p74 transistor BT 151 PIN DIAGRAM p-qfp100-14x14-0.50 REJ09B0213-0300 Nippon capacitors SCR bt 107 hd64f3062 555 timer datasheet
Text: products are generally in the high-impedance state. In operation with an unused pin in the open-circuit , current flows internally, and malfunctions may occur due to the false recognition of the pin state as an , reset signal is applied to the external reset pin , the states of pins are not guaranteed from the , Block Diagram 1.3.1 Pin Arrangement 6 Table 1.2 Comparison of H8/3008 Pin Arrangements 203 , , TMO pin output, counter clearing, and so on, is in accordance with the settings for each channel


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PDF REJ09B0395-0400 H8/3008 16-Bit Family/H8/300H H8/3008 HD6413008F HD6413008TE HD6413008VF HD6413008VTE block diagram induction heating SCR IC CHIP bl p74 transistor BT 151 PIN DIAGRAM p-qfp100-14x14-0.50 REJ09B0213-0300 Nippon capacitors SCR bt 107 hd64f3062 555 timer datasheet
2003 - Not Available

Abstract: No abstract text available
Text: 2.015 51.18 PIN 1 2.134 54.20 A PIN 34 PIN 17 "G" "F" SOLDER RETENT CLIP C L 45° u5v A PIN 36 PIN 35 PIN 51 .055 1.40 CC LL PIN 68 PIN 67 .050 1.27 , PIN 1 TOP PIN 2 TOP PIN 33 TOP PIN 34 TOP 1.650 41.91 PIN 67 TOP PIN 68 TOP C L PIN 35 TOP PIN 36 TOP .075 1.90 .185 4.70 .335 8.51 .075 1.90 .075 1.90 -B.099 2.51 PIN 2 BOTTOM PIN 1 BOTTOM PIN 35 BOTTOM PIN 36 BOTTOM .050 1.27 STAND-OFF FOOTPRINT


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PDF TS-1111--01
2008 - CMX638

Abstract: 3.5mm Stereo jack pinout female 3.5mm Stereo socket pinout CMX638 Evaluation Kit 3.5mm Stereo jack pinout PLC connect encoder ES0002 EV6180 Soundcard Circuits pcb 3.5mm female stereo pins
Text: 4. EV6180/6380 Signal Lists CONNECTOR PINOUT Connector Ref. Connector Pin No , . Connector Pin No. Signal Name Signal Type J8 Sleeve GNDA PWR Tip SOCKETP I/P , CODEC selected Audio CODEC output configured as single ended CSN drive select pin IRQN drive select pin Table 3 ­ Default jumper tab settings Notes: I/P O/P PWR = = = © 2008 CML , consumption of each supply rail remove the jumper tab from the relevant 2- pin header (JP5 for +3.3V digital


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PDF EV6180/6380 UM6180/4 CMX608, CMX618 CMX638 PE0002 EV6180: CMX608 CMX618 EV6380: 3.5mm Stereo jack pinout female 3.5mm Stereo socket pinout CMX638 Evaluation Kit 3.5mm Stereo jack pinout PLC connect encoder ES0002 EV6180 Soundcard Circuits pcb 3.5mm female stereo pins
2008 - Not Available

Abstract: No abstract text available
Text: /618/638 4. EV6180/6380 Signal Lists CONNECTOR PINOUT Connector Ref. Connector Pin No , . Connector Pin No. Signal Name Signal Type J8 Sleeve GNDA PWR Tip SOCKETP I/P , configured as single ended CSN drive select pin IRQN drive select pin Table 3 – Default jumper tab , the jumper tab from the relevant 2- pin header (JP5 for +3.3V digital, JP6 for +1.8V digital, JP7 for , three ways: Pressing switch SW1 Issuing a C-BUS reset command via the PE0002 Driving pin 16 of


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PDF EV6180/6380 UM6180/4 CMX608, CMX618 CMX638 PE0002 EV6180: CMX608 CMX618 EV6380:
MX029

Abstract: D8-D13 MX029DW MX029J MX029TN L 744 ns
Text: pops). The MX029 requires a single 5-volt supply and is available in the following packages: 16- pin SOIC (MX029DW), 16- pin CDIP (MX029J), and 24- pin TSSOP (MX029TN). 1998 MX-COM, INC. www.mxcom.com , Amplifier 4 MX029 2. Signal List Pin No. Type Description J, DW TN 1 1 Serial , of the two amplifier channels (Ch1 - Ch2) is controlled by the data entered serially at this pin , . Units Supply (VDD-VSS) -0.3 7.0 V Voltage on any pin to VSS -0.3 (VDD + 0.3) V


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PDF MX029 14-Bit 16-pin MX029J MX029 D8-D13 MX029DW MX029J MX029TN L 744 ns
1998 - encoder for PLC DELTA

Abstract: Mil-Std-188-113 DELTA MODULATION ENCODER
Text: 5.0V and is available in the following packages: 24- pin PLCC (MX629LH), 22- pin CERDIP (MX629J), and 22- pin , three-state output whose condition is set by the Data Enable and Powersave inputs. See Table 2. When this pin , perfect idle pattern. When this pin is a logical "1" the encoder encodes as normal. Internal 1M pullup. Data is made available at the encoder output pin by control of this input. See Encoder Output pin . Internal 1 M pullup. No Connection Normally at VDD/2 bias, this pin should be externally decoupled by


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PDF MX629 Mil-Std-188-113 Mil-Std-188-113 MX629 encoder for PLC DELTA DELTA MODULATION ENCODER
2008 - AMD Athlon 64 X2 4200

Abstract: RS780E AMD ATHLON 64 X2 AM2 pin out RADEON e2400 AMD Athlon 64 X2 AMD turion 64 X2 AMD Athlon II X2 ATI Radeon X1250 AMD Phenom II AMD Turion 64 X2 thermal
Text: Yes Yes 95°C S1 Lidless 638-pin oµPGA TL-56 TMDTL56HAX5DME Yes 1 1.8GHz , Yes Yes 95°C S1 Lidless 638-pin oµPGA TL-52 TMDTL52HAX5CTE Yes 1 1.6GHz , Yes Yes 95°C S1 Lidless 638-pin oµPGA AMD SempronTM Processors 3700+ SMS3700HAX4DQE , Duplex Yes Yes No Yes 95°C S1 Lidless 638-pin oµPGA 3500+ SMS3500HAX4CME , Duplex Yes Yes No Yes 95°C S1 Lidless 638-pin oµPGA 2100+ SMF2100HAX3DQE


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PDF 43838D AMD Athlon 64 X2 4200 RS780E AMD ATHLON 64 X2 AM2 pin out RADEON e2400 AMD Athlon 64 X2 AMD turion 64 X2 AMD Athlon II X2 ATI Radeon X1250 AMD Phenom II AMD Turion 64 X2 thermal
Not Available

Abstract: No abstract text available
Text: . The MX629 operates with a supply voltage of 5.0V and is available in the following packages: 24- pin PLCC (MX629LH), 22- pin CERDIP (MX629J), and 22- pin PDIP (MX629P). 1998 MX-COM, Inc , Table 2. When this pin is at a logical “0” the encoder is forced to an idle state and the encoder digital output is 0101, a perfect idle pattern. When this pin is a logical “1” the encoder encodes as normal. Internal 1M pullup. Data is made available at the encoder output pin by control of this input


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PDF Mil-Std-188-113 MX629 MX629
1998 - MX465

Abstract: MX465DW CTCSS Encoder/Decoder MX465DS MX465J MX465P MX465TN MX165C EIA-603
Text: Encoder/Decoder 2 MX465 Available in the following package styles: 24- pin TSSOP (MX465TN), 24- pin SSOP (MX465DS), 24- pin SOIC (MX465DW), 24- pin PDIP (MX465P), and 24 - pin CDIP (MX465J) the MX465 , 4 MX465 Signal List Pin No. Signal Type Description 1 VDD power Positive supply. This pin should be bypassed to VSS by a capacitor mounted close to the device pins. 2 XTAL , Figure 4). In Serial Mode, data is loaded and latched by a 0-1-0 strobe pulse on this pin (see Figure 5


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PDF MX465 TIA/EIA-603 MX165C MX465 MX465DW 24-pin-CDIP MX465J MX465DW CTCSS Encoder/Decoder MX465DS MX465J MX465P MX465TN EIA-603
2011 - Not Available

Abstract: No abstract text available
Text: hold the voltage of EN pin less than 0.3V. Another one is the main supply voltage whose purpose is for , Voltage Code PIN CONFIGURATION GND FB VOUT VOUT 1 2 3 4 8 7 EN POK VCNTL VIN VIN 6 5 PIN DESCRIPTION PIN NAME GND DESCRIPTION Ground pin . There's an external resistor divider connected to this pin which is necessary to give the feedback voltage to the regulator. The , voltage pin of the regulator. There should be set an output capacitor to compensate for closed-loop and


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PDF LXXLD15 LXXLD15 LXXLD15, QW-R502-638
1998 - MX465DW

Abstract: TSS400 MX465TN CTCSS Encoder/Decoder hex Pure sinewave inverter circuit diagram MX465P MX465J MX465DS MX465 MX165C
Text: Encoder/Decoder 2 MX465 Available in the following package styles: 24- pin TSSOP (MX465TN), 24- pin SSOP (MX465DS), 24- pin SOIC (MX465DW), 24- pin PDIP (MX465P), and 24 - pin CDIP (MX465J) the MX465 , 4 MX465 Signal List Pin No. Signal Type Description 1 VDD power Positive supply. This pin should be bypassed to VSS by a capacitor mounted close to the device pins. 2 XTAL , Figure 4). In Serial Mode, data is loaded and latched by a 0-1-0 strobe pulse on this pin (see Figure 5


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PDF MX465 TIA/EIA-603 MX165C MX465 MX465DW 24-pin-CDIP MX465J MX465DW TSS400 MX465TN CTCSS Encoder/Decoder hex Pure sinewave inverter circuit diagram MX465P MX465J MX465DS
2006 - PL-012

Abstract: No abstract text available
Text: Maximum Ratings Pin Connections RF OUT VCC V-TUNE GROUND Max. C .040 TYP SUGGESTED LAYOUT, TOLERANCE TO BE WITHIN ±.002 PIN 1 NOTES: G TYP METALLIZATION Q TYP .060 TRACE


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PDF ROS-638+ CK605 2002/95/EC) PL-012
1997 - 3543 amplifier

Abstract: 12 MHz xtal RESONATOR
Text: following package styles: 16- pin SOIC (MX102DW) and 16- pin CDIP (MX102J). © 1997 MX·COM,INC. www.mxcom.com , amplifier/comparator. Do not load this pin with peripheral circuitry; there is no drive capacity for , 's supply line. Do not attempt to draw current from either VDD pin . 5 BUFCLK output Buffered , analog amplifier/comparator. Used with the Signal Bias pin ; external coupling components are required , is fed directly into this pin ; Xtal/clock components are not required. See Table 2. Negative


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PDF MX102 10mVrms 13kHz 48-BIT 24-BIT 3543 amplifier 12 MHz xtal RESONATOR
1997 - Not Available

Abstract: No abstract text available
Text: external and peripheral functions. This MX102 is available in the following package styles: 16- pin SOIC (MX102DW) and 16- pin CDIP (MX102J). © 1997 MX•COM,INC. www.mxcom.com Tele: 800 638 5577 910 744 5050 , the analogue amplifier/comparator. Do not load this pin with peripheral circuitry; there is no drive , to the host circuit's supply line. Do not attempt to draw current from either VDD pin . 5 , . input The inverting input to the analog amplifier/comparator. Used with the Signal Bias pin


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PDF MX102 10mVrms 13kHz 48-BIT 24-BIT
MX604DW

Abstract: No abstract text available
Text: applications. The MX604 is available in the following packages: 24- pin TSSOP (MX604TN), 16- pin SOIC (MX604DW) and 16- pin PDIP (MX604P). 1998 MXCOM, INC. Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 , Modem 2. 4 MX604 PRELIMINARY INFORMATION Signal List Pin No. Name P, DW 1 , by a 3.579545MHz clock present at the XTAL/CLOCK pin . This may be generated by the on-chip , circuits. This block also includes a switchable equalizer section. When the RXEQ pin is low the overall


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PDF MX604 1200bps 75bps 58Mhz MX604 MX604DW
2000 - delta modulation

Abstract: No abstract text available
Text: 5.0V and is available in the following packages: 24- pin PLCC (MX619LH), 22- pin CERDIP (MX619J), and 22- pin , whose condition is set by the Data Enable and Powersave inputs. See Table 2. When this pin is at a , pattern. When this pin is a logical "1" the encoder encodes as normal. Internal 1M pullup. Data is made available at the encoder output pin by control of this input. See Encoder Output pin . Internal 1 M pullup. No Connection Normally at VDD/2 bias, this pin should be externally decoupled by capacitor C4


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PDF MX619 MX619 delta modulation
1999 - CMX469AD3

Abstract: CMX469AD3 marking CMX469 CMX469AE2 Modem circuit diagram MPT1327 CMX469AP6 CMX469A msk 1200 fsk modem 1200
Text: Clock Recovery and Carrier Detect Capabilities · Pin Selected Xtal/Clock Inputs 1.008MHz or 4.032MHz , in the following packages: 24- pin TSSOP (CMX469AE2), 20- pin SOIC (CMX469AD3), and 22- pin PDIP , . 1200/2400/4800bps MSK Modem 4 CMX469A PRELIMINARY INFORMATION 2. Signal List Pin No. E2 , " input pin . The selection of this frequency will affect the operational Data Rate of this device. Refer , transmitter is enabled, this pin outputs the (140-step pseudo sinewave) MSK signal. See Figure 8. With the


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PDF CMX469A 1200/2400/4800bps 008MHz 032MHz MPT1327) CMX469A 1200/2400/4800bps 2400/4800Hz 24-pin CMX469AE2 CMX469AD3 CMX469AD3 marking CMX469 CMX469AE2 Modem circuit diagram MPT1327 CMX469AP6 msk 1200 fsk modem 1200
2000 - FB412

Abstract: CMX629A CMX619AE2 MIL-STD-188-113 DB492 FDAA10255E
Text: packages: 24- pin TSSOP (CMX619AE2), 24- pin PLCC (CMX629AL2), 22- pin CERDIP (CMX629AJ3), and 22- pin PDIP , . When this pin is at a logical "0" the encoder is forced to an idle state and the encoder digital output is 0101, a perfect idle pattern. When this pin is a logical "1" the encoder encodes as normal. Internal 1M pull-up. Data is made available at the encoder output pin by control of this input. See Encoder Output pin . Internal 1 M pullup. No Connection Normally at VDD/2 bias, this pin should be externally


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PDF Mil-Std-188-113 CMX629A Mil-Std-188-113 DECODER27 22-pin CMX629AJ3 FB412 CMX629A CMX619AE2 DB492 FDAA10255E
2000 - eurocom

Abstract: delta plc 1-400HZ K7800
Text: of 5.0V and is available in the following packages: 24- pin PLCC (MX619LH), 22- pin CERDIP (MX619J), and 22- pin PDIP (MX619P). 2000 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax , set by the Data Enable and Powersave inputs. See Table 2. When this pin is at a logical "0" the , this pin is a logical "1" the encoder encodes as normal. Internal 1M pullup. Data is made available at the encoder output pin by control of this input. See Encoder Output pin . Internal 1 M pullup. No


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PDF MX619 MX619 eurocom delta plc 1-400HZ K7800
1998 - delta plc

Abstract: MIL-STD-188-113
Text: of 5.0V and is available in the following packages: 24- pin PLCC (MX629LH), 22- pin CERDIP (MX629J), and 22- pin PDIP (MX629P). 1998 MX-COM, Inc. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax , set by the Data Enable and Powersave inputs. See Table 2. When this pin is at a logical "0" the , this pin is a logical "1" the encoder encodes as normal. Internal 1M pullup. Data is made available at the encoder output pin by control of this input. See Encoder Output pin . Internal 1 M pullup. No


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PDF Mil-Std-188-113 MX629 MX629 delta plc MIL-STD-188-113
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