The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
BQ4013LYMA-70 Texas Instruments NON-VOLATILE SRAM MODULE
HM1-65642B/883 Intersil Corporation 8KX8 STANDARD SRAM, 150ns, CDIP28
24502BVA Intersil Corporation 1KX4 STANDARD SRAM, 120ns, CDIP18
BQ4014MB-120 Texas Instruments 256KX8 NON-VOLATILE SRAM MODULE, 120ns, PDIP32
SN74ALS870NT3 Texas Instruments 16X4 STANDARD SRAM, 19ns, PDIP24
SN74LS670FN Texas Instruments 4X4 STANDARD SRAM, 45ns, PQCC20

5v sram 4mb 54pin Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - L24002

Abstract: NAND "read disturb" 1GB CMOS 0.8mm process cross Lithium battery CR2025 sony M2V28S30AVP M5M51008CFP PC133 registered reference design Toshiba 512 NAND MLC FLASH BGA
Text: ) Status 144MRDRAM TM (2nd gen.) Pin assignments Low Power SRAM 1M 2M 4M Mitsubishi Low Power SRAM Technical Direction 1Mbit(x8) Low Power SRAM the Fourth Generation 2Mbit(x16) Low Power SRAM the Second Generation 4Mbit(x8) Low Power SRAM the Third Generation < 5V version> Fast SRAM 4M , SRAM the Third Generation < 5V version> 512k word x 8bits 4.5~5.5V TTL 55ns @Vcc=4.5V 50mA @Vcc=5.0V , Large Capacity 1M 4M Low Power Vcc ( 5V High Speed Fast SRAM 0.4um Super CMOS 0.25um CMOS


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PDF L-11002-01 64MDRAM 64MSDRAM 128MSDRAM 256MSDRAM 144MRDRAM L24002 NAND "read disturb" 1GB CMOS 0.8mm process cross Lithium battery CR2025 sony M2V28S30AVP M5M51008CFP PC133 registered reference design Toshiba 512 NAND MLC FLASH BGA
2000 - sandisk micro sd card pin

Abstract: MCP 1Gb nand 512mb dram 130 256K x 16 DRAM FPM cross reference ulsi 02bjxx L7103 PC133 registered reference design MCP 1Gb 512Mb 130 TSOP 48 Package nand memory toshiba Mitsubishi ECL Memory
Text: Wafer process Cell type Sample (CS) 4Mbit (x8) Low Power SRAM the Third Generation < 5V version> 512k , MITSUBISHI ELECTRIC L-11002-01 CONTENTS 1. General 2. DRAM 3. Low Power SRAM 4. Fast SRAM 5. MCP , PLANNING PRODUCTION DEVELOPMENT MEMORY IC (DRAM, SRAM ,FLASH,MODULE,PC CARD) DIV. SYSTEM LSI (MCU,ASIC , ·MCU ,MPU ·ASIC ·eRAM SAIJO FACTORY ·MCU ·ASIC ·eRAM KOCHI FACTORY ·MCU ,MPU ·ASIC · SRAM FUKUOKA SEMICONDUCTORS FACTORY EUROPEAN FACTORY MSE · SRAM ·FLASH ·MCU (DESIGN) KITA-ITAMI ·OPT


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PDF L-11002-01 L-11003-0I sandisk micro sd card pin MCP 1Gb nand 512mb dram 130 256K x 16 DRAM FPM cross reference ulsi 02bjxx L7103 PC133 registered reference design MCP 1Gb 512Mb 130 TSOP 48 Package nand memory toshiba Mitsubishi ECL Memory
2008 - Not Available

Abstract: No abstract text available
Text: AutoStoreTM on power down RECALL to SRAM initiated by software or power up Infinite read, write , QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite , cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the , . 20 year data retention Single 5V +10% operation Commercial and Industrial temperatures


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PDF CY14E102L, CY14E102N 8/128K CY14E102L) CY14E102N) CY14E102L/CY14E102N
2008 - TSOP 48 thermal resistance

Abstract: TSOP 54 Package TSOP 54 PIN 44TSOP
Text: AutoStore® on power down RECALL to SRAM initiated by software or power up Infinite read, write , QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides infinite , . Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the , . 20 year data retention Single 5V +10% operation Commercial and industrial temperatures


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PDF CY14E104L/CY14E104N 8/256K CY14E104L) CY14E104N) CY14E104L/CY14E104N TSOP 48 thermal resistance TSOP 54 Package TSOP 54 PIN 44TSOP
2008 - CY14E104N

Abstract: No abstract text available
Text: reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile , the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are , power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 5V +10% operation Commercial and


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PDF CY14E104L/CY14E104N 8/256K CY14E104L/CY14E104N CY14E104N
2008 - Not Available

Abstract: No abstract text available
Text: down RECALL to SRAM initiated by software or power up Infinite read, write, and recall , , producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles , the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both , retention Single 5V +10% operation Commercial and industrial temperatures 48-pin FBGA


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PDF CY14E108L, CY14E108N 1024K 8/512K CY14E108L) CY14E108N) CY14E108L/CY14E108N
2008 - Not Available

Abstract: No abstract text available
Text: reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the , restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL , AutoStoreTM on power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 5V +10% operation Commercial and


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PDF CY14E102L, CY14E102N 8/128K CY14E102L/CY14E102N
2008 - Not Available

Abstract: No abstract text available
Text: AutoStore® on power down ■RECALL to SRAM initiated by software or power up ■Infinite read , QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides infinite , . Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the , – 200,000 STORE cycles to QuantumTrap ■20 year data retention ■Single 5V +10%


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PDF CY14E104L/CY14E104N 8/256K CY14E104L) CY14E104N) CY14E104L/CY14E104N
2008 - Not Available

Abstract: No abstract text available
Text: down RECALL to SRAM initiated by software or power up Infinite read, write, and recall , , producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles , the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both , retention Single 5V +10% operation Commercial and industrial temperatures 48-pin FBGA


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PDF CY14E108L, CY14E108N 1024K 8/512K CY14E108L) CY14E108N) CY14E108L/CY14E108N
1996 - 5v sram 4mb 54pin

Abstract: 5v sram tsop54 elbh STK14EC16
Text: Access and R/W Cycle Time The Simtek STK14EC16 is a 4MB fast static RAM with a non-volatile Quantum , to SRAM on Power Up The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM . Data transfers automatically to the non-volatile storage , to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under , Retention · Single 3.0V +20%, -10% Operation · Commercial, Industrial Temperatures · 44-pin or 54-pin 400


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PDF STK14EC16 256Kx16 STK14EC16 48-pin ML0061 5v sram 4mb 54pin 5v sram tsop54 elbh
1998 - TAG 9109

Abstract: M35080 M95256 equivalent TSOP48 outline TSOP40 NVRAM 1KB "dual access" "nonvolatile memory" -RFID EEPROM 16MB M29F001 ST1335
Text: , 5V supply Size 1Mb 2Mb 4Mb 8Mb 16Mb Ref M29F001T M29F001B M29F010 M29F100T M29F100B , ) SRAM , 100-120ns Size 2Mb 4Mb 8Mb Description 2Mb Flash memory and 64Kb EEPROM 4Mb Flash , as M48T129Y above. 4Mb M48T512Y 4Mb (x8), 70ns, 5V ±10%, 10 year battery M48T512V 4Mb (x8), 85ns, 3.3V ±10%, 10 year battery M48T513Y 4Mb (x8), 70ns, 5V ±10%, 10 year battery,Watchdog, Reset Output , 4Mb M48Z512A 4Mb (x8), 70/85ns, 5V +10/-5%, 10 year battery M48Z512AY 4Mb (x8), 70/85ns, 5V ±10%


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PDF 286-CJ103 TAG 9109 M35080 M95256 equivalent TSOP48 outline TSOP40 NVRAM 1KB "dual access" "nonvolatile memory" -RFID EEPROM 16MB M29F001 ST1335
2001 - KM62256BLG-7

Abstract: K6R4016V1C-FI12 IS62LV1024LL-70T1 K6R4016V1C-TI10 K6R1016C1C-TC12 K6R4008V1C-JC12 MT58L32L32PT-7.5 GVT72024A8J-10L K6R4016V1C-FI10 KM62256BLG7
Text: ) 5v Async. 2 - [Cypress] ISSI SRAM Cross Reference Important: please read disclaimer on last , also offers sTSOP] 1Mb (128K x 8) 5v Async. *[ISSI also offers sTSOP] 4Mb (256K x 18) 3.3v Sync. 4Mb , (256K x 18) 3.3v Sync. Pipelined 4Mb (256K x 18) 3.3v Sync. Pipelined 12 - [Cypress] ISSI SRAM , ISSI SRAM Cross Reference Important: please read disclaimer on last page Cypress P/N ISSI P/N , Async. 1Mb (128K x 8) 5v Async. 1Mb (128K x 8) 5v Async. 1Mb (128K x 8) 5v Async. 1Mb (128K x 8) 5v


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PDF C7C1334-10AC IS61NW6432-8TQ C7C1334-5AC IS61NW6432-5TQ IS61NW6432-6TQ, C7C1334-7AC IS61NW6432-7TQ C7C1335-5 IS61C632A-5TQ C7C1335-7AC KM62256BLG-7 K6R4016V1C-FI12 IS62LV1024LL-70T1 K6R4016V1C-TI10 K6R1016C1C-TC12 K6R4008V1C-JC12 MT58L32L32PT-7.5 GVT72024A8J-10L K6R4016V1C-FI10 KM62256BLG7
2008 - TSOP 54 PIN

Abstract: TSOP 54 Package CY14B104L CY14B104N
Text: ® on power down RECALL to SRAM initiated by software or power up Infinite read, write , QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite , cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the , temperatures 48-pin FBGA and 44/ 54-pin TSOP - II packages Pb-free and RoHS compliance Logic


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PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N TSOP 54 PIN TSOP 54 Package CY14B104L CY14B104N
2000 - TSOP32 FOOTPRINT

Abstract: SOH28 PCB FOOTPRINT NVRAM 1KB M41T81 M48Z129Y M48Z129V M48Z128Y M48Z128V M48Z128 M48T18
Text: (x8), 70ns, 3V Low Power SRAM 4Mb (x8), 70ns, 5V Low Power SRAM 1Mb (x8), 70ns, 3V Low Power SRAM , to 16 Kbit SRAM with battery backup, for 3.3V and 5V supplies, through hole or surface mounting. · TIMEKEEPER - 4 Mbit to 1 Kbit SRAM with battery backup, for 3.3V and 5V supplies. Additional features , /-5%, 10 year battery 4Mb (x8), 85ns, 3.3V ±10%, 10 year battery* 4Mb (x8), 70/85ns, 5V ±10%, 10 year battery* 4Mb (x8), 70/85ns, 5V +10/-5%, 10 year battery 1Mb (x8), 85ns, 3.3V ±10%, 10 year


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PDF NL-5652 FLNVRAM/1000 TSOP32 FOOTPRINT SOH28 PCB FOOTPRINT NVRAM 1KB M41T81 M48Z129Y M48Z129V M48Z128Y M48Z128V M48Z128 M48T18
2008 - Not Available

Abstract: No abstract text available
Text: reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the , restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both STORE and RECALL operations , AutoStoreTM on power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall , Commercial, Industrial and Automotive temperatures 48-pin FBGA, 44 and 54-pin TSOP II packages Pb-free and


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PDF CY14B102L, CY14B102N 8/128K CY14B102L/CY14B102N
1998 - toshiba toggle mode nand

Abstract: TC518128 TC518129 TC551001 equivalent 551664 TC518512 Toggle DDR NAND flash sgs-thomson power supply jeida 38 norm Toshiba NOR FLASH
Text: 5V 256K / 1M / 4M SRAM 120 - 150ns (2.7V) 1M / 2M SRAM 3V 85ns (2.7V) 1M / 2M / 4M SRAM , SRAM n SRAM PACKAGE SELECTION GUIDE Density 256k 1M Org. x8 x8 VDD 5V 5V 3V DIP 28 32 , ) 5V (4 M SRAM ) 21.35mm 14mm 20mm x8 160mm2 32pin TSOP-1 0.5mm pitch 8.0mm 140mm2 40pin TSOP , -1 0.5mm pitch TSB current package 54pin TSOP-2 0.8mm pitch 57 Standard SRAM n STATIC RAM & , Standard SRAM n TOSHIBA 256K BIT E/R CMOS STATIC RAM FEATURES Single Power Supply Voltage : 5V + 10


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PDF 64M128M 66MHz 100MHz 200MHz) 500/600MHz 800MHz 400MHz 800MHz) X16/X18X32 PhotoPC550 toshiba toggle mode nand TC518128 TC518129 TC551001 equivalent 551664 TC518512 Toggle DDR NAND flash sgs-thomson power supply jeida 38 norm Toshiba NOR FLASH
2008 - ZS20

Abstract: CY14B102N CY14B102L TSOP 48 thermal resistance 54-pin TSOP thermal resistance junction to case
Text: down RECALL to SRAM initiated by software or power up Infinite Read, Write, and Recall , -10% operation Commercial, Industrial and Automotive Temperatures 48-ball FBGA and 44/ 54-pin , 's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the , restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL


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PDF CY14B102L, CY14B102N 8/128K CY14B102L) CY14B102N) 48-ball 44/54-pin ZS20 CY14B102N CY14B102L TSOP 48 thermal resistance 54-pin TSOP thermal resistance junction to case
2001 - HM62

Abstract: Hitachi DSAUTAZ006 16MB SRAM
Text: 512K Revision Blank =1st generation 8Mb C= 0.18µm 4Mb L =Low Power SRAM 16 256 C L TT I 7 SL Z Packing , June 2001 Hitachi Low Power SRAM Description The low power SRAM range from Hitachi offers high performance and low power by employing a leading edge 0.18µm Hi-CMOS process. Both 4Mb and 8Mb , . Package RTSOP STSOP TSOP SOP CSP DIP Speed(ns) Voltage 5V 2.7-3.6V 2.2-3.6V 2.7-3.6V 2.7-3.6V 2.2-3.6V Density 4Mb 4Mb 8Mb 16Mb x8 x16 Part name Availability 55 70 HM628512C In production


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PDF HM628512C HM62V8512C D-85622 HM62 Hitachi DSAUTAZ006 16MB SRAM
2008 - TSOP II 54

Abstract: TSOP 48 thermal resistance junction to case TSOP 48 thermal resistance TSOP 54 thermal resistance
Text: reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the , restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL , pin, or AutoStore® on power down RECALL to SRAM initiated by software or power up Infinite read, write , operation Commercial and industrial temperatures 48-pin FBGA and 44/ 54-pin TSOP - II packages Pb-free and


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PDF CY14B104L, CY14B104N 8/256K CY14B104L/CY14B104N TSOP II 54 TSOP 48 thermal resistance junction to case TSOP 48 thermal resistance TSOP 54 thermal resistance
2007 - TSOP 54 Package

Abstract: TSOP 48 thermal resistance TSOP 54 PIN TSOP 54 Package used in where TSOP II 54 TSOP II 54 Package
Text: elements is initiated by software, device pin or Autostore® on power down · RECALL to SRAM initiated by , incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides , QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the , Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. No


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PDF CY14B104L/CY14B104N 8/256K CY14B104L/CY14B104N to10ns to15ns TSOP 54 Package TSOP 48 thermal resistance TSOP 54 PIN TSOP 54 Package used in where TSOP II 54 TSOP II 54 Package
2008 - Not Available

Abstract: No abstract text available
Text: AutoStore® on power down ■RECALL to SRAM initiated by software or power up ■Infinite read , QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite , cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the , €“10% operation ■Commercial and industrial temperatures ■48-pin FBGA and 44/ 54-pin TSOP - II


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PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N
MPC456

Abstract: No abstract text available
Text: Power Requirements: G + 5V ±5% at 145mA max (+30mA/MB SRAM ) (+8mA/MB Flash) Ordering Information , Drive Add 2MB Flash Add 4MB Flash Add 8MB Flash Add 16MB Flash Add 32MB Flash Delete all SRAM Reduce SRAM to 1MB Increase SRAM to 4MB Micro/sys 3730 Park Place, Montrose, CA 91020 (818)244-4600 , for RAM in 1M blocks  LEDs for disk access, write protect  Optional flash-based option ROM  5V , 4MB Flash EPROM devices. All devices are surface mount type. In systems running under a disk-based


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PDF PC/104 MPC456 PC/104 MPC456 512KB D0000 E0000
1999 - footprint so44

Abstract: 9977 ST1355 TSOP32 FOOTPRINT IC SOCKET TSOP48 52 pin plcc socket ST19GF34 PSDSoft ST19AF08 TSOP48 socket footprint
Text: Memory, Single Supply 5V Size 512Kb 1Mb 2Mb 4Mb 8Mb 16Mb Ref M29F512B M29F010B M29F100BT , ±10%, 10 year battery 1Mb (x8), 70ns, 5V ±10%, 10 year battery, Reset Output, Battery Low Output 4Mb (x8), 70/85ns, 5V +10/-5%, 10 year battery 4Mb (x8), 70/85ns, 5V ±10%, 10 year battery 16Mb (x8 , Power-fail Deselect voltage, controls 1Mb to 4Mb LPSRAM NVRAM Controller, 5V ±10% or 5V +10/-5%, selectable , 1Mb (x8), 55ns, 5V ±10%, with Output Enable 4Mb (x8), 55ns, 5V ±10%, with Output Enable Package


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PDF operat911) D-90449 BRMEMSEL/0699 footprint so44 9977 ST1355 TSOP32 FOOTPRINT IC SOCKET TSOP48 52 pin plcc socket ST19GF34 PSDSoft ST19AF08 TSOP48 socket footprint
2008 - Not Available

Abstract: No abstract text available
Text: down RECALL to SRAM initiated by software or power up Infinite read, write, and recall , , producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles , the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both , -pin FBGA, 44 and 54-pin TSOP II packages Pb-free and RoHS compliance Logic Block Diagram VCC


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PDF CY14B108L, CY14B108N 1024K 8/512K CY14B108L) CY14B108N) CY14B108L/CY14B108N
2008 - CY14B104L

Abstract: CY14B104N
Text: down RECALL to SRAM initiated by software or power up Infinite read, write, and recall , technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and , transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile , during power loss to store data from the SRAM to nonvolatile elements. NC No Connect No Connect


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PDF CY14B104L, CY14B104N 8/256K CY14B104L) CY14B104N) CY14B104L/CY14B104N CY14B104L CY14B104N
Supplyframe Tracking Pixel