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CD4046BNSRE4 CD4046BNSRE4 ECAD Model Texas Instruments CMOS Micropower Phase-Locked Loop 16-SO -55 to 125
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565 PLL pin diagram Datasheets Context Search

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2012 - MO-220-VNND-4

Abstract: adl537x D8P analog devices
Text: Clock Input, Negative. This pin has a secondary function as a synchronization input. PLL Reference Clock , suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital , : ADL5370, ADL537x family IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516 , Diagram . 3 Specifications , .8 Pin Configuration and Function Descriptions.9 Outline Dimensions


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PDF 16-Bit, AD9122-EP AD9122-EP ADL537x 52809-A MO-220-VNND-4 72-Lead CP-72-7) MO-220-VNND-4 D8P analog devices
2002 - 565 pin diagram

Abstract: F562 565 pin dETAILS ocs4 pll 565 565 PLL AF9704 AF9706 microcontroller mb90560 pll 565 application
Text: LQFP 64- pin plastic SH-DIP (FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01) MB90560/ 565 Series , " section for details of each package. 6 × MB90560/ 565 Series s PIN ASSIGNMENTS 64 63 62 61 , /O CIRCUITS" for details of the circuit types. (Continued) 10 MB90560/ 565 Series Pin No , ) 11 MB90560/ 565 Series (Continued) Pin No. QFPM06 LQFPM09 SDIP Pin Name State , (3.3 V) input pin MB90560/ 565 Series s I/O CIRCUITS Type Circuit Remarks X1 Xout Rf


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L F0204 565 pin diagram F562 565 pin dETAILS ocs4 pll 565 565 PLL AF9704 AF9706 microcontroller mb90560 pll 565 application
2002 - 565 PLL

Abstract: DIP-64P-M01 F2MC-16LX FPT-64P-M06 FPT-64P-M09
Text: LQFP 64- pin plastic SH-DIP (FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01) MB90560/ 565 Series , " section for details of each package. 6 × MB90560/ 565 Series s PIN ASSIGNMENTS 64 63 62 61 , /O CIRCUITS" for details of the circuit types. (Continued) 10 MB90560/ 565 Series Pin No , ) 11 MB90560/ 565 Series (Continued) Pin No. QFPM06 LQFPM09 SDIP Pin Name State , (3.3 V) input pin MB90560/ 565 Series s I/O CIRCUITS Type Circuit Remarks X1 Xout Rf


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L F0204 565 PLL DIP-64P-M01 FPT-64P-M06 FPT-64P-M09
2002 - programmable timer

Abstract: FF201
Text: LQFP 64- pin plastic SH-DIP (FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01) MB90560/ 565 Series , " section for details of each package. 6 × MB90560/ 565 Series s PIN ASSIGNMENTS 64 63 62 61 , /O CIRCUITS" for details of the circuit types. (Continued) 10 MB90560/ 565 Series Pin No , ) 11 MB90560/ 565 Series (Continued) Pin No. QFPM06 LQFPM09 SDIP Pin Name State , (3.3 V) input pin MB90560/ 565 Series s I/O CIRCUITS Type Circuit Remarks X1 Xout Rf


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PDF DS07-13715-3E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L programmable timer FF201
2001 - Not Available

Abstract: No abstract text available
Text: for details of each package. 6 DS07-13715-5E MB90560/ 565 Series I PIN ASSIGNMENTS 64 63 , . DS07-13715-5E 9 MB90560/ 565 Series I PIN DESCRIOTIONS Pin No. QFP*3 LQFP*4 SDIP*5 , set as an input port. (Continued) 10 DS07-13715-5E MB90560/ 565 Series Pin No. QFP*3 , VSS power supply input pin for A/D converter. (Continued) DS07-13715-5E 11 MB90560/ 565 , pin only and leave the X1 pin open. DS07-13715-5E 15 MB90560/ 565 Series X0 OPEN X1


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PDF DS07-13715-5E 16-bit F2MC-16LX MB90560/565 MB90561A/562A/F562B/V560/567/568/F568 F2MC-16L
2001 - MB90F562BP

Abstract: DS07-13715-5E 565 PLL MB90560 MB90F562 pll 565 application DIP-64P-M01 F2MC-16LX MB90F562BPMC MB90561APMC
Text: " section for details of each package. 6 DS07-13715-5E MB90560/ 565 Series PIN ASSIGNMENTS 64 , . DS07-13715-5E 9 MB90560/ 565 Series PIN DESCRIOTIONS Pin No. QFP*3 LQFP*4 SDIP*5 , set as an input port. (Continued) 10 DS07-13715-5E MB90560/ 565 Series Pin No. QFP*3 , pin for A/D converter. (Continued) DS07-13715-5E 11 MB90560/ 565 Series (Continued) Pin No , leave the X1 pin open. DS07-13715-5E 15 MB90560/ 565 Series X0 OPEN X1 MB90560/ 565


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PDF DS07-13715-5E 16-bit F2MC-16LX MB90560/565 MB90561A/562A/F562B/V560/567/568/F568 F2MC-16L MB90F562BP DS07-13715-5E 565 PLL MB90560 MB90F562 pll 565 application DIP-64P-M01 MB90F562BPMC MB90561APMC
2001 - DIP-64P-M01

Abstract: F2MC-16LX FPT-64P-M06 FPT-64P-M09 DDR4 jedec FTP-64P-M09
Text: LQFP 64- pin plastic SH-DIP (FPT-64P-M06) (FPT-64P-M09) (DIP-64P-M01) MB90560/ 565 Series , . 6 × MB90560/ 565 Series s PIN ASSIGNMENTS 64 63 62 61 60 59 58 57 56 55 54 53 , .) * : Not support on the MB90F568, MB90567, and MB90568. 9 MB90560/ 565 Series s PIN DESCRIOTIONS , types. (Continued) 10 MB90560/ 565 Series Pin No. QFPM06 LQFPM09 SDIP Pin Name , " for details of the circuit types. (Continued) 11 MB90560/ 565 Series (Continued) Pin No


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PDF DS07-13715-2E 16-bit F2MC-16LX MB90560/565 MB90561/561A/562/562A/F562/F562B/V560 MB90567/568/F568 F2MC-16L DIP-64P-M01 FPT-64P-M06 FPT-64P-M09 DDR4 jedec FTP-64P-M09
2001 - Not Available

Abstract: No abstract text available
Text: DS07-13715-5E MB90560/ 565 Series ■PIN ASSIGNMENTS 64 63 62 61 60 59 58 57 56 55 54 , MB90560/ 565 Series ■PIN DESCRIOTIONS QFP*3 LQFP*4 SDIP*5 State/ Circuit Pin Function *1 , input port. (Continued) 10 DS07-13715-5E MB90560/ 565 Series Pin No. QFP*3 LQFP*4 , converter. (Continued) DS07-13715-5E 11 MB90560/ 565 Series (Continued) Pin No. QFP*3 LQFP*4 , , however, cannot be guaranteed. 18 DS07-13715-5E MB90560/ 565 Series ■BLOCK DIAGRAM X0, X1


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2013 - MO-220-VNND-4

Abstract: No abstract text available
Text: current output. 3.3 V Analog supply. PLL reference clock input, Negative. This pin has s secondary function as a synchronization input. PLL reference clock input, Positive. This pin has s secondary , -55°C to +105°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is , logo Pin 1 identifier ESDS identification (optional) Stresses beyond those listed under , . The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram . The


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PDF 16-BIT, V62/12654 5962-V036-13 V62/12654-01XE AD9122SCPZ-EP MO-220-VNND-4
AM DEMODULATOR USING PLL 565

Abstract: NE565 PLL CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 AM DEMODULATOR USING ne565 circuit diagram ne565 PLL NE565 Signetics NE565 565 PLL pin diagram Signetics 565
Text: Signetics AN 183 Circuit Description of the NE565 PLL Application Note Linear Products CIRCUIT DESCRIPTION OF THE NE565 PLL The 565 is a general purpose PLL designed to operate at frequencies , counter for frequency m ultiplication applications. W ith the 565 , it is also possible to break the toop , diagram of the VCO is show n in Figure 1. If is the charging current created by the application o f the , utput o f the Schm itt trigger. The com ple te circuit for the 565 is show n in Figure 2. T ransistors Q


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PDF NE565 AN183 AM DEMODULATOR USING PLL 565 NE565 PLL CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 AM DEMODULATOR USING ne565 circuit diagram PLL NE565 Signetics NE565 565 PLL pin diagram Signetics 565
EWM 1000

Abstract: 902750 902950 EWM-900-FDTC-HS pll 564 EWM-900-FDTC-BS 50E3 wireless audio transmitter receiver schematic PLL FSK DEMODULATOR 9600 baud pll 564 schematic
Text: response on this pin due to the TX PLL loop filter. Therefore, the transmitter is not capable of , required Simple serial programming interface RSSI Figure 2. Pin-Out Diagram Rev Date 9/13/01 1 , p-p deviation 50 ohm load Pin Description Pin Number Name Description 1 GND , AUDIO Receive audio output. 8 LNAEN LNA control input. The LNA is on when this pin is high and off when this pin is low. Do not let this pin float. 9 GND Transceiver ground. Connect


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PDF EWM-900-FDTC 902-928MHz EWM-900-FDTC EWM 1000 902750 902950 EWM-900-FDTC-HS pll 564 EWM-900-FDTC-BS 50E3 wireless audio transmitter receiver schematic PLL FSK DEMODULATOR 9600 baud pll 564 schematic
CH8398

Abstract: CH8398A STG1703 TQD4133 stg170
Text: for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68- pin PLCC 5V , . 1 Pinout Diagram CH8398A .4 Pin Description , triple 256 x 6-bit palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398A pixel bus


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PDF CH8398A 16-bit ATT20C498 T004133 CH8398 CH8398A STG1703 TQD4133 stg170
7S1 zener diode

Abstract: CH8398 STG1703 gi 9440 diode stg170
Text: features for "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68- pin , .4-27 Pinout Diagram CH8398 . 4-30 Pin , unused bit P[i] = pixel input pin Secondary Mode: 16B1P2C: 16 bpp ( 5-6-5 ), 1 pixel data, 2 PCLK cycles , input pin Secondary Mode: 16B1P1C: 16 bpp ( 5-6-5 ), 1 pixel data, 1 PCLK cycle, 64K colors Pixel data


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PDF CH8398 16-bit ATT20C498 CH8398 7S1 zener diode STG1703 gi 9440 diode stg170
gi 9440 diode

Abstract: CH8398 STG1703 7S1 zener diode
Text: "Green PC" applications Anti-sparkle circuitry Dual-programmable 135 MHz PLL clocks On-chip loop filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68- pin PLCC 5V , .4-27 Pinout Diagram CH8398 . 4-30 Pin Description , bits per pixel X = unused bit P[i] = pixel input pin Secondary Mode: 16B1P2C: 16 bpp ( 5-6-5 ), 1 pixel , pixel input pin Secondary Mode: 16B1P1C: 16 bpp ( 5-6-5 ), 1 pixel data, 1 PCLK cycle, 64K colors Pixel


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PDF CH8398 16-bit ATT20C498 D0023E gi 9440 diode STG1703 7S1 zener diode
PLL IC 565

Abstract: for PLL IC 565 565 PLL pin diagram lock range of 565 PLL IC 0420 LOP pll 565 FO56 16G041-HD CERAMIC LEADLESS CHIP CARRIER 16G041-HA
Text: °C operating temperature range 1 Patented, self-acquiring PLL GaAs IC design ■Available in standard frequencies: 100,155.52, 250, 565 , and 622.08 Mbit/s. Custom frequencies available upon request. • PLL , (GBLj GigaBit Logic 16G041-H Low Power, PLL Clock & Data Recovery Circuit 100 to 625 Mbit/s , -H integrates GigaBit's 16G041 PLL clock and data recovery GaAs IC together with a high performance loop filter and other components to realize a complete, 3-terminal (data in, clock and data out) PLL clock


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PDF 16G041-H PLL IC 565 for PLL IC 565 565 PLL pin diagram lock range of 565 PLL IC 0420 LOP pll 565 FO56 16G041-HD CERAMIC LEADLESS CHIP CARRIER 16G041-HA
2008 - CAMERA PARALLEL RGB TO MIPI CSI-2

Abstract: MIPI CSI-2 Parallel mipi csi-2 receiver MIPI csi-2 MIPI csi mipi csi receiver RGB TO MIPI cSI2 MIPI CAMERA automotive RGB to CSI-2 MIPI CSI-2 to Parallel
Text: pins February 2008 20- pin socket Description ITU-R BT.656-4 YUV (YCbCr) 4:2:2, RGB 565 , AVDD AGND ISP System diagram Readout Y Decoder Serial Ctrl. Receiver PLL and Clock , option (VS6735) Two-wire serial control interface On-chip PLL , 6 to 27 MHz clock input , integrated PLL allows for low frequency system clock, and flexibility for successful EMC integration. This , . 1/5 www.st.com 5 Overview Overview Figure 1. VS6725 application diagram Figure 2


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PDF VS6725 VS6735 VS6725: VS6735: 1600H 10-bit VS6735) CAMERA PARALLEL RGB TO MIPI CSI-2 MIPI CSI-2 Parallel mipi csi-2 receiver MIPI csi-2 MIPI csi mipi csi receiver RGB TO MIPI cSI2 MIPI CAMERA automotive RGB to CSI-2 MIPI CSI-2 to Parallel
frequency shift keying using pll 565

Abstract: 565 PLL AM DEMODULATOR USING PLL 565 565 PLL pin diagram pll 565 as an fsk demodulator fsk demodulator using pll 565 Signetics NE565 CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 NE565 NE565D
Text: Diagram . The center frequency of the PLL is determined by the free-run ning frequency of the VCO; this , the VCO. Because of its unique and highly linear VCO. the 565 PLL can lock to and track an input , The NE/SE565 Phase-Locked Loop ( PLL ) is a self-contained, adaptable filter and demodulator for the , adjustable over 10 to 1 range with same capacitor PIN CO NFIGURATIO NS F, N Packages VCO OUTPUT [ T , [I U NC 7 1 OEMODULATED -' OUTPUT NOTE: 1. SO non-standard pin out. APPLICATIONS ·


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PDF NE/SE565 NE/SE565 001Hz 500kHz. 67kHz frequency shift keying using pll 565 565 PLL AM DEMODULATOR USING PLL 565 565 PLL pin diagram pll 565 as an fsk demodulator fsk demodulator using pll 565 Signetics NE565 CIRCUIT DIAGRAM OF AM DEMODULATOR USING PLL 565 NE565 NE565D
Signetics NE561

Abstract: AM DEMODULATOR USING PLL 565 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco Signetics NE565 UA711 NE561N
Text: of a single external component. Signetics makes three basic classes of single-chip PLL circuits', the general pur pose PLL , the PLL with an added m ultiplier and the PLL tone decoder. The 560N. 562N and 565 , voltagecontrolled oscillator fVCO! in the feedback path. The block diagram of a basic PLL system is shown in Figure , synchronous reception o f radio signals using PLL techniques was de scribed (Ref. 1) in the early thirties , of transistors. This com plexity made PLL techniques im practical or uneconomi cal in the m ajority


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PDF 200Hz. Signetics NE561 AM DEMODULATOR USING PLL 565 SIGNETICS PLL ne561 NE561 signetics Signetics NE562 566 vco Signetics NE565 UA711 NE561N
565 PLL pin diagram

Abstract: PLL IC 565 PLL pSK DEMODULATOR psk demodulation DIP20 S020 TDA7331 TDA7331D 57KHz rds decoder
Text: decoder (microprocessor). BLOCK DIAGRAM The device operates in accordance with the EBU (European , 57KHz PLL , BI-PHASE PSK decoder, differential decoding circuit, ARI indication and RDS signal quality , V Tod Operatinq Temperature Ranqe -40 to 85 °c Tstq Storage Temperature -35 to 125 °c PIN FUNCTION N° pin Name Description 1 MPX RDS input signal 2 VREF Reference voltage 3 OSEL Oscillator selector pin : - open, closed to VCC = quartz oscillator - closed to GND = external driven 4 FILOUT Filter


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PDF TDA7331 57KHz 332MHz 328MHz DIP20 TDA7331 TDA7331D 565 PLL pin diagram PLL IC 565 PLL pSK DEMODULATOR psk demodulation DIP20 S020 TDA7331D rds decoder
Not Available

Abstract: No abstract text available
Text: , a smoothing filter and cross detector, a bit rate clock recovery circuit, a 57KHz PLL , BI-PHASE , DIAGRAM January 1997 1 /7 This is prelim inary information on a new product now in developm ent , Operatinq Temperature Ranqe Storage Temperature PIN FUNCTION N° pin 1 2 3 Name MPX VREF OSEL , Reference voltaqe Oscillator selector pin : - open, closed to VCC = quartz oscillator - closed to GND = , Oscillator input Testing output pin : 57kHz clock output RDS clock output 1187.5Hz RDS data output Output


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PDF TDA7331 57KHz 332MHz 328MHz TDA7331 outp000
2005 - PLL IC 566

Abstract: PLL IC 565 IC 566 function generator tb31223 application of IC 566 function generator PLL 566 TDA 8223 A pll 565 application datasheet for PLL IC 565 s358m
Text: Note: EM78567/566/ 565 Changed the POVD voltage from 1.6V to 2.0V Added 48- pin TQFP package Modified , change without further notice) EM78567/566/ 565 8-BIT Microcontroller 4 Pin Configuration , further notice) EM78567/566/ 565 8-BIT Microcontroller 5 Functional Block Diagram Xin Xout ROM , to change without further notice) ·5 EM78567/566/ 565 8-BIT Microcontroller 6 Pin , EM78567/566/ 565 8-BIT Microcontroller Product Specification DOC. VERSION 1.4 ELAN


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PDF EM78567/566/565 EM78P567 ICE567 PLL IC 566 PLL IC 565 IC 566 function generator tb31223 application of IC 566 function generator PLL 566 TDA 8223 A pll 565 application datasheet for PLL IC 565 s358m
2004 - Mobile Camera Module

Abstract: 55560-0201 PLL IC 565 565RGB FPC CONNECTOR 20pin 20 fpc digital camera CMOS Camera Module connector mobile camera cmos camera module VS6524P02S
Text: to QVGA, QQVGA and subQCIF ITU-R BT.656-4 YUV (YCbCr) 4:2:2 with embedded syncs, RGB 565 , RGB , syncs, 24 MHz clock Two-wire serial control interface On-chip PLL , 6.5 to 27 MHz clock , as a 2.8 V single supply camera or as a 1.8 V / 2.5 V supply camera. The integrated PLL allows for , /3 VS6524 Figure 1. Application Diagram Table 1. Technical Specifications Video Interface , MHz typ. (on-chip PLL ) Power consumption VS6524 VGA Mobile Camera Module 8-bit parallel


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PDF VS6524 10-bit 10-without Mobile Camera Module 55560-0201 PLL IC 565 565RGB FPC CONNECTOR 20pin 20 fpc digital camera CMOS Camera Module connector mobile camera cmos camera module VS6524P02S
565 PLL pin diagram

Abstract: PLL 566 Signetics NE566 vco 566 NE566 application note pll 565 application NE566 triangle wave vco 566 566 pin diagram 566 vco
Text: CIRCUIT DESCRIPTION OF THE 566 PLL The 566 is the voltage-controlled oscillator portion of the 565 . The basic die is the same as that of the 565 ; modified metalization is used to bring out only the VCO. The 566 circuit diagram is shown in Figure 1. Transis tor Q ie provides a buffered triangle waveform output. (The triangle waveform is available at capacitor Ci also, but any current drawn from Pin 7 will alter the duty cycle and frequency.) The square wave output is available from by Pin 4. The circuit


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PDF NE566 565 PLL pin diagram PLL 566 Signetics NE566 vco 566 NE566 application note pll 565 application NE566 triangle wave vco 566 566 pin diagram 566 vco
565 PLL

Abstract: fsk demodulator using pll 565 pll 565 as an fsk demodulator AM DEMODULATOR USING PLL 565 566 VCO frequency shift keying using pll 565 vco 566 565 PLL pin diagram NE565 ne565n
Text: unique and highly linear VCO, the 565 PLL can lock to and track an input signal over a very wide , Loop ( PLL ) is a self-contained, adaptable filter and dem odulator for the frequency range from 0.001Hz , knearity, a phase comparator, an amplifier and a low pass filter as shown in the Block Diagram . The center frequency of the PLL is determined by the free-run ning frequency of the VCO; this frequen cy can be , same capacitor PIN CONFIGURATIONS F, N Packages COMMUMTOM r r VCO INPUT _ R £F E R S *C f ( T


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PDF NE/SE565 NE565 SE565 001Hz 500kHz. 200pp 300mV, 000i2. 67kHz 565 PLL fsk demodulator using pll 565 pll 565 as an fsk demodulator AM DEMODULATOR USING PLL 565 566 VCO frequency shift keying using pll 565 vco 566 565 PLL pin diagram ne565n
565 PLL pin diagram

Abstract: STG1703 CH8398A supervga pll 565
Text: filters for PLL clocks Pin compatible to SGS-Thomson STG1703 Low power CMOS technology in 68- pin PLCC , -bit palette RAM, and a triple 8-bit 110/135 MHz video DAC. The video clock PLL provides 16 programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398A pixel bus is 16 bits , driver software can initialize the PLL RAM entries to the desired values. MIX-COLOR® mode provides the , /256 pseudo-color mode to be mixed with 64K color 5-6-5 or 32K color 55-5 bypass. Mixed mode switching


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PDF CH8398A 16-bit CH8398A STG1703 68-pin 565 PLL pin diagram STG1703 supervga pll 565
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