The Datasheet Archive

Top Results (2)

Part Manufacturer Description Datasheet Download Buy Part
ASDMPC-65.536MHZ-LR-T Abracon Corporation XO, Clock, 2.3MHz Min, 170MHz Max, 65.536MHz Nom, CMOS,
ASVMPC-65.536MHZ-LR-T Abracon Corporation XO, Clock, 2.3MHz Min, 170MHz Max, 65.536MHz Nom, CMOS,

Search Stock (13)

  You can filter table by choosing multiple options from dropdownShowing 13 results of 13
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
15,36MHZ 10PF Chip One Exchange - -
1536MHZ Chip One Exchange - -
ABM3-19.3536MHZ-T Abracon Corporation Chip1Stop 1,000 $0.80 $0.58
ASDMPC-65.536MHZ-LR-T Abracon Corporation Sager - -
ASDMPC-65.536MHZ-LR-T Abracon Corporation Allied Electronics & Automation 0 $1.09 $1.04
ASDMPC-65.536MHZ-LR-T Abracon Corporation Avnet 0 $0.85 $0.78
ASV-65.536MHZ-CS-T Abracon Corporation Future Electronics 0 $0.91 $0.91
ASV-65.536MHZ-L-K-S-T Abracon Corporation Future Electronics 0 $0.99 $0.99
ASVMPC-65.536MHZ-LR-T Abracon Corporation Sager - -
ASVMPC-65.536MHZ-LR-T Abracon Corporation Avnet 0 $0.88 $0.81
FCX-05 36MHZ 7PF/+-30PPM River Eletec Corp Chip1Stop 23 $2.29 $1.18
HSM53-0665.536MHZ Unknown Bristol Electronics - -
MP-1-6.5536MHZ MtronPTI Master Electronics 722 $0.72 $0.69

No Results Found

536MH Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract:
Text: =1 5.36MHz A|N=1 5.36MHz A|n =15.36MHz NOTES 1. An input voftage of 0.0 volts ±0.5 LSB should


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PDF DS4062 PCA869 60MHz PCA869 37bfl522
B23SL

Abstract:
Text: No file text available


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PDF S235b05 010720b B23SL
opcode table for 8086 microprocessor

Abstract:
Text: INPUT OUTPUT NOMAL MODE OUTPUT OUTPUT OUTPUT 28 TDIO I/O 1, 536MHz CLOCK: · A t MASTER MODE


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PDF HD81501A opcode table for 8086 microprocessor
S6B33D1

Abstract:
Text: : 1452-1492) • Channel Bandwidths - DVB-H/T 5, 6, 7, and 8MHz -T-DMB, DAB(-IP) 1, 536MHz - ISDB-T 430kHz and


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PDF S3C2413 S3C2412 S3C2443 S3C6400 S5M8602/S3C4F31 S6B33D1 S6B33B6 S6D0164 LCD TV Samsung regulator S6D0154 S6B33BG electronic rolling display amoled driver
dmo 365 rb

Abstract:
Text: FSb BCLK MASTER MODE (BCLK = 1, 536MHz ) MASTER MODE ^ SCS-THOMSON M icnoHJECvnoaDcs 7351b


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PDF PLCC44 350mW 18KFT 26AWG/24AWG 7T2TE37 D732bc dmo 365 rb hybrid ic FBA 1001 1000 fba hybrid buk 457 equivalent dmo 365 r g0732 m43r N33S
HC4551

Abstract:
Text: . Input frequency can be selected as 2.048MHz, 1 544MHz or 1, 536MHz 13 17 PDN The input pin


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PDF HC-5512D HC4-5512D 50/60HZ HC4551
1998 - D03B

Abstract:
Text: /section #1 and #2 Inserted in the testboard D03B; pass bandwidth: - 3 dB 5.36MHz ; -30 dB 6.24MHz


Original
PDF X6850K X6850K, X6850K 64kHz 81MHz: 23MHz: 31MHz: D03B
0A95

Abstract:
Text: NUMBER 35 36 34 38 94 95 DESCRIPTION Codec frame sync. 8 KHz Codec master clock. 1, 536MHz Codec data


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PDF MX93022A MX93022A 100-PIN 0A95 DB37M
mu 250 mikro

Abstract:
Text: Data Sheet AS35116 PCM CONFERENCE CIRCUIT General Description Key Features Up to 10 Independent Conferences for Up to 32 Channels PCM Serial Interface (1, 536MHz , 1,544MHz, 2.048MHz) Parallel Microprocessor Control Interface Transparent Mode and Conference Modes Digital Gain Setting Function (0/-3/-6 dB) Tone Generator Input For Signal Tone Injection Pin Selectable A/p Law Format Open Drain PCM Output Low Power CMOS Technology +5V Power Supply An additional feature is an input for an


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PDF AS35116 536MHz, 544MHz, 048MHz) mu 250 mikro
tsl 337

Abstract:
Text: , 536MHz clock in DPLL. 30 ABIT/VDET I ABITSET/VDET: • At MASTER MODE, input pin for activation of layerl


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PDF HD81501 192kb/s tsl 337 opcode table for 8086 microprocessor 6809 8086 DMA cmos serie 4000 I16KBI JRS232C TACT SWITCH lsw
CD22354A

Abstract:
Text: leading edge may be a logic input which selects either 1, 536MHz / 1,544MHz or 2.048MHz for Master Clock in , , 536MHz , 1,544MHz or 2.048MHz. May be asynchronous with MCLKX, but best performance is realized from , be 1, 536MHz , 1,544MHz or 2.048MHz. May be asynchronous with MCLKr , but best performance is realized


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PDF CD22354A, CD22357A CD22354A CD22357A 64kHz 048MHz, CD22354AE
2952 controller

Abstract:
Text: 1.544 or 1, 536MHz 2952 CLK Clock 3= 2.048MHz Trc Tfc Rise, Fall Times, SCL 50 ns Tro tfd Rise, Fall


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PDF 29C48 29C48 2952 controller 2952 29C44 29C53 PDI Gain Setting PUB43801 Ringing Subscriber Line Interface Circuit NXP
Not Available

Abstract:
Text: °C and for nominal Master clock frequency MCLK = 1, 536MHz and oversampling ratio = 160. Absolute , Typical values are given for A V d d = 3 V , T amb = 25°C and for nominal master clock MCLK = 1, 536MHz , values are given for A V d d = 3 V , Tamb = 25°C and for nominal master clock MCLK = 1, 536MHz


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PDF STLC7550 34bis 56Kbps 16-BIT 45kHz
1997 - KT8557

Abstract:
Text: /1.544MHz or 2.048MHz clock input available. 9 MCLKX 10 BCLKX Must be1. 536MHz /1.544MHz or


Original
PDF KT8554B/7B 16-CERDIP KT8554B/7B 600ohm 77459Vrms 100Kohm, 048MHz KT8557 MLX9
CVSD

Abstract:
Text: (See Table 1 below). table 1. bclkr/clksel hc-5557 hc-5552/53/54 Clock 2.048MHz 1.544/1, 536MHz Low , must be 2.048MHz for HC-5557 (A law) and 1.544 or 1, 536MHz for HC-5552/53/54 (ft law) (freq MCLKx =


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PDF HC-5552/53 HC-5554/57 HC-5552 HC-5553 HC-5554 HC-5557 HC-5502A, HC-5504, HC-5508 CVSD design a 60hz notch filter HC-55564
2012 - 514MH

Abstract:
Text: 9.5 nH 518MHz ~ 527MHz 9.0 nH 527MHz ~ 536MHz 8.7 nH 536MHz ~ 553MHz 8.2 nH 553MHz ~ 573MHz , 9.0 nH 527MHz ~ 536MHz 8.7 nH 536MHz ~ 553MHz 8.2 nH 553MHz ~ 573MHz 7.5 nH 573MHz ~ 593MHz


Original
PDF PL560-08 600MHz PAN1201051 5-Jan-12 KD-VB0F48 PL560-08DC 600MHz. 272MHz 514MH IT2105FE-33.600MHz
CD22354A

Abstract:
Text: selects either 1, 536MHz / 1,544MHz or 2.048MHz for Master Clock in synchronous mode and BCLKX is used for both transmit and receive directions. 8 MCLKr/PDN Receive Master Clock. Must be 1, 536MHz , 1,544MHz or , 2.048MHz and for the CD22354A must be 1, 536MHz or 1.544MHz. These clocks need not be synchronous. However


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PDF CD22354A, CD22357A 64kHz. 128kHz CD22354A CD22354AE CD22357A CD22357AE
Not Available

Abstract:
Text: train. 6 dr 7 BCLKr/ CLKSEL Logic input which selects either 1, 536MHz /1.544MHz or


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PDF KT8554/7 KT8554/7 300Hz 3400Hz, 40dBm0 KT8554 KT8557 600ohm 100Kohm,
Not Available

Abstract:
Text: FSb BCLK mi ini MASTER MODE (BCLK = 1, 536MHz ) MASTER MODE 19/74 STLC5412 Figure 4c


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PDF STLC5412 DIP28 PLCC44 STLC5412FN 18KFT G/24AW
Not Available

Abstract:
Text: °C and for nominal M aster clock frequency MCLK = 1, 536MHz and oversampling ratio = 160. ABSOLUTE , = +5V, T amb = 25°C and for nominal master clock MCLK = 1, 536MHz , differential mode and , MCLK = 1, 536MHz , differential mode and oversampling ratio = 160. Measurement band = DC to 0.425 x


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PDF 34bis) 34bis 16-BIT 45kHz 88MHz TQFP44A
Not Available

Abstract:
Text: 64kHz to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1, 536MHz , receive directions. 8 MCLK r/PDN Receive Master Clock. Must be 1, 536MHz , 1,544MHz or 2.048MHz , , 536MHz , 1,544MHz or 2.048MHz. May be asynchronous with MCLK r , but best performance is realized from


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PDF CD22354A, CD22357A CD22354A CD22357A
5040a

Abstract:
Text: the filter to operate with 2.048MHz, 1.544MHz or 1, 536MHz clock frequencies. By connecting the


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PDF ETC5040 ETC5040A 50/60HZ DIP16 ETC5040J ETC5040AJ ETC5040/ETC5040A double1031 DIP-20 -i-U54 5040a Flexiwatt
Not Available

Abstract:
Text: clock MCLK = 1, 536MHz , differential mode and oversampling ratio = 160. Measurement band = DC to 0.425 x , Typical values are given for AV dd = +5V, Tamb = 25°C and for nominal master clock MCLK = 1, 536MHz


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PDF ST7546 16-BIT 45kHz 88MHz 200mVpp
siemens isdn nt1

Abstract:
Text: interface. TEs ][ ][ IOM-2, 1, 536MHz , TIC-Bus S-transceiver D -channel a rbitra tio n PEB 8191 , allows building of a small PBX. s TEs II II IOM-2, 1, 536MHz S-transceiver Switching & Loops


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PDF PEF8191 T8191-XV11-01-7600 500hm 980hm) ---40-IO CI64x~ siemens isdn nt1 36A4 PEB 2466 PEB8091 PEB8191
Not Available

Abstract:
Text: No file text available


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PDF DIP28 LCC44 PLCC44 18KFT 26AWG/24AWG STLC5411
Supplyframe Tracking Pixel