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528-byte Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1999 - SMFV004

Abstract: SMFV008 SMFV016
Text: Program : (512 + 16) Byte - Block Erase : (8K + 256) Byte - Status Register · 528-Byte Page Read , the 528-byte page in typically 250µs and an erase operation can be performed in typically 2ms on an , Cell Array : (8M + 256K)bit x 8bit - Data Register : (512 + 16)bit x 8bit · 528-Byte Page Read , operation programs the 528-byte 16M x 8 Bit SmartMediaTM Card ·Single 2.7V~3.6V Supply ·Organisation - , the 528-byte Future Electronics · Command Register Operation · 22 pad SmartMedia TM (SSFDC


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PDF SMFV004/008/016 528-Byte SMFV004 16K-byte SMFV004 SMFV008 SMFV016 SMFV008 SMFV016
1998 - 25f080

Abstract: 25F160 32 megabit serial flash transistor ba15 25F08 25F320 0000-037F 32M Nonvolatile SRAM NXSF029A-1201 NX25F160C
Text: 528-byte SRAM Buffers - Byte-level addressing - Transfer and Compare sector to SRAM - Configurable , , to be read without having to clock an entire 528-byte sector out of the device. In most cases data is read through one of two 528-byte SRAM buffers by using the Transfer Sector to SRAM and Read SRAM , transfers the contents of a specified 528-byte sector directly to the SRAM. Writing to a sector is , SRAM (71H and 73H) The Read SRAM command (71H and 73H) provides access to the 528-byte SRAM


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PDF NX25F080C, NX25F160C NX25F320C 16M-BIT 32M-BIT NXSF029A-1201 NX25F080C NX25F160C 25f080 25F160 32 megabit serial flash transistor ba15 25F08 25F320 0000-037F 32M Nonvolatile SRAM NXSF029A-1201
2003 - ci 4093

Abstract: K9S1208
Text: column address of 512 to 527. A 528-byte data register is connected to memory cell arrays and is , Program : (512 + 16) Byte * Multi Page Program : 2K Bytes - Block Erase : (16K + 512) Byte ·528- Byte Page , page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and , K9S1208V0X : (512+16) Byte x 131,072 K9D1G08V0X : (512+16) Byte x 262,144 Page Register & S/A A8 , Page Register (=256 Bytes) (=256 Bytes) 8 bit 512B Byte 16 Byte I/O 0 ~ I/O 7 Page


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PDF K9D1G08V0M/A-SSB0 K9S1208V0M/A-SSB0 128MB ci 4093 K9S1208
CO2V

Abstract: No abstract text available
Text: D escription A program operation program s the 528-byte page in typically 250us and an erase , escription A program operation program s the 528-byte page In typically 250us and an erase operation can be , : (256+8) Byte - Block Erase : (4K+128) Byte · M ulti-B lo ck Erase - Status R egister Features · A utom atic Program and Erase - Page Program : (256+8) Byte - Block Erase : (4K+128)B yte - Status R egister C urrent D escription G eneral D escription A program operation program s the 264- byte page In typically 300us (500us


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PDF SAMSF002 KM29N040T KM29V040T A18/19 528-byte 250us 32000T/R 32000T/R CO2V
2002 - ATO Solution nand flash

Abstract: K9D1G08V0M-SSB0 K9S1208V0M-SSB0 K9D1G08V0M
Text: address of 512 to 527. A 528-byte data register is connected to memory cell arrays and is accommodating , Program : (512 + 16) Byte * Multi Page Program : 2K Bytes - Block Erase : (16K + 512) Byte ·528- Byte Page , . Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for , Decoders K9S1208V0M : (512+16) Byte x 131,072 K9D1G08V0M : (512+16) Byte x 262,144 Page Register & S/A , Page Register (=256 Bytes) (=256 Bytes) 8 bit 512B Byte 16 Byte I/O 0 ~ I/O 7 Page


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PDF K9D1G08V0M-SSB0 K9S1208V0M-SSB0 128MB ATO Solution nand flash K9D1G08V0M-SSB0 K9S1208V0M-SSB0 K9D1G08V0M
2002 - a1-a10

Abstract: No abstract text available
Text: ) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation - Random Access : 12µs(Max.) - , 200µs on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for , 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer , MEMORY 1,024M + 32M Bit NAND Flash ARRAY A0 - A 7 (512 + 16) Byte x 262,144 Page Register & S/A


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PDF K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Page28] 48-Pin 1220F 047MAX a1-a10
2003 - IC 4093

Abstract: K9K1G08U0M-YIB0 K9K1G08U0M K9K1G08U0M-YCB0 K9K1G08U0M-YCB0T
Text: by eight planes · Automatic Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation - Random Access : 12µ s(Max.) - Serial Page Access , mass storage market. A program operation can be performed in typical 200µs on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K- byte block. Data in the page can be read out , sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to


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PDF K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Page28] 48-Pin 1220F IC 4093 K9K1G08U0M-YIB0 K9K1G08U0M K9K1G08U0M-YCB0 K9K1G08U0M-YCB0T
1998 - 25F160

Abstract: TSOP 28 SPI memory Package flash 16 megabit serial flash 25F64 latch 74H 001H NX25F160C NXSF028A-1101 25F640
Text: on-board 528-byte SRAM Buffers - Byte-level addressing - Transfer and Compare sector to SRAM - , without having to clock an entire 528-byte sector out of the device. In most cases data is read through one of two 528-byte SRAM buffers by using the Transfer Sector to SRAM and Read SRAM commands. For , SRAM is fully byte-addressable. Thus, the entire 528-bytes , a single byte , or a sequence of bytes can , to SRAM command transfers the contents of a specified 528-byte sector directly to the SRAM. Writing


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PDF NX25F160C 16M-BIT NXSF028A-1101 NX25F160C-3V 28-pin, 25F160 TSOP 28 SPI memory Package flash 16 megabit serial flash 25F64 latch 74H 001H NX25F160C NXSF028A-1101 25F640
2003 - K9K1G08U0M-YCB0

Abstract: IC 4093 K9K1G08U0M K9K1G08U0M-YIB0
Text: Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation , performed in typical 200µs on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve , sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to , Decoders 1,024M + 32M Bit NAND Flash ARRAY (512 + 16) Byte x 262,144 Page Register & S/A A8


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PDF K9K1G08U0M Page28] 48-Pin 1220F 047MAX K9K1G08U0M-YCB0 IC 4093 K9K1G08U0M K9K1G08U0M-YIB0
2002 - 001H

Abstract: 32-PIN NXSF032A-0502
Text: without having to clock an entire 528-byte sector out of the device. Data can be read directly from the array using a Read Sector Command or through one of two 528-byte SRAM buffers by using the Transfer , 528-bytes , a single byte , or a sequence of bytes can be read from, or written to the SRAM. This , specified 528-byte sector directly to the SRAM. Writing to a sector is accomplished by first bringing CS , access to the 528-byte SRAM independent of any Flash memory array operations. The TR bit in the status


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PDF NX25F641C 64M-BIT NXSF032A-0502 NX25F641C. NX25F641C-3T 32-pin, 001H 32-PIN NXSF032A-0502
2001 - Not Available

Abstract: No abstract text available
Text: ) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation - Random Access : 12µs(Max.) - , to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer , typically 200µ s and an erase operation can be performed in typically 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and data , ARRAY A0 - A7 (512 + 16) Byte x 262,144 Page Register & S/A A8 Command Command Register


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PDF K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Page28] 48-Pin 1220F
2002 - Not Available

Abstract: No abstract text available
Text: ) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation - Random Access : 12µs(Max.) - , 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer , typical 200µs and an erase operation can be performed in typical 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and data , Bit NAND Flash ARRAY A0 - A 7 (512 + 16) Byte x 262,144 Page Register & S/A A8 Command


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PDF K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 Page28] 48-Pin 1220F 047MAX
1999 - digital VOICE RECORDER

Abstract: KM29U128 NAND Reliability note KM29U128IT KM29U128T TSOP 48 Package nand memory
Text: Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read , . A program operation programs the 528-byte page in typically 200ms and an erase operation can be performed in typically 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and data input/output as well as command inputs


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PDF KM29U128T, KM29U128IT 528-Byte KM29U128 KM29U128T/TI digital VOICE RECORDER NAND Reliability note KM29U128T TSOP 48 Package nand memory
K9F4G08U0M

Abstract: K9F4G08U 52-ULGA 52ULGA K9K8G08U1M K9F4G08U0M-ICB0 K9F4G08 81h-10h K9F4G08U0M-YCB
Text: controller can detect a bit error for each 528-byte plane by monitoring the Status bits (I/O1 & I/O 2) of the , ) or the each 528-byte plane unit. A page of 2,112- byte is composed of 4 planes of 528-byte and each 528-byte plane is made up of 512- byte in the main area and 16- byte in the spare area. Spare Area , 16 Byte 16 Byte Table 2. Definition of the 528-Byte Plane Main Area (Column 0~2,047) Plane , 'st 528-Byte Plane "A" 0 ~ 511 "E" 2,048 ~ 2,063 2'nd 528-Byte Plane "B" 512 ~ 1,023


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PDF K9K8G08U1M K9F4G08U0M K9F4G08U0M-Y K9F4G08U0M K9F4G08U 52-ULGA 52ULGA K9K8G08U1M K9F4G08U0M-ICB0 K9F4G08 81h-10h K9F4G08U0M-YCB
2001 - K9K1G08U0B

Abstract: K9K1G08B0B K9K1G08R0B 528-byte 3310H
Text: on the 528-byte page and an erase operation can be performed in typically 2ms on a 16K- byte block. Data in the data register can be read out at 50ns(1.8V device : 60ns) cycle time per byte . The I/O , column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating , 8bit · Automatic Program and Erase - Page Program - (512 + 16) Byte - Block Erase : - (16K + 512) Byte · Page Read Operation - Page Size - (512 + 16) Byte - Random Access : 15µs(Max.) - Serial


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PDF K9K1G08R0B K9K1G08B0B K9K1G08U0B K9K1G08U0B K9K1G08B0B K9K1G08R0B 528-byte 3310H
2001 - K9K1G08X0B

Abstract: K9K1G08U0B K9K1G08B0B K9K1G08R0B ci 4093
Text: typically 200µs on the 528-byte page and an erase operation can be performed in typically 2ms on a 16K- byte block. Data in the data register can be read out at 50ns(1.8V device : 60ns) cycle time per byte . The I , columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is , (512 + 16)bit x 8bit · Automatic Program and Erase - Page Program - (512 + 16) Byte - Block Erase : - (16K + 512) Byte · Page Read Operation - Page Size - (512 + 16) Byte - Random Access : 15µs(Max


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PDF K9K1G08R0B K9K1G08B0B K9K1G08U0B K9K1G08X0B K9K1G08U0B K9K1G08B0B K9K1G08R0B ci 4093
2000 - K9F1208U0M-PIB0

Abstract: K9F1208U0M
Text: Automatic Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page , be performed in typical 200µs on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins , 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between , extended operation of one-page Copy-Back program. => After successive reading of multiple 528 byte data set


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PDF K9F1208U0M 48-Pin 1220F 047MAX K9F1208U0M-PIB0 K9F1208U0M
Not Available

Abstract: No abstract text available
Text: Programmable Read Only Memory (NAND EEPROM) organized as 528 byte X 16 pages X 512 blocks. The device has a 528-byte , memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (8 , Register 528 X 8 Page size 528 byte Block size (8 k + 256) byte Mode : Read, Reset, Auto Page Program Auto , : 528Byte/Page Operation V Byte /Page Operation T he in form ation con tained herein Is


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PDF TC5832 TC5832FT 528-byte, 528-byte TC5832FT--
2001 - Not Available

Abstract: No abstract text available
Text: CopyBack operation, the system controller can detect a bit error for each 528-byte plane by monitoring the , with the whole page unit (2,112- byte ) or the each 528-byte plane unit. A page of 2,112- byte is composed of 4 planes of 528-byte and each 528-byte plane is made up of 512- byte in the main area and 16- byte , 528-Byte Plane Main Area (Column 0~2,047) Plane Area Name Spare Area (Column 2,048~2,111) Column Address Area Name Column Address 1’st 528-Byte Plane "A" 0 ~ 511 "E" 2,048


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PDF K9K8G08U1M K9F4G08U0M
2001 - Not Available

Abstract: No abstract text available
Text: €¢ Automatic Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte • 528-Byte , columns are located from column address of 512 to 527. A 528-byte data register is connected to memory , performed in typically 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and data input/output as well as command inputs. The , - A7 Y-Buffers Latches & Decoders 1,024M + 32M Bit NAND Flash ARRAY (512 + 16) Byte x


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PDF K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 K9K1G08U0M-YCB0 48-Pin 1220F
2000 - Not Available

Abstract: No abstract text available
Text: four planes · Automatic Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation - Random Access : 12µs(Max.) - Serial Page Access : 50ns(Min.) · , market. A program operation can be performed in typical 200µs on the 528-byte page and an erase operation , from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays , extended operation of one-page Copy-Back program. => After successive reading of multiple 528 byte data set


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PDF K9F1208U0M 48-Pin 1220F 047MAX
2001 - K9F4G08U0M

Abstract: two-plane program nand
Text: for each 528-byte plane by monitoring the Status bits (I/O1 & I/O 2) of the Status Register. There are , , the page program should be performed with the whole page unit (2,112- byte ) or the each 528-byte plane unit. A page of 2,112- byte is composed of 4 planes of 528-byte and each 528-byte plane is made up of , ) (3'rd plane) (4'th plane) 16 Byte 16 Byte 16 Byte 16 Byte Table 2. Definition of the 528-Byte Plane Plane 1'st 528-Byte Plane 2'nd 528-Byte Plane 3'rd 528-Byte Plane 4'th 528-Byte Plane Main Area


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PDF K9K8G08U1M K9F4G08U0M K9F4G08U0M two-plane program nand
2002 - K9F1208U0M-YIB0

Abstract: K9F1208U0M K9F1208U0M-YCB0 flash disk controller
Text: x8bit multipled by four planes · Automatic Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte · 528-Byte Page Read Operation - Random Access : 12µs(Max.) - Serial Page , state mass storage market. A program operation can be performed in typical 200µs on the 528-byte page , column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating , byte data set at the source planes, the above data are moved to internal page registers and same


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PDF K9F1208U0M-YCB0, K9F1208U0M-YIB0 48-Pin 1220F 047MAX K9F1208U0M-YIB0 K9F1208U0M K9F1208U0M-YCB0 flash disk controller
2001 - a26 transistor

Abstract: No abstract text available
Text: from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays , eight planes ·Automatic Program and Erase - Page Program : (512 + 16) Byte - Block Erase : (16K + 512) Byte ·528- Byte Page Read Operation - Random Access : 12µ s(Max.) - Serial Page Access : 50ns(Min , can be performed in typically 2ms on a 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and data input/output as well as command


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PDF K9D1G08V0M-SSB0 a26 transistor
ssfdc

Abstract: 64MB 3.3V SmartMedia card TS64MVSSFDC 64mb nand flash
Text: Program and Erase Page Program : (512 + 16) Byte Block Erase : (16K + 512) Byte !" 528-Byte Page Read , solid state mass storage market. A program operation programs the 528-byte page in typically 200us and an erase operation can be performed in typically 2ms on an 16K- byte block. Data in the page can be read out at 50ns cycle time per byte . The I/O pins serve as the ports for address and data input , ) Byte x 131072 Page Register & S/A A8 Y-Gating Command Command Register /CE /RE /WE


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PDF TS64MVSSFDC 2048K 528-Byte 200us ssfdc 64MB 3.3V SmartMedia card TS64MVSSFDC 64mb nand flash
Supplyframe Tracking Pixel