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LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LT1018MJ8/883 Linear Technology LT1018 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LM108AJ8 Linear Technology LM108A - Operational Amplifiers; Package: CERDIP; Pins: 8; Temperature: Military
LT1175CDWF#MILDWF Linear Technology LT1175 - 500mA Negative Low Dropout Micropower Regulator; Pins: 5
LTC1041MJ8/883 Linear Technology LTC1041 - BANG-BANG Controller; Package: CERDIP; Pins: 8; Temperature: Military
LTC2904CDDB#TRMPBF Linear Technology LTC2904 - Precision Dual Supply Monitor with Pin-Selectable Thresholds; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C

50-pin lvds Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2007 - SIO1007-JV

Abstract: SIO1007 50-pin lvds SMSC SIO1007 Super I/O DB800 Clock Buffer ddr2 ram slot pin detail of motherboard intel 965 motherboard circuit diagram ICH8M 82801hem 82801HBM
Text: . 3.4.1.3.2 LVDS Flat Panel Interface The development board provides one 50-pin LVDS video interface , abbreviation, a period, and the pin number (e.g., P1.0). 316704-001 / Development Kit User's Manual 7 , defined as: The time difference between a signal at the input pin of a receiving agent crossing the , specifications; i.e., ringback, etc.) and the output pin of the driving agent crossing the switching voltage , the package substrate. A pad is only observable in simulations. Pin The contact point of a


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PDF GME965 945GM SIO1007-JV SIO1007 50-pin lvds SMSC SIO1007 Super I/O DB800 Clock Buffer ddr2 ram slot pin detail of motherboard intel 965 motherboard circuit diagram ICH8M 82801hem 82801HBM
2006 - 4 pin crystal oscillator

Abstract: ICS556-03 LVDS Crystal 3 pin crystal oscillator
Text: ICS556-03 QUAD LVDS OSCILLATOR/BUFFER LVDS CRYSTAL BUFFER Pin Assignment EN1 1 16 EN4 , OSCILLATOR/BUFFER Pin Description 2 ICS556-03 REV D 051310 ICS556-03 QUAD LVDS OSCILLATOR/BUFFER LVDS CRYSTAL BUFFER Pin Number Pin Name Pin Type Pin Description 14 D , /BUFFER LVDS CRYSTAL BUFFER Package Outline and Package Dimensions (16- pin TSSOP, 4.40 mm Body, 0.65 , DATASHEET ICS556-03 QUAD LVDS OSCILLATOR/BUFFER Description Features The ICS556-03 is


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PDF ICS556-03 ICS556-03 16-pin 4 pin crystal oscillator LVDS Crystal 3 pin crystal oscillator
2001 - EP20K1000E

Abstract: EP20K400E EP20K600E 10226-1A10VE ldvs connector altlvds_tx vhdl code for lvds driver vhdl code for lvds receiver
Text: 1100 7 0011100 8 00111100 Driving the dual-function DESKEW pin high places the LVDS , diagram of the APEX 20KE LVDS PLLs, including LVDS-specific pin names. 23 AN 120: Using LVDS in , output pin can be placed within two pads of LVDS pins unless separated by a power or ground pin . Use the , software will give an error message for illegal output or bidirectional pin placement next to the LVDS pin , space. LVDS Paired Pin Labeling Information on the dual-purpose paired LVDS pins are displayed in


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2002 - TXDN12

Abstract: VSC9182 GR253-CORE STM-64 VSC9186 0011bb
Text: Multicast and Broadcast · Serial LVDS 622Mb/s High-Speed Interface with PECL/CML Compatibility and , differential LVDS STS-12/STM-4 inputs · Receives 64 serial 622.08Mb/s STS-12/STM-4 line channels (these 64 , 622.08Mb/s differential LVDS STS-12/STM-4 outputs · Optionally inserts byte-interleaved parity into B1 , Interrupt output pin to signal status changes of internal alarms Test Interface · IEEE P1149.1 test access , until the CONFIG pin is asserted and the next frame boundary is received (signaled by the SYNC input).


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PDF VSC9182 64x64 STS-12/STM-4 768x768 622Mb/s 50MHz 11-Bit P1149 TXDN12 VSC9182 GR253-CORE STM-64 VSC9186 0011bb
2006 - ICS556-03

Abstract: ICS556-03I
Text: output. IDTTM / ICSTM QUAD LVDS OSCILLATOR/BUFFER Pin Description 2 ICS556-03 REV C 092309 ICS556-03 QUAD LVDS OSCILLATOR/BUFFER LVDS CRYSTAL BUFFER Pin Number Pin Name Pin Type , DATASHEET ICS556-03 QUAD LVDS OSCILLATOR/BUFFER Description Features The ICS556-03 is a clock oscillator with quad LVDS outputs. Using a standard 25 MHz crystal, no additional external components are required to generate quad LVDS outputs at 25 MHz. · · · · · · This product is


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PDF ICS556-03 ICS556-03 16-pin U-09-0/BUFFER ICS556-03I
2006 - Not Available

Abstract: No abstract text available
Text: LVDS CRYSTAL BUFFER Pin Number 14 15 Pin Name D EN3 Pin Type Output Input Differential , LVDS CRYSTAL BUFFER Package Outline and Package Dimensions (16- pin TSSOP, 4.40 mm Body, 0.65 mm , DATASHEET QUAD LVDS OSCILLATOR/BUFFER Description The ICS556-03 is a clock oscillator with quad LVDS outputs. Using a standard 25 MHz crystal, no additional external components are required to generate quad LVDS outputs at 25 MHz. This product is intended for clock generation. It has low output


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PDF ICS556-03 16-pin 25MHz 199707558G
2012 - 4x10G

Abstract: EXS00A-CG EXS00A EXS00A-CG02813
Text: output swing LVDS output, AC coupled w/ 100 diff load HCSL output, 50 load to GND on each output pin , Switching SPI, I2CTM, and Pin Programmable Professional user GUI for Quick Design Turnaround 7 x 7 mm 48 , , LVPECL, LVDS , or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data , I2C or SPI programming interface and in the absence of serial interface, pin mode is also available , outputs using fractional dividers. The CDCM6208 is packaged in a small 48- pin 7mm x 7mm QFN package


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PDF CDCM6208 SCAS931B 4x10G EXS00A-CG EXS00A EXS00A-CG02813
2010 - MAX14979E

Abstract: laptop lcd LVDS 26 pin no3a
Text: ) Pin Description PIN NAME 1 COM0- Common LVDS Differential Terminal for Switch 0 , Switch PIN NAME 22 NC2+ Normally Closed LVDS Differential Terminal for Switch 2 23 NO1 , 19-5252; Rev 0; 4/10 High-Bandwidth, ±15kV ESD Protection LVDS Switch The MAX14979E is , differential signal ( LVDS ) and low-voltage positive emitter-coupled logic (LVPECL) switching applications , 16 Multiplexer/Demultiplexer S Space-Saving, Lead-Free, 36- Pin , 6mm x 6mm TQFN Package Eye


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PDF MAX14979E Q15kV 650MHz MAX14 MAX14979E laptop lcd LVDS 26 pin no3a
2006 - IDT5V5216

Abstract: 5V5216 pin assignment lvds TSSOP14 Figure10
Text: IDT5V5216 1 Single Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/ LVDS Transceiver PIN ASSIGNMENT NC , 2 Single Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/ LVDS Transceiver PIN DESCRIPTION , / LVDS Drivers Enable This pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/ LVDS drivers , /LVPECL/ LVDS Interface Input/Output This pin globally determines the type of input/output of the LVTTL , output signal can be LVPECL or LVDS , as selected by the DIFF_SEL pin . OUT_A: LVTTL Output This pin


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PDF IDT5V5216 PGG14) 5V5216 IDT5V5216 5V5216 pin assignment lvds TSSOP14 Figure10
2009 - vhdl code for lvds driver

Abstract: LVDS 51 connector EP20K1000E EP20K400E EP20K600E verilog code for lvds driver vhdl code for lvds receiver
Text: Driving the dual-function DESKEW pin high places the LVDS inputs in calibration mode. The calibration , pin names. 23 AN 120: Using LVDS in APEX 20KE Devices Figure 13. LVDS PLL Block Diagram 4 , . EP20K300E devices support using LVDS on dedicated clock signals and LVDS data in bypass (1) mode in the 652- pin ball-grid array (BGA) and 672- pin FineLine BGA packages. EP20K200E and smaller devices support using LVDS , reducing board space. LVDS Paired Pin Labeling Information on the dual-purpose paired LVDS pins are


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2003 - verilog code for lvds driver

Abstract: vhdl code for lvds driver LVDS 51 connector LVDS connector 30 pins EP20K1000E EP20K400E EP20K600E altlvds_tx vhdl code for lvds receiver
Text: 1100 7 0011100 8 00111100 Driving the dual-function DESKEW pin high places the LVDS , , including LVDS-specific pin names. 23 AN 120: Using LVDS in APEX 20KE Devices Figure 13. LVDS PLL , and LVDS data in bypass (×1) mode in the 652- pin ball-grid array (BGA) and 672- pin FineLine BGA , space. LVDS Paired Pin Labeling Information on the dual-purpose paired LVDS pins are displayed in , , LVDSRXINCLK1p. LVDS pins have a specific naming convention: all LVDS pin names begin with LVDS . The next two


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2009 - Not Available

Abstract: No abstract text available
Text: Bias Current (Each Pin ) LVDS CLOCK OUTPUTS Output Frequency Differential Output Voltage Offset , CTRL_A CTRL_A selects either CMOS (high) or LVDS (low) logic for Output 1 and Output 0. This pin has an , 1.8 V, 6 LVDS /12 CMOS Outputs Low Power Clock Fanout Buffer ADCLK846 FUNCTIONAL BLOCK DIAGRAM FEATURES ADCLK846 LVDS /CMOS OUT0 (OUT0A) OUT0 (OUT0B) VREF OUT1 (OUT1A) CLK OUT1 (OUT1B) CLK CTRL_A LVDS /CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) APPLICATIONS Low jitter clock


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PDF LVDS/12 ADCLK846 MO-220-VGGD-2 80808-A 24-Lead CP-24-2 ADCLK846BCPZ ADCLK846BCPZ-REEL7 ADCLK846/PCBZ
2006 - ICS859S0424I

Abstract: ICS859S0424AGI
Text: ] LVDS 2.5V VCC 1 LVPECL LVDS 3.3V Float 0 LVDS Block Diagram Pin , PRELIMINARY ICS859S0424I 4:4 DIFFERENTIAL-TO-LVPECL/ LVDS CLOCK MULTIPLEXER Description Features The ICS859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up , /PCLKx input pairs can accept LVPECL, LVDS , CML or SSTL levels. The fully differential architecture and , internal pulldown resistors. The CLK_SEL1 pin is the most significant bit and the binary number applied


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PDF ICS859S0424I ICS859S0424I t408-284-2775 199707558G ICS859S0424AGI
2003 - tolerance j12

Abstract: LVDS 30 pin connector cable LVDS connector 30 pin MDR 26 pin LVDS connector 40 pins NAME connector 30 pin IDC MDR 68 pin configuration MDR 14 pin lvds connectors pin assignments CLINK3V485
Text: DS90CR485 transmitter DS_OPT pin (J6) automatically generates an LVDS switching pattern at the LVDS outputs , The TSEN pin reports the presence of a remote termination resistor on the LVDS clock line. The user , . 1.01 MDR Connector Transmitter LVDS Output Pin # Receiver LVDS Input NAME Pin # NAME , 17 Transmitter PRBS Generator Mode . 19 LVDS Cable Sense (TSEN) Status Flag . 19 Pin & Signal Assignments


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PDF DS90CR485/486 DS90CR485/486 48-bit, CLINK3V48BT-133 CLINK3V485/486 tolerance j12 LVDS 30 pin connector cable LVDS connector 30 pin MDR 26 pin LVDS connector 40 pins NAME connector 30 pin IDC MDR 68 pin configuration MDR 14 pin lvds connectors pin assignments CLINK3V485
1998 - k1306 datasheet

Abstract: M130 DIODE 1334 smd ISO 9435 JD smd diodes vcsel laser diode DIODE 709 1334 V23815-K1306-M130 V23814-K1306-M130 50-pin lvds
Text: . Typ. Max. Units Data Pin Diode Array Amplifier Gain Amplifier LVDS Output Stage , spacing (250 µm) and alignment pin spacing (4600 µm) 52 DO10N LVDS Out Data Output #10 , FEATURES · Power supply 3.3 V · Low voltage differential signal electrical interface ( LVDS ) · 12 , Receiver: 840 nm PIN diode array · Fiber ribbon: 62.5 µm graded index multimode fiber · MT based optical , (VIN)(1) . ­0.5 V to VCC+0.5 V LVDS Input Differential Voltage (|VID|)(2


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PDF V23814-K1306-M130 V23815-K1306-M130 D-13623, de/semiconductor/products/37/376 k1306 datasheet M130 DIODE 1334 smd ISO 9435 JD smd diodes vcsel laser diode DIODE 709 1334 V23815-K1306-M130 V23814-K1306-M130 50-pin lvds
2002 - VSC9182

Abstract: No abstract text available
Text: Switch with Nonblocking 768x768 STS-1 Switch Matrix · Supports Both Multicast and Broadcast · Serial LVDS , switch configuration (address map) Input Backplane Interface · Serial 622.08Mb/s differential LVDS , Serial 622.08Mb/s differential LVDS STS-12/STM-4 outputs Optionally inserts byte-interleaved parity into , output pin to signal status changes of internal alarms Test Interface · IEEE P1149.1 test access port , memory. The programming does not take effect until the CONFIG pin is asserted and the next frame boundary


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PDF VSC9182 64x64 STS-12/STM-4 768x768 622Mb/s 50MHz 11-Bit P1149
2006 - 5V5218

Abstract: IDT5V5218 TSSOP24 Figure10
Text: IDT5V5218 1 Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/ LVDS Transceiver PIN ASSIGNMENT , LVTTL/LVPECL/ LVDS Transceiver PIN DESCRIPTION Table-1 Pin Description Name Pin No. I/O , pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/ LVDS drivers for channel 1: high for , RE2_EN: Type-1/Type-2 M-LVDS Receiver 2 and LVTTL/LVPECL/ LVDS Drivers 2 Enable This pin controls the , /Output 1 and 2 This pin globally determines the type of input/output 1 and 2 of the LVTTL/LVPECL/ LVDS


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PDF IDT5V5218 PGG24) 5V5218 5V5218 IDT5V5218 TSSOP24 Figure10
2007 - J504 lcd connector

Abstract: JP504
Text: : J104 Aux / LVDS Interface Pin Description – MityARM/MityDSP without FPGA Pin Signal Type Standard , Aux / LVDS Interface Pin Description – MityARM/MityDSP with FPGA Installed Pin Signal Type , Interface  SD/MMC Card Socket  Audio Output Expansion:  3 50- pin IO Expansion Slots ï , ) controller for external display connection with DDC support. Interface to QVGA\WQVGA display via 5 pair LVDS , SATA Header Battery (RTC) USB0 SATA 10- pin Header TRS232E RS232 PHY RJ-45 &


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PDF MityARM-1810 1810F MityDSP-L138 L138F RS485 MityARM-1808 1808F MityARM1808/1810 MityDSPL138 RS232 J504 lcd connector JP504
2012 - Not Available

Abstract: No abstract text available
Text: SPI, I2C™, and Pin Programmable Professional user GUI for Quick Design Turnaround 7 x 7 mm 48 , inputs that can feature a low frequency crystal or CML, LVPECL, LVDS , or LVCMOS signals for a variety of , serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed , packaged in a small 48- pin 7mm x 7mm QFN package. Additional list of FEATURES Supply Voltage: The , LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over PVT


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PDF CDCM6208 SCAS931A
2012 - Not Available

Abstract: No abstract text available
Text: . Configured as LVPECL or LVDS with the QC_CTRL pin . Power Supply for C-Bank Differential Output. Connect to , . Configured as LVPECL or LVDS with the QA_CTRL2 pin . A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin . A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin . A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin . A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin . Power Supply for B-Bank Differential Outputs


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PDF MAX3638
AN1003

Abstract: lvds 32 pin
Text: Translator 8 PIN SOIC / MSOP 3.0V to 5.5V LVDS to PECL / LVPECL Translator 8 PIN SOIC / MSOP , AN1004 Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL HIGH-PERFORMANCE PRODUCTS About LVDS Interfacing LVDS with PECL and LVPECL As the bandwidth increases in Telecom / Datacom and even in consumer / commercial applications , the high speed, low power, noise, and cost of LVDS , . Signal level translation between PECL / LVPECL to LVDS can be achieved using resistor divider network


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PDF AN1004 AN1003 lvds 32 pin
2014 - Not Available

Abstract: No abstract text available
Text: 637 OUTPUT TYPE P = LVPECL - Pin 1 Enable [std] L = LVDS - Pin 1 Enable [std] E = LVPECL - Pin 2 Enable [opt] V = LVDS - Pin 2 Enable [opt] PACKAGING T - 1k pcs./reel SUPPLY VOLTAGE 2 = 2.5 Vdc , , load, temperature and 1st year aging. LVPECL/ LVDS OUTPUT WAVEFORM ENABLE TRUTH TABLE PIN 1 or , Model 637 Low Jitter LVPECL or LVDS Clock Oscillator FEATURES • • • • • • â , RMS Maximum LVPECL or LVDS Output Fundamental and 3rd Overtone Crystal Designs Frequency Range


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PDF EIA-418 J-STD-020;
2012 - ICS844021BGI-01LF

Abstract: No abstract text available
Text: ICS844021I-01 is packaged in a small 8- pin TSSOP, making it ideal for use in systems with limited board space. FEATURES · One Differential LVDS output · Crystal oscillator interface, 18pF parallel resonant crystal , BLOCK DIAGRAM OE Pullup PIN ASSIGNMENT VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ OE , / ICSTM LVDS CLOCK GENERATOR 1 ICS844021BGI-01 REV. A NOVEMBER 6, 2012 ICS844021I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 1 2 3, 4 5 6, 7 8 Name VDDA


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PDF ICS844021I-01 ICS844021I-01 34MHz. 25MHz 875MHz 20MHz 34MHz) ICS844021BGI-01LF
2006 - 173-MIL

Abstract: ICS843404 ICS843404AG ICS843404AGT
Text: can be bypassed using the VCO_SEL pin . · Three banks of outputs: one bank of two LVDS outputs and , Bypass mode. LVCMOS/LVTTL interface levels. Output supply pin for LVDS outputs. No connect , Power Output supply pin for LVPECL outputs. LVDS_FSEL1, Frequency select pins for LVDS outputs. See , DATA SHEET Integrated ICS843404 LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK ICS843404 Circuit LVCMOS/CRYSTAL-TO-3.3V LVPECL AND GENERATOR Systems, Inc. LVDS CLOCK GENERATOR GENERAL DESCRIPTION


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PDF ICS843404 ICS843404 75MHz, 375MHz 25MHz, 199707558G 173-MIL ICS843404AG ICS843404AGT
2001 - lvds connectors pin assignments

Abstract: cna 450 spice simulation
Text: . When more than one LVDS channel is connected to the same I/O bank, the VREF pin is supplied by the , /O standard assignments can be assigned to the procedure outlined in the LVDS Pin Assignment , technique is connected to a TFF. Place LVDS output pin pairs so that the skew between the positive and , Request CLK Read Rec 13 AN 138: LVDS Signaling Using APEX I/O Pins LVDS Pin Assignment , ® May 2001, ver. 1.0 Introduction LVDS Signaling Using APEX Device I/O Pins Application


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PDF TIA/EIA-644 lvds connectors pin assignments cna 450 spice simulation
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