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LT1034-1.2#TR Linear Technology IC SPECIALTY ANALOG CIRCUIT, Analog IC:Other
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5 to 32 decoder circuit Datasheets Context Search

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1997 - POCSAG

Abstract: S-29131A S-7040D S-7040DQP S-7040XQP 92F-11
Text: . PAGING DECODER IC (POCSAG) S-7040D Circuit Design 1. Interface to ID-ROM 1.1 ID-ROM assignment , SIG-IN BS2 BS1 8 7 6 5 4 3 2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 32 31 30 , pin has noise reduction circuit . Duty cycle of 25 to 75% is required. 14 SIG-IN In 15 BS2 Out Output pin for quick charge signal to RF circuit reference voltage. BS1 Out , oscillation and resets the internal circuit . IDROM data is fetched after recovery. Connect to VDD when the


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PDF S-7040DQP) S-18XX) POCSAG S-29131A S-7040D S-7040DQP S-7040XQP 92F-11
1996 - SAA7197

Abstract: clock generator using ic 555 TDA8709 SAA7196H SAA7196 SAA7194 SAA7191B SAA7186 QFP120 YUV10
Text: circuit (DESCPro) Fig.1 Block diagram of decoder part (continued in Fig.2). 5 CONTROL I2C-BUS , Digital video decoder , Scaler and Clock generator circuit (DESCPro) · Mode 3: YUV15 to YUV0 and HREF/VS , Semiconductors Product specification Digital video decoder , Scaler and Clock generator circuit (DESCPro , Digital video decoder , Scaler and Clock generator circuit (DESCPro) 1 SAA7196 · I2C-bus control , 2 The CMOS circuit SAA7196, digital video decoder , scaler and clock generator (DESCPro), is a


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PDF SAA7196 SAA7197 clock generator using ic 555 TDA8709 SAA7196H SAA7196 SAA7194 SAA7191B SAA7186 QFP120 YUV10
1999 - "Decoder IC"

Abstract: POCSAG S-29131A S-7040D S-7040DQP S-7040XQP
Text: DECODER IC (POCSAG) S-7040D n Circuit Design 1. Interface to ID-ROM 1.1 ID-ROM assignment The S , elements: Crystal oscillator ( 32 KHz/76 KHz), CG, RF · Direct interface to IDROM (S-29131A / S-2913) · 3 , correction up to 2 bits Battery saving Battery low alert Extended function 1 PAGING DECODER IC , Hard-clear circuit RST XRS CLK-OUT VDD VSS Figure 2 n Pin Configuration 32 -pin QFP Top , synchronous to falling edge of the clock. H 5 RX-DATA Out Output pin for received data. L


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PDF S-7040D S-7040D "Decoder IC" POCSAG S-29131A S-7040DQP S-7040XQP
SAA7194

Abstract: No abstract text available
Text: specification Digital video decoder , scaler, and clock generator circuit (DESCPro) SAA7196 5 . BLOCK , , digital video decoder , scaler and clock generator (DESCPro), is a highly integrated circuit for DeskTop , ) of the input interface are used in Y/C mode (Fig. 1(a) on page 5 ) to decode digitized luminace and , , and only one ADC is neccessary (Fig.3 on page 12). The 32 -bit VRAM output port is interface to the , Expansion port is configurable to send data from the decoder unit or to accept external data for input


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PDF SAA7196 VR017 VR019 VRO20 VR016 VR018 VR022 VR023 VR025 SAA7194
hlx crystal

Abstract: HP611 VR029 SAA7197 SAA7196H SAA7196 SAA7194 SAA7191B SAA7186 QFP120
Text: specification Digital video decoder , Scaler and Clock SAA7196 generator circuit (DESCPro) 5 BLOCK DIAGRAM , ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Decoder part 7.1.1 , Digital video decoder , Scaler and Clock generator circuit (DESCPro) SAA7196 1 FEATURES Digital 8 , GENERAL DESCRIPTION The CMOS circuit SAA7196, digital video decoder , scaler and clock generator (DESCPro , ) • 32 -bit VRAM output port; interface to the video memory. It outputs the down-scaled video data


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PDF SAA7196 hlx crystal HP611 VR029 SAA7197 SAA7196H SAA7196 SAA7194 SAA7191B SAA7186 QFP120
POCSAG

Abstract: "Decoder IC" S-29131A S-7040D S-7040XQP DS-VTC-200
Text: internal circuit and the POCSAG signal. Acceptable duty ratio of preamble ranges from 25% to 75%. 32 , .16 Circuit Design .21 PAGING DECODER IC (POCSAG) S , per an address External elements: Crystal oscillator ( 32 KHz/76 KHz), CG, Rf Direct interface to , output. Serial output of received data is enabled in synchronous to falling edge of the clock. H 5 , enabled by register). Thispinhas noise reduction circuit . Dutycydeof 25 to 75% is required. 15 BS2 Out


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PDF S-4S20B S-29131A) S-7040DQP) S-18XX) POCSAG "Decoder IC" S-29131A S-7040D S-7040XQP DS-VTC-200
"Preamble signal"

Abstract: No abstract text available
Text: . 16 Circuit Design. 21 PAGING DECODER , This pin has noise reduction circuit . Duty cycle of 25 to 75% is required. Output pin for quick charge signal to RF circuit reference voltage. Output pin for control signal of RF circuit power supply , 2.7 KHz / 3.2 KHz. Input pin for oscillation control. "H" to this pin enables oscillation. "L" disables oscillation and resets the internal circuit . IDROM data is fetched after recovery. Connect to Vdo when the pin


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PDF S-7040D_ "Preamble signal"
5 to 32 decoder circuit

Abstract: VR015 YUV10 SAA7186 SAA7194 mPC 514 SAA7197 VR029 VR012 YR025
Text: Products Objective specification Digital video decoder , scaler and clock generator circuit (DESCPro , Digital video decoder , scaler and clock generator circuit (DESCPro) SAA7196 GENERAL DESCRIPTION The CMOS circuit SAA7196, digital video decoder and scaler (DESC), is a highly integrated circuit for , ADC is necessary (Fig.3). The 32 -bit VRAM output port is interface to the video memory; it outputs the , identical to that of SAA7194. It is divided into two sections: - subaddress OOh to 1F for the decoder part


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PDF bbS3T24 SAA7196 CYB56 VR010 VR011 YR012 VR013 YR014 VR015 5 to 32 decoder circuit YUV10 SAA7186 SAA7194 mPC 514 SAA7197 VR029 VR012 YR025
saa5000

Abstract: TBA2800
Text: , 32 kBytes ROM, and 1024 Bytes RAM. An IM/I2C master interface, a 5 -input ADC, ports and 6 PWM , circuit . Features: - CPU with 6 MHz clock (3 MIPS) Closed-Caption Decoder 3-line caption mode , Bytes RAM up to 29 port lines six PWM converters, 6-bit 5 -input ADC (8-bit resolution/6-bit accuracy , to 512 kBytes external ROM up to 26 port lines six PWM converters, 6-bit 5 -input ADC (8 , Caption Slicer 1>' 61 . • ' . ' - P W M O to H S y n C2 ■PW M 5 T' 61/ 1,-


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PDF CCU3000 CCU3001, 3000-I 3001-I PLCC68) CCU3001 65C02 CCU3000: CCU3001: saa5000 TBA2800
scrambler satellite v.35

Abstract: BUS13r IESS-308 sCRAMBLER iess-309 standard BPSK demodulator bpsk modulation and demodulation IESS309 intelsat scrambler scrambler v.35 diagram
Text: Quality Monitor Error Threshold Selection Ratio of channel errors to window size 1/8 5 / 32 3/16 7/ 32 1/4 9 , decoder with up to 3 bit soft decision inputs and an 80 stage trellis · Two versions for operation at the , Excellent performance for code rates up to 7/8 · Encoder and decoder valid data synchronization inputs and , forward error correction circuit that can provide more than 5 dB of coding gain for information rates up , rate 3/4. The decoder offers optional differential decoder and CCITT V.35 descrambling to be applied


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PDF PM7018-256 PM7018-2500 861029R5 scrambler satellite v.35 BUS13r IESS-308 sCRAMBLER iess-309 standard BPSK demodulator bpsk modulation and demodulation IESS309 intelsat scrambler scrambler v.35 diagram
POCSAG

Abstract: circuit diagram of scrolling LED message display "Decoder IC" s7038af 7038A S-7038AF S-29131A TSI S 14001 29131 S14001
Text: Circuit Design configuration of ID-ROM). Table 5 Setup of number of retries 1. Interface to ID-ROM" for , DECODER IC (POCSAG) S-7038AF ■Circuit Design 1. Interface to ID-ROM 1.1 ID-ROM assignment Using S , circuit example: Tone-only pager 3.2 Display pager A CPU and a display unit are added to a tone-only , DECODER IC (POCSAG) S-7038AF Features Operating voltage : 1.7 to 5.5 V (3.0 V typ.) Current consumption , External elements: Crystal oscillators ( 32 kHz/76 kHz), Cq, Rf Direct interface to IDROM (S


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PDF S-14001 SEGO-31 POCSAG circuit diagram of scrolling LED message display "Decoder IC" s7038af 7038A S-7038AF S-29131A TSI S 14001 29131 S14001
Not Available

Abstract: No abstract text available
Text: and decoder output filters are incorporated on-chip. Sam pling clock rates can be programm ed to 16, 32 or 64K bits/second from an internal clock generator or externally injected in the 8 to 64K bits , Force Idle: A logical “0” at this pin gates a 0101. pattern internally to the decoder so that the decoder output goes to VD /2. W hen this pin is at a logical “ 1” , the decoder operates as normal. D , Internal, 32kb/s = f/ 32 1 1 Internal, 16kb/s = f/64 External Clocks Clock rates refer to f =


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PDF MX629 Mil-Std-188-113 MX629J 22-pin MX629 td-188-113, 500Hz 98m/sec. 100C3;
1999 - 7040D

Abstract: "Decoder IC" diodes SY 200 POCSAG POCSAG out of range S-7040XQP S-7040DQP S-7040D S-29131A SY 200
Text: is enabled by register). This pin has noise reduction circuit . Duty cycle of 25 to 75% is required , internal circuit . IDROM data is fetched after recovery. Connect to VDD when the pin is not used. No , column means that the pin is pulled up to VDD. Seiko Instruments Inc. 3 PAGING DECODER IC , , XRST to VDD, other pins are open and the oscillation circuit operates. 4. Current flowing into the IC is defined to be positive. 5 . f (VDD=3.0 V) - f0 f/ IC= ×106 (ppm) f0: Average frequency when


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1996 - MCT 2E C4

Abstract: Block diagram on monochrome tv receiver circuit Block diagram on monochrome tv transmitter VMUX QFP120 yb4 42 Programmable PLL Clock Generator VC80 digital cvbs encoder 1024 768 BUS CONTROLLED VERTICAL DEFLECTION SYSTEM
Text: circuit (DESCPro) Fig.1 Block diagram of decoder part (continued in Fig.2). 5 CONTROL I2C-BUS , Digital video decoder , Scaler and Clock generator circuit (DESCPro) · Mode 3: YUV15 to YUV0 and HREF/VS , Semiconductors Product specification Digital video decoder , Scaler and Clock generator circuit (DESCPro , Digital video decoder , Scaler and Clock generator circuit (DESCPro) 1 SAA7196 · I2C-bus control , 2 The CMOS circuit SAA7196, digital video decoder , scaler and clock generator (DESCPro), is a


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PDF SAA7196 SCA52 657021/1200/01/pp76 MCT 2E C4 Block diagram on monochrome tv receiver circuit Block diagram on monochrome tv transmitter VMUX QFP120 yb4 42 Programmable PLL Clock Generator VC80 digital cvbs encoder 1024 768 BUS CONTROLLED VERTICAL DEFLECTION SYSTEM
Not Available

Abstract: No abstract text available
Text: rates can be programmed to 16, 32 or 64K bits/second from an internal clock generator The MX609 is a , circuit ) vss Encoder Force Idle: When this pin is at a logical “0” the encoder is forced to an , “O’’ at this pin gates a 0101. pattern internally to the decoder so that the Decoder Output goes to VD /2. When this pin is a logical “1” the decoder operates as D normal. Internal 1M12 , available at the ports for external circuit synchronization. Independent or com­ mon data rate inputs to


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PDF MX609J MX609P MX609LH MX609DW z-2800Hz) 500Hz-3000Hz) 820Hz, -20dB 0002b07
LHi 874

Abstract: LHi 888 sp1191 HP611 APER XD7 SAA7194 VR029 VR06 VR030 sot349
Text: the decoder part (Tables 9 and 10 on page 32 and page 33) - subaddress 20h to 3F for the scaler part , Product specification Digital video decoder and scaler circuit (DESC) SAA7194 Table 5 VRAM port output , INTEGRATED CIRCUITS DATA SHEET SAA7194 Digital video decoder and scaler circuit (DESC , Product specification Digital video decoder and scaler circuit (DESC)SAA7194 Ï CONTENTS I VJBB 1 , SAA7194, digital video decoder and scaler (DESC), is a highly integrated circuit for DeskTop Video


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PDF SAA7194 007clcà LHi 874 LHi 888 sp1191 HP611 APER XD7 SAA7194 VR029 VR06 VR030 sot349
SAA7194

Abstract: No abstract text available
Text: decoder part (Tables 9 and 10 on page 32 and page 33) - subaddress 20h to 3F for the scaler part (Tables , Product specification Digital video decoder and scaler circuit (DESC)SAA7194 n CO NTENTS 1. 2 , Digital video decoder and scaler circuit (DESC) SAA7194 1. FEATURES 2. GENERAL DESCRIPTION â , circuit SAA7194, digital video decoder and scaler (DESC), is a highly integrated circuit for DeskTop , are used in Y/C mode (Fig. 1(a) on page 5 ) to decode digitized luminace and chrominance signals


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PDF SAA7194 711002b 00711b2 SAA7194
mmi "tiw PROM" programming

Abstract: MMI PLE5P8 63S481 22AA 63S081 PLE9P4 PLE10P4 PLE11P8 PLE9R8 63s281
Text: ) NUMBER TERMS REGISTERS MAX* PLE5P8 5 8 32 25 PLE5P8A 5 8 32 15 PLE8P4 8 4 256 30 PLE8P8 8 8 256 , AND array driving a fixed OR array). PRODUCT TERM AND INPUT LINES PLE PAL Product Terms 32 to 4096 1 to 16 Input Lines 5 to 12 6 to 64 The PLE family features common electrical parameters and , ns «h Hold time from input to clock 0 - 5 0 - 5 ns «h (ES) Hold time from ES to clock 5 -3 5 , ) are tested w'th CL = 5 PF- is open for "1" to high impedance test, measured at Vqh-0.5 v output level


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PDF 512P8 F18P08 63S481 FECP65 51A-074 SA31-2 63RA481 PLE11P4 F18P06 51A-064 mmi "tiw PROM" programming MMI PLE5P8 63S481 22AA 63S081 PLE9P4 PLE10P4 PLE11P8 PLE9R8 63s281
tl3101

Abstract: 68HCll 68HC11 PCM-123 68hc11 l6
Text: number of bits (up to 5 ) defined by the code selected. The decoder requires up to 5 ADPCM bits and a 2 , circuit . Per-channel control of all algorithm featured are featured in all modes; up to 14 separate ADPCM , or 32 full-duplex channel capacity (48 or 64 channel with two processors) • 2-, 3-, 4- and 5 , Timing for 24- or 32 -Channel Full-Duplex Interleaved Operation.12 Figure 5 . Input and Output Timing , encoding 64 kbit/s Pulse Code Modulation (PCM) to 16, 24, 32 , or 40 kbit/s ADPCM and decoding from ADPCM to


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PDF Bt8110 tl3101 68HCll 68HC11 PCM-123 68hc11 l6
1998 - motorcycle regulator

Abstract: transponder key 74HC4060 transponder digi-key motorcycle ignition e bike motor controller DS40149 74HC4060 2N3904 motor circuit diagram of Garage Door Openers
Text: application circuit is 25 millimeters (one inch). PIN FUNCTIONS Stand-alone transponder decoder , microcontroller interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from , clock to transistor Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce , components used in the decoder circuit as shown in the schematics, in Figure 2 and Figure 3. Table 9 lists , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5 -bit IFF commands or opcodes


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PDF AN675 HCS410 PIC16C56 PIC16C56 motorcycle regulator transponder key 74HC4060 transponder digi-key motorcycle ignition e bike motor controller DS40149 74HC4060 2N3904 motor circuit diagram of Garage Door Openers
1998 - motorcycle ignition circuit diagram

Abstract: circuit diagram voltage regulator for motorcycle LM358n pin motorcycle remote control security system block diagram PIC16C56 LM358 HCS410 AN675 transponder key 74HC4060
Text: application circuit is 25 millimeters (one inch). PIN FUNCTIONS Stand-alone transponder decoder , microcontroller interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from , clock to transistor Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce , components used in the decoder circuit as shown in the schematics, in Figure 2 and Figure 3. Table 9 lists , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5 -bit IFF commands or opcodes


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PDF AN675 HCS410 PIC16C56 PIC16C56 DS00675D-page motorcycle ignition circuit diagram circuit diagram voltage regulator for motorcycle LM358n pin motorcycle remote control security system block diagram LM358 AN675 transponder key 74HC4060
1997 - HD -1553 CMOS manchester encoder-decoder

Abstract: 15531 TDR 5160 pulse transformer 1553 HD3-15531B-9 HD-15531 HD1-15531B-9 HD1-15531B-8 HD1-15531-9 HD1-15531
Text: · Variable Frame Length to 32 Bits · Sync Identification and Lock-In · Separate Manchester II , , the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed , CLK IN DECODER CLK 9 32 SEND DATA SYNCHR CLK SEL 10 31 ENCODER PARITY SEL BIPOLAR , SELECT GATE 17 CHARACTER IDENTIFIER COMMAND SYNC DATA SYNC 5 DECODER CLK DECODER CLK


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PDF HD-15531 MIL-STD-1553 HD-15531 MIL-STD-1553 MIL-STD-1553. HD -1553 CMOS manchester encoder-decoder 15531 TDR 5160 pulse transformer 1553 HD3-15531B-9 HD1-15531B-9 HD1-15531B-8 HD1-15531-9 HD1-15531
1998 - DN7437

Abstract: dual diode ser. 2A 100V SOT23 P3499 motorcycle ignition circuit diagram DS40149 LM78L05ACH key100 93LC46B CIRCUIT DIAGRAM 74HC4060 transponder transponder key
Text: stored in EEPROM. The decoder reads the transponder's 32 -bit serial number, forces the upper 4 bits to 6h , Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce a magnetic field , output DATA_T2B is fed directly to the microcontroller. Table 8 lists the components used in the decoder , interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from the transponder , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5 -bit IFF commands or opcodes


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PDF AN675 HCS410 PIC16C56 PIC16C56 00662B-page DN7437 dual diode ser. 2A 100V SOT23 P3499 motorcycle ignition circuit diagram DS40149 LM78L05ACH key100 93LC46B CIRCUIT DIAGRAM 74HC4060 transponder transponder key
1998 - mode 5 IFF

Abstract: motorcycle regulator ic lm358n motorcycle remote control security system block diagram transponder key e bike motor controller 74HC4060 transponder MOTORCYCLE IGNITION Transponder PPM Transponder texas
Text: application circuit is 25 millimeters (one inch). PIN FUNCTIONS Stand-alone transponder decoder , microcontroller interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from , clock to transistor Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce , components used in the decoder circuit as shown in the schematics, in Figure 2 and Figure 3. Table 9 lists , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5 -bit IFF commands or opcodes


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PDF AN675 HCS410 PIC16C56 PIC16C56 D-81739 mode 5 IFF motorcycle regulator ic lm358n motorcycle remote control security system block diagram transponder key e bike motor controller 74HC4060 transponder MOTORCYCLE IGNITION Transponder PPM Transponder texas
sCapacitor

Abstract: DELTA MODULATION ENCODER BS9450
Text: output filters are incorporated on-chip. Sampling clock rates can be programmed to 16, 32 or 64K bits , Connection Decoder Force Idle: A logical "0" at this pin gates a 0101. pattern internally to the decoder so that the decoder output goes to VD D /2. When this pin is at a logical "1", the decoder operates as , Internal, 32kb/s = f/ 32 Internal, 16kb/s = f/64 Clock rates refer to f = 1,024MHz Xtal/clock input , . relative to the Mil-Std-188-I13 Specification - T -7 5 -1 9 3 2 S' 5 c ·9 1" n . 1 c |- i


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PDF 00012SS MX629 MeetsMil-Std-188-113 MX629 Mil-Std-188-113, BS9450. BS9450 BS9450 sCapacitor DELTA MODULATION ENCODER
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