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Part Manufacturer Description Datasheet Download Buy Part
PIM400K6Z ABB Critical Power PIM400 Series; ATCA Board Power Input Module, -36 to -75 Vdc; 400W/10A, I2C Digital Interface & Short pins (3.68mm)
ISL88016IHTZ-T7A Intersil Corporation 6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C
ISL88017IHTZ-T7A Intersil Corporation 6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C
ISL88017IHTZ-TK Intersil Corporation 6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C
ISL88016IHTZ-TK Intersil Corporation 6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C
ISL88017IHTZ-T Intersil Corporation 6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C

492-Pin Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
12B36

Abstract: RBS 2102 48022 B918 SEQ100 aeq68 MCC141532Z 43256 3b84 MC141532T
Text: MOTOROLA http://www.chipdocs.com MC141532T PIN ASSIGNMENT (COPPER VIEW) MOTOROLA http , Comi 4 Comi 3 MC141532 Die Pin Assignment MC141533 Die Pin Assignment MC141532 • MC141533 3-48 , -0.3 tO VDD+0.3 V I Current Drain Per Pin Excluding VDD and Vss 25 mA Ta Operating Temperature -30 to , Characteristics tables or Pin Description section. Vss = AVSS = DVSS (DVgg = Vgg of Digital circuit, AVSS = Vgg , Drain from Pin AVDD Internal DC/DC Converter On, Display On, Tripler 0 200 300 (xA and DVDD. Enable, R


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PDF MC141532 MC141533 500nA) Mo-104 Seq12 Com20 Seq13 Seq74 12B36 RBS 2102 48022 B918 SEQ100 aeq68 MCC141532Z 43256 3b84 MC141532T
2000 - L45H

Abstract: FW82443BX FW82801AA fw82810 FW82443ZXM FW82443dX FW82805AA-S-L377 FW82801BA FW82443GX FW82820
Text: PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PIN 324 324 324 208 324 , PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PIN 421 241 241 492 492 241 241 , PBGA PBGA PBGA PBGA PBGA PBGA PIN 421 324 324 324 241 241 241 241 544 544 208 492 , PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PIN 241 241 544 544 360 360 360


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PDF FW88386VXSG827000 FW82443ZXMS FW82801AAS FW82806AAS FW82840QPS FW82801BAS FW82801BAMS L45H FW82443BX FW82801AA fw82810 FW82443ZXM FW82443dX FW82805AA-S-L377 FW82801BA FW82443GX FW82820
PLL5220

Abstract: 52C20 9605 mont PLL52C21 100MHZ PLL52C20 puts
Text: PLL52C20/-21 Low Cost Three- PLL Clock Generator FEATURES PIN INFORMATION n Generates up to , reference clock. 3V or 5V operation. Low power CMOS technology Available in 8 pin PDIP or 150mil SOIC , DESCRIPTIONS PIN NUM BER NAME PIN TYPE 1 XIN I Crys tal in put to be con nected to one end , . 2 XOUT O Crys tal out put. DE SCRIP TION 4 FSEL I This pin de ter mines the CLK1 or CLK4 ( pin 5) fre quency. When high, it se lects CLK4. When low, it se lects CLK1. It has in


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PDF PLL52C20/-21 150mil PLL52C20 PLL52C21 PLL5220 52C20 9605 mont 100MHZ puts
OP492

Abstract: No abstract text available
Text: PIN CONNECTIONS APPLICATIONS · · · · · · · Single S u p p ly S ystem s Signal C o n d itio n e rs , OP-292 8- PIN HERMETIC DIP (Z-Suffix) 8- PIN PLASTIC DIP (P-Suffix) 8- PIN SO (S-Suffix) OP-492 14- PIN HERMETIC DIP (Y-Suffix) 14- PIN PLASTIC DIP (P-Suffix) 14- PIN SO (S-Suffix) GENERAL DESCRIPTION The OP


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PDF OP-292/OP-492 OP-292 00V/m OP-492 14-PIN OP-292/492 OP292/492 OP492
24MHZ

Abstract: PLL52C72-04 BI 668
Text: PLL52C72-04 Spread Spec trum Clock Gen er ator with in te grated SDRAM buffers FEATURES PIN , n Mixed voltage support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP. BLOCK DIAGRAM , 10K Pull down is at tached.When SIO is High pin 23 is 24MHZ. FREQUENCY SELECTION (MHz) F3 F2 , in te grated SDRAM buffers SIGNAL DESCRIPTIONS PIN PIN NUM BER TYPE NAME DE SCRIP TION Ref er ence Clock with 2X drive strength. This pin latches in F3 value at power- on. ( see Fre quency


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PDF PLL52C72-04 318Mhz 24Mhz/48MHZ 48Mhz 300mil 24MHZ PLL52C72-04 BI 668
NEC 9902

Abstract: PLL52C32-01 50MHZ MPC932P 9902 ST
Text: clock driver device targeted for Zero Delay applications. PIN INFORMATION The device provides 6 , 2.5V ) 1 Dedicated PLL Feedback Output Output Enable Control 1 common shut down pin to disable all of the ouputs. Output frequency up to 133 MHz. Fully integrated PLL. 32 pin TQFP Packaging 3.3V VCC / 2.5V VCC 100ps Cycle to Cycle Jitter Pin for pin compatible will with the MPC932P FREQUENCY , design. The shut down pins will disable the outputs when driven LOW. A common shut down pin COM_SD is


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PDF PLL52C32-01 PLL52C32-01 100ps NEC 9902 50MHZ MPC932P 9902 ST
9806

Abstract: 48MHZ PLL52C68-06 NEC CIR
Text: PLL52C68- 06 High Speed Spread Spec trum Clock Gen er ator PIN INFORMATION FEATURES n , jitter n Power management control pin to Stop CPU, PCI or Power down all clock outputs. n Mixed voltage support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP FREQUENCY SELECTION (MHz) F2 , Labs. Inc. High Speed Spread Spec trum Clock Gen er ator SIGNAL DESCRIPTIONS NAME PIN NUM BER PIN TYPE VDD1 VDD VDDL1 VDDL2 P P P P VSS 48 9,15,19,21,33 46 41,37 3,6,12,18


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PDF PLL52C68- 133Mhz. 318Mhz, 48Mhz 300mil 9806 PLL52C68-06 NEC CIR
133MHZ

Abstract: DT 9803
Text: delay Skew between any Outputs less than 250ps Frequency up to 133MHZ Available in 300mil 32 pin SOJ , 1.5V VDD+0.5V 0 to 133MHZ 1 to 5ns 1.5V/ns ± 250ps 50% ± 5% 15 PIN INFORMATION 45437 , SIGNAL DESCRIPTIONS NAME PIN NUM BER PIN TYPE VDD 1,5,15,24, 28,32 4,8,18,19, 25,29 16 , ) BIT Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 PIN # Default DE , Bit Bit Bit Bit 7 6 5 4 3 2 1 0 PIN # Default 31 30 27 26 23 22 21 20


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PDF PLL52C69- 440BX 250ps 133MHZ 300mil 133MHZ DT 9803
Not Available

Abstract: No abstract text available
Text: O P -292 and O P -492 include C erD IP and plastic plus SO-8 and SO -14, respectively. PIN , T] outb +IN B OP-292 8- PIN H E RM ETIC DIP (Z-SuffiX) 14- PIN H ERM ETIC DIP (Y -S uffix) 8- PIN PLA STIC DIP (P -S uffix) 14- PIN PLASTIC DIP (P -S uffix) 8- PIN SO (S -S uffix , output stage enables the output to swing to ground w hile sinking current. OP-492 14- PIN SO (S -S


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PDF OP-292/OP-492 14-PIN OP292/492 OP-492
24MHZ

Abstract: 48MHZ PLL52C72-05 Z048
Text: PLL52C72-05 Spread Spec trum Clock Gen er ator with in te grated SDRAM buffers FEATURES PIN , n Mixed voltage support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP. BLOCK DIAGRAM , 10K Pull down is at tached.When SIO is High pin 23 is 24MHZ. FREQUENCY SELECTION (MHz) F3 F2 , in te grated SDRAM buffers SIGNAL DESCRIPTIONS PIN PIN NUM BER TYPE NAME DE SCRIP TION Ref er ence Clock with 2X drive strength. This pin latches in F3 value at power- on. ( see Fre quency


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PDF PLL52C72-05 318Mhz 24Mhz/48MHZ 48Mhz 300mil 24MHZ PLL52C72-05 Z048
OP492

Abstract: No abstract text available
Text: -14, respectively. · · · · · · · PIN CONNECTIONS APPLICATIONS · · · · · · · Single S upply S , [ T IN * [ T V- [T O P-292 8- PIN H E RM ETIC DIP (Z -S u ffix ) 8- PIN P LA S T IC DIP (P -S u ffix ) 8- PIN SO (S -S u ffix ) OP-492 14- PIN H E RM ETIC DIP (Y -S u ffix ) 14- PIN P LA S T IC DIP (P -S u ffix ) 14- PIN SO (S -S u ffix ) GENERAL DESCRIPTION The O P -292/492 dual and quad


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PDF OP-292/OP-492 OP-292 10OV/mV 14-PIN OP292/492 OP492
diode SKE 1/10

Abstract: 10KOHM 24MHZ 48MHZ
Text: PLL52C66- 03 Spread Spec trum 3DIMM Clock Gen er ator with I2C PIN INFORMATION FEATURES n , Available in 300mil 48 pin SSOP. FREQUENCY SELECTION (MHz) F2 F1 F0 CPU/SDRAM PCI 0 0 0 , 133 100.2 25 37.5 41.6 33.4 34.3 37.3 33.3 33.3 SKEW CONTROL SKEW( pin 2) CPU VOLTAGE , are HIGH by de fault and LOW when 10K Pull down is at tached. I/O MODE CONFIGURATION MODE( pin 7 , VDDL1 VDDL2 VSS PIN PIN DE SCRIP TION NUM BER TYPE 1 P Power sup ply for REF0,REF1,crys tal


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PDF PLL52C66- 318Mhz 24Mhz 48Mhz 300mil diode SKE 1/10 10KOHM
SiS530

Abstract: SEL24
Text: PLL52C66-3 1 Spread Spec trum Clock Gen er ator for SiS530 & 620 Chip sets FEATURES PIN , support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP. I/O MODE CONFIGURATION MODE PIN21 1 0 , Labs. Inc. Spread Spec trum Clock Gen er ator for SiS530 & 620 Chip Sets SIGNAL DESCRIPTIONS PIN PIN NUM BER TYPE DE SCRIP TION 1,6,14,19,30, P 3.3V Power sup ply 36 42,48 P Power sup ply for2.5V. Pin 42 for CPU(0:2), pin 48 for IOAPIC. 3,9,16,22 P 3.3V ground. 27,33,39,45 NAME VDD VDDL


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PDF PLL52C66-3 SiS530 318Mhz, 24Mhz 48Mhz 300mil PIN21 PIN20 PIN18 PIN17 SiS530 SEL24
24MHZ

Abstract: 48MHZ PIN14 PLL52C68-02
Text: PLL52C68- 02 High Speed Spread Spec trum Clock Gen er ator with I2C FEATURES PIN INFORMATION , support from 2.5V to 3.3V n Available in 300mil 28 pin SOP FREQUENCY SELECTION (MHz) F2 F1 F0 , NAME PIN NUM BER PIN TYPE VDD1 VDD2 VDD3 VDDL1 VDDL2 VSS 26 20 9,12 25 23 3,15 , clocks. F2 16 I Fre quency in put pin (see Fre quency se lec tion Ta ble) with in ter nal , S48=1, 48MHZ while S48=0. REF/S48 27 B At power- up, this pin is an input to se lect the


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PDF PLL52C68- 133Mhz, 318Mhz 48Mhz 300mil 24MHZ PIN14 PLL52C68-02
Z-15HW4-B

Abstract: omron z-15f Z-15GW2A55-B5V Z-15GQA55-B5V Z-15GL-B Z-15HL2-B Z15F Z-15HL2 Z-15ES-B Z-15GWA55-B5V
Text: models. Drip-proof models use weather-resistive chloroprene rubber. Without Terminal Cover The pin , Standard G (0.5 mm) Pin p g plunger High-sensitivi ty H (0.25 mm) High-capacity E (1.8 mm , ), is also available. 2. The pin plungers of reverse-type models are continuously pressed by the actuator levers with compression coil springs and the pin plungers are freed by operating the levers. Reverse-type models are highly vibration- and shock-resistive because the pin plungers are normally pressed


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PDF RCJ-17-4. Z-15jNJj55, B01-E1-10 Z-15HW4-B omron z-15f Z-15GW2A55-B5V Z-15GQA55-B5V Z-15GL-B Z-15HL2-B Z15F Z-15HL2 Z-15ES-B Z-15GWA55-B5V
PLL52C65-02

Abstract: No abstract text available
Text: PLL52C65-02 Pen tium/SDRAM Clock Gen er ator with In te grated Buff ers PIN INFORMATION , in 300mil 48 pin SSOP. FREQUENCY SELECTION (MHz) F2 F1 F0 CPU/SDRAM BCLK 0 0 , In te grated Buff ers SIGNAL DESCRIPTIONS NAME VDD PIN PIN NUM BER TYPE 7,15,21, P Power , To con fig ure mul ti plexed pin of pin 26,27 and 44 to ei ther in put (MODE=0) or out put (MODE=1). , put for se rial in ter face port SDRAM7//PCISTP 26 B Mul ti plexed pin con trolled by MODE


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PDF PLL52C65-02 48/24Mhz 300mil PLL52C65-02
AGP 9805

Abstract: 9805 ,C 24MHZ 48MHZ st 9805 PLL52C
Text: PLL52C66- 29 Spread Spec trum 3DIMM Clock Gen er ator with AGP & I2C FEATURES PIN INFORMATION , with low jitter n Mixed voltage support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP , (0:3) VDD3 : SDRAM(0:11), 48MHZ, 24MHZ, SDATA, SCLK I/O MODE CONFIGURATION MODE ( Pin 25) PIN21 , SIGNAL DESCRIPTIONS NAME PIN NUM BER PIN TYPE VDD(1:4) P 3.3V Power sup ply P , ex cept PCISTP, CPUSTP, AGPSTP,PD 18,17,9,8 B Mulit plexed pin con trolled by MODE sig


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PDF PLL52C66- 318Mhz, 24Mhz 48Mhz 300mil AGP 9805 9805 ,C st 9805 PLL52C
PLL52C66-23

Abstract: 24MHZ 48MHZ
Text: PLL52C66- 23 Spread Spec trum Clock Gen er ator with 3- DIMM Buffers FEATURES PIN INFORMATION , jitter n Mixed voltage support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP. FREQUENCY , : IOAPIC VDD2 : PCI_F, PCI(0:4) VDD4 : 48MHZ, 24MHZ VDDL2 : CPU(0:1) BLOCK DIAGRAM I/O MODE PIN CONFIGURATION MODE ( Pin 7) 1 (OUT PUT) 0 (IN PUT) PIN2 REF0 PCISTP 45437 Warm Springs Blvd., Fre mont , * PIN PIN NUM BER TYPE 1 6,14 19,30,36 27 48 42 3,9,16,22, 33,39,45 4 5 8,46,25, 26


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PDF PLL52C66- 318Mhz 24Mhz 48Mhz 300mil 9901Rev PLL52C66-23
PLL52C64-05

Abstract: PLL52C64-25 PLL52C64 PLL52C64-06
Text: PLL52C64-06 Clock Gen er ator with Zero De lay Out put Buff ers FEATURES PIN INFORMATION n , . Available in 300mil 24 pin SOP. DESCRIPTION The PLL52C64-06 is a high performance clock generator , DESCRIPTIONS PIN TYPE NAME DE SCRIP TION VDD 12,17,22 P Power sup ply (3V ~ 5V) VDDq2 , and BCLK, all BCLK out puts must be loaded equally. The BCLK6 pin is advised to have a ca paci tive load since this pin is used to feed back to in ter nal 0- delay cir cuits for de lay ad just ing


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PDF PLL52C64-06 PLL52C64-05 PLL52C64-25 250ps 318Mz 24Mhz 48Mhz 150ps) PLL52C64-25 PLL52C64 PLL52C64-06
amphenol connectors

Abstract: AMPHENOL 14 PIN Amphenol Connectors 5 pin male amphenol contact 0 1X311 L311 50 pin connector
Text: Amphenol Economy Solder-Cup D-Subminiatures ED Series FEMALE AMPHENOL LOGO APPEARS ON OPPOSITE SIDE SHOWN FRONT VIEW POSITION I 1 -.041 H |— .060 DIA. BACK VIEW END VIEW FEMALE 50 PIN CONNECTOR f POSITION f 1 FRONT VIEW .112 J" U .109 (TYP) - F - END VIEW DIMENSIONS IN INCHES SHELL SIZE NO. OF CONTACTS A fi C 0 € F E 9 1.220 «35 0.984 0311 .492 .436 A IS 15*7 .962 , SHOWN HALE 50 PIN CONNECTOR FRONT VIEW cr: ■SS b- S=- H1- END VIEW DIMENSIONS IN INCHES


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PDF 2JJ92 1X311 amphenol connectors AMPHENOL 14 PIN Amphenol Connectors 5 pin male amphenol contact 0 1X311 L311 50 pin connector
48MHZ

Abstract: No abstract text available
Text: PLL52C66- 38 Spread Spec trum AGP Clock Gen er ator with 3DIMM Buffers PIN INFORMATION , management control pin to stop clocks. n High speed integrated SDRAM buffers n Supports 2-wire I2C serial , value is readable via I2C n Mixed voltage support from 2.5V to 3.3V n Available in 300mil 48 pin SSOP , ning Stopped Low Run ning Run ning SIGNAL DESCRIPTIONS NAME PIN NUM BER VDD(1:4) P , when CPUSTP is LOW. I SDRAM clock in put pin O SDRAM clocks with fre quen cies de fined by


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PDF PLL52C66- 318Mhz 48Mhz 300mil PIN21 PIN20 PIN18 PIN17 SDRAM10 SDRAM11
Connector 221

Abstract: TT238DCP
Text: ,1 1.74 15,3 0.60 125 4.92 4 0.16 C A D Kodierstift TT9KP16 coding pin , werden. Through the insertion of the coding pin in to unused contact chambers, additional codings can be realized. At this position, no pin contact can be attached to the respective connector/receptacle , temperature range -67°F to +221°F scope of supply coding pin In Kombination mit entsprechenden


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PDF
3743p

Abstract: PLL52C62-01 PLL52C62 P52C62-01
Text: PLL52C62-01 Pen tium/SDRAM Clock Gen er ator with In te grated Buff ers PIN INFORMATION , voltage support from 3.0 to 5V or (VDDq2=2.5V) Available in 300mil 48 pin SSOP. FREQUENCY SELECTION , Buff ers SIGNAL DESCRIPTIONS NAME VDD PIN NUM PIN BER TYPE 7,15,21 P Power sup ply (3V ~ 5V , , Pin 26,27 and 44 will be OUT PUT. When LOW, they are IN PUT. REF1/MODE2 F0/SDRAM10 F1/SDRAM9 F2 , MODE2 is LOW pin 18.19 and 20 are Bidi rec tional , when MODE2 is HIGH they are strictly in puts. F0


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PDF PLL52C62-01 32Mhz) 318Mhz 24Mhz 48Mhz 300mil 3743p PLL52C62-01 PLL52C62 P52C62-01
2005 - 54MBPS

Abstract: JEP95 SST13LP02 SST13LP02-QDF SST13LP02-QDF-K
Text: -00-000 11/05 1 The SST13LP02 is offered in a 24-contact WQFN package. See Figure 1 for pin assignments and Table 1 for pin descriptions. The SST logo and SuperFlash are registered Trademarks of Silicon , RFIN_HB 21 3 NC 22 2 NC 23 1 RFIN_LB NC 24 NC VREF_LB PIN , VCC1_HB NC VCC2_HB NC NC Det_HB 1304 P1.0 FIGURE 1: PIN ASSIGNMENTS FOR 16 , Dual-Band Power Amplifier SST13LP02 Preliminary Specifications PIN DESCRIPTIONS TABLE 1: PIN


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PDF SST13LP02 SST13LP022 18Chuan S71304-00-000 54MBPS JEP95 SST13LP02 SST13LP02-QDF SST13LP02-QDF-K
2006 - MRD 532

Abstract: 24-wqfn-4x4-QD-1 JEP95 SST13LP02 SST13LP02-QDF SST13LP02-QDF-K SST13LP022
Text: -01-000 9/06 1 The SST13LP02 is offered in a 24-contact WQFN package. See Figure 2 for pin assignments and Table 1 for pin descriptions. The SST logo and SuperFlash are registered Trademarks of Silicon , 24 NC VREF_LB Pin Assignments 18 RFOUT_LB 17 GND 16 GND 15 RFOUT_HB , .1 FIGURE 2: Pin Assignments for 16-contact WQFN ©2006 SST Communications Corp. S71304-01-000 3 , Pin DescriptionS TABLE 1: Pin Description Symbol Pin No. Pin Name Type Function GND


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PDF SST13LP02 SST13LP022 S71304-01-000 MRD 532 24-wqfn-4x4-QD-1 JEP95 SST13LP02 SST13LP02-QDF SST13LP02-QDF-K
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