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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
446405-2 TE Connectivity Ltd 8 CONTACT(S), MALE, D SUBMINIATURE CONNECTOR, CRIMP, PLUG
446405-3 TE Connectivity Ltd 8 CONTACT(S), MALE, D SUBMINIATURE CONNECTOR, CRIMP, PLUG
446405-4 TE Connectivity Ltd 8 CONTACT(S), MALE, D SUBMINIATURE CONNECTOR, CRIMP, PLUG
446405-6 TE Connectivity Ltd MALE, D SUBMINIATURE CONNECTOR, PLUG
446405-1 TE Connectivity Ltd AMPLIMITE PLUG ASY,SZ 4,COAX 8C8
TMS416160 Texas Instruments IC FAST PAGE DRAM, Dynamic RAM

4464+64k+dram Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - SCR 131- 6 W 49

Abstract: CL480VCD C-Cube microsystems cd rom 40 pinout
Text: (code FIFO), 34, 40 DRAM /ROM array, 34 internal GBUS registers, 34, 41 address out-of-range interrupt. See AOR interrupt address strobe signals. See UCAS/LCAS AEE_FM DRAM parameter, 201 AEE_MS DRAM parameter, 201 AOR interrupt, 111, 155, 166, 180, 184, 202 ARGUMENT1 DRAM parameter, 204 ARGUMENT2 DRAM parameter, 204 ARGUMENT3 DRAM parameter, 204 ARGUMENT4 DRAM parameter, 204 ARGUMENT5 DRAM parameter, 204 ARGUMENT6 DRAM parameter, 204 ARGUMENT7 DRAM parameter, 204 Index 1 audio data stream ID, 76, 77 data


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PDF ARGUM30, 16-bit, SCR 131- 6 W 49 CL480VCD C-Cube microsystems cd rom 40 pinout
4194304-WORD

Abstract: dram 88 pin dram module
Text: . 57 DRAM Module. 57 [168-pin Buffered DIMM] HB56UW3273 Series 33554432-word x 72-bit DRAM Module. 59 HB56UW3272 Series 33554432-word x 72-bit DRAM Module. 88 HB56UW1673E Series 16777216-word x 72-bit DRAM Module. 104 HB56UW1672E Series 16777216-word x 72-bit DRAM Module. 117 HB56AW1672E Series 16777216-word x 72


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MSM6389B

Abstract: dram MSM6720 MSM65917 MSM514800CP msm5412222b MSM41464 MS8104160 MD56V62160 msm6591
Text: Replacement (if any) Category MD56V62160E (under develop) DRAM MSM514223B P/N Replacement (if any)Category ASM MSM51C2800 DRAM ASM MSM51C2800 DRAM ASM MSM51C4256 DRAM ML62882A MCU MSM51(V)4223C ML62886 MCU MSM514252 ML62886A MCU MSM514256xx DRAM MSM51C4260B DRAM ML62887 MCU MSM514258xx DRAM MSM51V1000 DRAM ML62887A MCU MSM514260Bxx DRAM MSM51V1000 DRAM ML62887B MCU MSM514262V ASM MSM51V4256xx DRAM


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PDF MD56V62160 MD56V62160E MSM514223B MSM51C2800 MSM51C4256 ML62882A MSM51 4223C ML62886 MSM6389B dram MSM6720 MSM65917 MSM514800CP msm5412222b MSM41464 MS8104160 MD56V62160 msm6591
motorola dram 16 x 16

Abstract: DRAM refresh EC000 MC68322
Text: SECTION 7 DRAM CONTROLLER The MC68322 supports fast-page mode DRAM devices. Nibble mode and static column DRAM devices are not supported. The MC68322 directly supports up to six banks of DRAM with bank sizes of 256 Kbytes x 16, 1 Mbyte x 16, and 4 Mbytes x 16. All DRAM sizes are a fixed data width of one , (RGP), printer video controller (PVC), DMA, and EC000 core can make accesses through the DRAM controller. The RGP and PVC utilize burst cycle accesses to maximize DRAM bus bandwidth, while the EC000 core


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PDF MC68322 EC000 256-word motorola dram 16 x 16 DRAM refresh
2004 - PC2-5300F

Abstract: 512MB D-RAM ddr2 dram J0632E80 DDR2 memory organization DRAM elpida 72 pin dimm ELPIDA DDR2
Text: FB-DIMM4.8Gbps 18DIMM FB-DIMM JEDECDDR2 SDRAM Memory Controller DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM AMB AMB AMB DRAM DRAM DRAM DRAM DRAM DRAM DRAM 8 DIMM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DIMM Document No. J0632E80 (Ver.8.0) Date Published February 2007 (K) Japan Printed


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PDF 18DIMM J0632E80 PC2-5300F DDR2-667 667Mbps) 512MB4GB 240-pin 512Mb 512MB PC2-5300F D-RAM ddr2 dram J0632E80 DDR2 memory organization DRAM elpida 72 pin dimm ELPIDA DDR2
ET 8211

Abstract: 8211 720x576 ISO-11172 OTI-8511 OTI8211 CCIR601 OTI-8211 microsparc RISC processor DATA39
Text: data · Supports ISA, Intel, and Motorola bus interfaces · · · · · · · On-chip DRAM , Picture-in-picture support Glueless interface to industry-standard video encoders, audio DACs, and DRAM devices , Review and System DRAM Configurations Functional Review Cont'd. The OTI-8211 utilizes the MicroSPARC , DRAM for decoding and buffering. Standard 4-Mbit DRAM chips may be used via direct connection to the , interactive elements. DRAM Interface and Configuration The DRAM interface generates signals for addressing


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PDF OTI-8211 CCIR601 720x480 720x576 55-Mbps 15-Mbps ET 8211 8211 720x576 ISO-11172 OTI-8511 OTI8211 OTI-8211 microsparc RISC processor DATA39
MCF5206

Abstract: RC10 RC11 00FE0000
Text: SECTION 10 DRAM CONTROLLER 10.1 INTRODUCTION The DRAM controller (DRAMC) provides a glueless interface between the ColdFire core and external DRAM . The DRAMC supports two banks of DRAM . Each DRAM bank can be from 128 kbyte to 256 Mbyte. The DRAMC can support DRAM bank widths of 8, 16, or 32 bits. Two row address strobe (RAS[1:0]) signals are provided externally to access the two DRAM banks. Data byte lanes are enabled using the four column address strobe (CAS[3:0]) signals. The DRAM write (DRAMW) signal


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PDF 33Mhz) 0x00100000 0x000e0000, 0x0010-0x001effff 32-bit 512-byte MCF5206 RC10 RC11 00FE0000
2004 - PC2-6400F

Abstract: pc2 4200F PC2-5300F DRAM elpida dram module elpida memory ddr2
Text: DIMM In the new FB-DIMM, all signals - clock, address, command and data - to and from the DRAM on , helps to secure the DRAM timing margins during high-speed operation, with a much shorter signal path between the DRAM and the AMB. The FB-DIMM also adopts a Point-to-Point connection on the bus between the , Controller Memory Controller DRAM DRAM DRAM DRAM AMB DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM AMB DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM AMB FB-DIMM Point-to-Point architecture (Serial connection) Up to


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PDF 240-pin 512Mb PC2-6400F* PC2-5300F PC2-4200F DDR2-800 800Mbps) PC2-6400F pc2 4200F DRAM elpida dram module elpida memory ddr2
Siemens HYB 41256-12

Abstract: 41256-12 dram 41256-15 511000BJ-70 41256-12 Q67100-Q539 511000BZL-70 514400J-80 514256BZ-70 514400J-10
Text: -20/19 P-ZIP-20/19 P-ZIP-20/19 P-SOJ-26/20 350 mil P-SOJ-26/20 350 mil DRAM (Access Time 100 ns) DRAM (Access Time 120 ns) DRAM (Access Time 150 ns) DRAM (Access Time 60 ns) DRAM (Access Time 70 ns) DRAM (Access Time 80 ns) DRAM (Access Time 60 ns) DRAM (Access Time 70 ns) DRAM (Access Time 80 ns) DRAM (Access Time 60 ns) DRAM (Access Time 70 ns) DRAM (Access Time 60 ns) DRAM (Access Time 70 ns) DRAM (Access Time 60 ns) DRAM (Access Time 70 ns) DRAM (Access Time 80 ns) DRAM (Access Time 60 ns) DRAM


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PDF 511000B-60 511000B-70 511000B-80 511000BJ-60 511000BJ-70 511000BJ-80 511000BJL-60 511000BJL-70 511000BL-60 511000BL-70 Siemens HYB 41256-12 41256-12 dram 41256-15 41256-12 Q67100-Q539 511000BZL-70 514400J-80 514256BZ-70 514400J-10
1997 - m5m4v4169

Abstract: M5M4V4169CRT-10 256K-WORD M5M4V4169TP 70P3S-M 256-kword 1-OF-128 1kx16
Text: -BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM PIN CONFIGURATION (TOP VIEW) Preliminary This , M5M4V4169CRT is a 4M-bit Cached DRAM which integrates input registers, a 262,144-word by 16-bit dynamic memory , monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM /SRAM cache. 2. The , circuit density at reduced costs. FEATURES Type name SRAM Access/cycle DRAM Access/cycle


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PDF M5M4V4169CRT-10 256K-WORD 16-BIT) 1024-WORD M5M4V4169CRT 144-word 16-bit 1024word m5m4v4169 M5M4V4169TP 70P3S-M 256-kword 1-OF-128 1kx16
1996 - CL480 c-cube

Abstract: No abstract text available
Text: 5 DRAM /ROM Interface This chapter describes the local DRAM /ROM interface bus. It details all of the signals necessary to connect the CL48x to a DRAM array and optional ROM. The memory controller in , external DRAMs and ROMs. The maximum transfer rate between the host and DRAM is approximately 2.5 Mbytes per second. The CL48x can be booted directly from ROM or the host can load microcode into DRAM . Figure 5-1 illustrates the DRAM interface bus and how it is used. 5.1.1 DRAM : Amount and Organization 5.1


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PDF CL48x CL480 c-cube
2004 - PC2-5300F

Abstract: ELPIDA sdram dram DDR2-667 dram DRAM elpida elpida module
Text: faster bus speeds. Elpida Memory will continue to expand its FB-DIMM lineup and provide DRAM products , , address, command and data - to and from the DRAM on the module are buffered FB-DIMM Point-to-Point , . This helps to secure the DRAM timing margins DRAM DRAM DRAM during high-speed operation with a much shorter signal path DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM AMB between the DRAM and the AMB. The FB-DIMM also adopts a Point-to-Point connection on the


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PDF 512MB 240-pin 512MB PC2-5300F DDR2-667 667Mbps) E0632E80 PC2-5300F ELPIDA sdram dram DDR2-667 dram DRAM elpida elpida module
51w4260

Abstract: 51W4265C HM 338 262144-WORD
Text: . 129 [64M DRAM ]. 129 HM 5164165A/ 4194304-word x 16-bit DRAM . 131 HM5165165A Series HM5164160A/ 4194304-word x 16-bit DRAM . 164 HM5165160A Series HM 5164805A/ 8388608-word x 8-bit DRAM . 192 HM5165805A Series HM 5164800A/ 8388608-word x 8-bit DRAM


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PDF HM5283206 131072-word 32-bit HM530281R 331776-word HM538253B/ 262144-word HM538254B HM538123B 51w4260 51W4265C HM 338
2004 - PC2-5300F

Abstract: DDR2-533 DDR2-667 MEMORY pc2 ELPIDA DDR2 5300F DRAM elpida elpida module
Text: from the DRAM on the Point-to-Point architecture (Serial connection) module are buffered at the high-speed Advanced Memory DRAM Memory Controller DRAM and the AMB. DRAM DRAM DRAM DRAM operation, with a much shorter signal path between the DRAM DRAM DRAM secure the DRAM timing margins during high-speed DRAM DRAM Buffer (AMB) chip located on the DIMM. This helps to DRAM DRAM DRAM DRAM well as between the DIMMs themselves. This allows DRAM DRAM the bus


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PDF PC2-5300F DDR2-667 667Mbps) PC2-4200F DDR2-533 533Mbps) 512Mb 512MB PC2-5300F DDR2-533 DDR2-667 MEMORY pc2 ELPIDA DDR2 5300F DRAM elpida elpida module
300b tube

Abstract: 90-FBGA-11 165-FBGA-1517 48-TSOP1-1220F 44-TSOP2-400BF-Lead-Free SAMSUNG MCP 0X13 Tube 300b tray bga 64 24-SOJ-300
Text: Samsung Proprietary [ Shipping Quantity Information ] As of 2004-03-02 Divide DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM * 1 , [ Shipping Quantity Information ] As of 2004-03-02 Divide DRAM DRAM DRAM DRAM PKG Name DRAM


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PDF FBGA-11 24-SOJ-300 -SOJ-300 -TSOP2-300AF -SOJ-300B 28-SOJ-300 28-SOJ-300A 28-SOJ-400 300b tube 90-FBGA-11 165-FBGA-1517 48-TSOP1-1220F 44-TSOP2-400BF-Lead-Free SAMSUNG MCP 0X13 Tube 300b tray bga 64 24-SOJ-300
1998 - 1kx16

Abstract: diode wb1 SCR table TK 69 TSOP
Text: MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH , . 2. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576 , size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data , conventional DRAM /SRAM cache. The RAM is fabricated with a high performance CMOS process, and is ideal for , DRAM Access/cycle 49ns/70ns 56ns/80ns 60ns/90ns 75ns/120ns # 70-pin,400-mil TSOP (type II


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PDF M5M4V16169DTP/RT-7 16MCDRAM 16-BIT) 1024-WORD M5M4V16169DTP/RT 16M-bit 576-word 16-bit 1kx16 diode wb1 SCR table TK 69 TSOP
2004 - Not Available

Abstract: No abstract text available
Text: and from the DRAM on the Point-to-Point architecture (Serial connection) module are buffered at the high-speed Advanced Memory DRAM Memory Controller DRAM and the AMB. DRAM DRAM DRAM DRAM operation, with a much shorter signal path between the DRAM DRAM DRAM secure the DRAM timing margins during high-speed DRAM DRAM Buffer (AMB) chip located on the DIMM. This helps to DRAM DRAM DRAM DRAM well as between the DIMMs themselves. This allows


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PDF DDR2-667 667Mbps) PC2-4200F PC2-5300F DDR2-533 533Mbps) 512Mb 512MB
2001 - DB-9 DB25

Abstract: MD8 to DB25 SA15 SA16 SA17 SA18 15PIN D-SUB cable smartBus480 Code 5O
Text: SDRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM POWER DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM POWER DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Volt 5o 5i 5i 5i 5o 5o 5o 5o , DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM POWER DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM POWER DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM POWER DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM SDRAM SDRAM DRAM DRAM DRAM DRAM 3o 3o 3o 3o 3o 3o 3o


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PDF PC/104 SA17-SA19. DB-9 DB25 MD8 to DB25 SA15 SA16 SA17 SA18 15PIN D-SUB cable smartBus480 Code 5O
HYB514100BJ-70

Abstract: L-SIM-30-1 hyb 511
Text: mil P-SOJ-28-3 400 mil 60 ns 1 M x 1 DRAM 30 70 ns 1 M x 1 DRAM 30 80 ns 1 M x 1 DRAM 30 60 ns 1 M x 1 DRAM 30 70 ns 1 M x 1 DRAM 30 80 ns 1 M x 1 DRAM 30 60 ns 1 M x 1 DRAM 30 70 ns 1 M x 1 DRAM 30 80 ns 1 M x 1 DRAM 30 60 ns 1 M x 1 DRAM1 » 30 70 ns 1 M x 1 DRAM ') 30 60 ns 1 M x 1 DRAM '5 30 70 ns 1 M x 1 DRAM1 * 30 60 ns 1 M x 1 DRAM ') 30 70 ns 1 M x 1 DRAM1 » 30 50 ns 16 M x 1 DRAM 172 ; ; 60 ns 16 M x 1 DRAM 172 70 ns 16 M x 1 DRAM 172 80ns 1 6 M x1 DRAM 172 50 ns 1 6 M x 1 DRAM ;:Í72í : 60


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PDF 511000B-60 5110OOB-70 511000B-80 511000BJ-6Q 511000BJ-70 5110Q0BJ-80 511000BZ-60 511000BZ-70 511000BZ-80 511000BL-60 HYB514100BJ-70 L-SIM-30-1 hyb 511
1997 - M5M4V4169

Abstract: No abstract text available
Text: -BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM PIN CONFIGURATION (TOP VIEW) Preliminary This , M5M4V4169CRT is a 4M-bit Cached DRAM which integrates input registers, a 262,144-word by 16-bit dynamic memory , monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM /SRAM cache. 2. The , circuit density at reduced costs. FEATURES Type name SRAM Access/cycle DRAM Access/cycle


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PDF M5M4V4169CRT-10 256K-WORD 16-BIT) 1024-WORD M5M4V4169CRT 144-word 16-bit 1024word M5M4V4169
1997 - rx69

Abstract: BA715 Rx71 C-Cube microsystems C-Cube VRP3 CL4020 Rx68 MD235 MD28
Text: 5 DRAM Interface Functional Description This chapter describes the functional operation of the VRP3's DRAM interface. It consists of these sections: s s s s s s s 5.1, DRAM Configurations 5.2, DRAM Connections 5.3, Address Mapping 5.4, Interleaved DRAM Accesses 5.5, DRAM Access Cycles 5.6, DRAM Refresh 5.7, DRAM Design Schematic 59 DRAM Configurations 5.1 DRAM Configurations The VRP3's internal DRAM controller generates the control signals needed to access the external DRAM array. The CL4020


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PDF CL4020 CL4040, speeds67 74ABT841 CL4040 rx69 BA715 Rx71 C-Cube microsystems C-Cube VRP3 Rx68 MD235 MD28
Micron Designline Vol 8

Abstract: DDR SDRAM designline PC266 Micron DDR SDRAM designline dram ddr 1997 Micron NAND DQS DQSQ ddr designline 1999 Micron Designline Vol 9 micron ddr 1998
Text: SDR DDR /2N PC100/ SDRAM DRAM 2 SDRAM CK) 1 , DDR SDRAM DRAM SDR SDR 2 2 (2) DDR SDRAM 3 WRITE DDR 2N , 2N DRAM / 2N READ 2 2 2 2 WRITE 3 READ 2 4 WRITE WRITE , READ WRITE DRAM DRAM DQS x8 4 READ DQ WRITE x8 x16 DRAM x64 x72 DIMM 9 x8 DRAM X16 1 2 64 72 x16 DRAM x4 DIMM 1 WRITE


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PDF PC100/ PC133 256-Mb Micron Designline Vol 8 DDR SDRAM designline PC266 Micron DDR SDRAM designline dram ddr 1997 Micron NAND DQS DQSQ ddr designline 1999 Micron Designline Vol 9 micron ddr 1998
HY57V641620

Abstract: hy57v64162 CD164
Text: -64-10x10-0.5 * * CD-DA * SDRAM/ DRAM * 16.9344MHz * * / 1M/4M/8M/16Mx16 SDRAM / 1M/4M x16 DRAM , SC9821C 1 Addr<4> SDRAM/ DRAM 4 2 Addr<5> SDRAM/ DRAM 5 3 Addr<6> SDRAM/ DRAM 6 4 Addr<7> SDRAM/ DRAM 7 1.0 Http: www.silan.com.cn 2006.07.21 20 SC9821C 5 Addr<8> SDRAM/ DRAM 8 6 Addr<9> SDRAM/ DRAM 9 7 VDD3.3 8 Addr<10> SDRAM/ DRAM 10 9 Addr<11> SDRAM/ DRAM 11 10 SClk 16.9344M SDRAM/ DRAM


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PDF SC9821C LQFP-64-10x10-0 9344MHz 1M/4M/8M/16Mx16 ICCIOC9821C HY57V641620 hy57v64162 CD164
1997 - CL680 C-Cube

Abstract: C-Cube microsystems
Text: 5 DRAM /ROM Interface This chapter describes the local DRAM /ROM interface bus. It details all of the signals necessary to connect the CL680 to a DRAM array and to the required ROM. The memory , into DRAM . Figure 5-1 illustrates the DRAM interface bus and how it is used. 5.1.1 DRAM : Amount and Organization 5.1 General Description The CL680 DRAM controller can support up to two Mbytes of local Dynamic RAM; however, only four Mbits (512K bytes) of DRAM are needed to read, decode, and output VideoCD


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PDF CL680 70-ns CL680 C-Cube C-Cube microsystems
DRAM Controller

Abstract: 112-12a 100C we32100 8 bit dRAM Controller we32103
Text: WE® 32103 DRAM Controller Description The WE 32103 DRAM Controller provides address multiplexing, access and cycle time management, and refresh control for dynamic random access memory ( DRAM ). In , for a wide range of memory configurations. The DRAM controller is capable of addressing up to 16 Mbytes of DRAM using 1 Mbit chips. The DRAM controller is available in 10-, 14-, and 18-MHz frequency , dual-ported memory configurations using two DRAM controllers • Drives up to 88 DRAM devices without


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PDF 32-bit 18-MHz 125-pin DRAM Controller 112-12a 100C we32100 8 bit dRAM Controller we32103
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