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MSP430-3P-EXTIS-MSP430-PAD-X-ADPT Texas Instruments MSP430-PAD-x Breadboard Units
1017-467-0200 TE Connectivity Ltd PAD HOLDER
SLK2701PZP Texas Instruments TRANSCEIVER, PQFP100, POWER PAD, PLASTIC, VQFP-100
EL5327CL-T13 Intersil Corporation 10 BUFFER AMPLIFIER, QCC24, EXPOSED PAD, LPP-24
EL5427CL-T13 Intersil Corporation 12 BUFFER AMPLIFIER, QCC32, EXPOSED PAD, LPP-32
EL5327CL-T7 Intersil Corporation 10 BUFFER AMPLIFIER, QCC24, EXPOSED PAD, LPP-24
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AD44PA-D SMC Corporation of America Allied Electronics & Automation - $13.35 $13.35
NAD44PA-D SMC Corporation of America Allied Electronics & Automation - $13.35 $13.35

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44-PAD Datasheets Context Search

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Not Available

Abstract: No abstract text available
Text: > 60 Aluminum Bull Eye , Solder Pad , Leadwire , Pin P90 CO4015 CO4015 / CO4015 - F 4 , Bull Eye , Solder Pad , Leadwire , Pin P90 CO4530 CO4530 4.5 3 1.5 , 2 , 3 2.2 K ( -42 , -44 , -46 , 50 )± 3 0.5 50 - 16000 > 60 Aluminum Bull Eye , Solder Pad , Leadwire , ± 3 0.5 50 - 16000 > 60 Aluminum Bull Eye , Solder Pad , Leadwire , Pin P90 CO6012 , Aluminum Bull Eye , Solder Pad , Leadwire , Pin P90 CO6015 CO6015 6 1.5 1.5 , 2 , 3


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PDF CO4012 CO4012 C4012 CO4015 CO4015 CSM4712
2002 - psd3xx

Abstract: PA510 WSI PSD312-b psd3xxl TQFP44 PSD311R PSD302R PSD301R PQFP44 CS10
Text: ) .10 Programmable Address Decoder ( PAD , ).31 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , A11­A15 A8­A10 CSIOPORT A19/CSI A19/CSI ALE/AS PAD A ALE/AS RD AD0­AD7 PAD B WR , Programmable Address decoder ( PAD ) I/O · Latched address output · Open-drain or CMOS output t Two


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PDF PLDCC44 CLDCC44 PQFP44 TQFP44 psd3xx PA510 WSI PSD312-b psd3xxl TQFP44 PSD311R PSD302R PSD301R PQFP44 CS10
1999 - WSI PSD312-b

Abstract: PSD312-B-70J WSI PSD311-B-70J WSI psd3xx PSD312-B-15J PSD302-B-70M PSD302-B-90JI WSI PEP300 PSD3XX WSI pro PROGRAMMER PSD/ZPSD psd301 programming
Text: ) .10 Programmable Address Decoder ( PAD , ).31 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , A8­A10 CSIOPORT A19/CSI A19/CSI ALE/AS PAD A ALE/AS RD AD0­AD7 PAD B WR 13 , Address decoder ( PAD ) I/O · Latched address output · Open-drain or CMOS output t Two Programmable


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PDF 800-TEAM-WSI WSI PSD312-b PSD312-B-70J WSI PSD311-B-70J WSI psd3xx PSD312-B-15J PSD302-B-70M PSD302-B-90JI WSI PEP300 PSD3XX WSI pro PROGRAMMER PSD/ZPSD psd301 programming
2002 - ZPSD301B-90JI

Abstract: STMicroelectronics date code format ZPSD302B-90JI PSD312-B-15J 80C18 PLD Programming Information ZPSD301V-B-25J
Text: ) .10 Programmable Address Decoder ( PAD , ).31 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , PROG. PORT EXP. PC0­ PC2 CSIOPORT A19/CSI PAD A ALE/AS RD 13 P.T. WR RESET LOGIC IN AD8­AD15 PAD B CS8­ CS10 PORT C 27 P.T. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e


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PDF PLDCC44 CLDCC44 PQFP44 TQFP44 ZPSD301B-90JI STMicroelectronics date code format ZPSD302B-90JI PSD312-B-15J 80C18 PLD Programming Information ZPSD301V-B-25J
2002 - psd3xx

Abstract: WSI PSD312-b 80C31-12 INTEL PSD312-B-15J PSD302-B-90JI PSD311-B-70J WSI PSD312-B-90JI PSD311-B-15J 74LS373 Decoder PSD302-B-70L
Text: ) .10 Programmable Address Decoder ( PAD , ).31 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , A11­A15 A8­A10 CSIOPORT A19/CSI A19/CSI ALE/AS ALE/AS PAD A RD AD0­AD7 PAD B WR , Address decoder ( PAD ) I/O · Latched address output · Open-drain or CMOS output t Two Programmable


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PDF PLDCC44 CLDCC44 PQFP44 TQFP44 psd3xx WSI PSD312-b 80C31-12 INTEL PSD312-B-15J PSD302-B-90JI PSD311-B-70J WSI PSD312-B-90JI PSD311-B-15J 74LS373 Decoder PSD302-B-70L
2001 - WSI PSD312-b

Abstract: PSD312-B-70J WSI PSD311-B-15J PSD302-B-70J PSD312-B-15J zpsd312b90ji PSD301-B-15J
Text: ) .10 Programmable Address Decoder ( PAD , ).31 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , /AS RESET OPTIONAL PAGE LOGIC* P3­P0 A16­A18 PROG. PORT EXP. PC0­ PC2 CSIOPORT A19/CSI PAD A ALE/AS RD 13 P.T. WR RESET LOGIC IN AD8­AD15 PAD B CS8­ CS10 PORT C 27 P.T. AD0­AD7


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PDF 800-TEAM-WSI WSI PSD312-b PSD312-B-70J WSI PSD311-B-15J PSD302-B-70J PSD312-B-15J zpsd312b90ji PSD301-B-15J
psd3xx

Abstract: Waferscale Integration PSD301 pmr 210 mb WSI PEP300 PSD3XX PSD311B-15J WSI PSD312-b WSI pro PROGRAMMER PSD/ZPSD PSD312-B-90JI PSD311-B-70J WSI PSD302-B
Text: ) .10 Programmable Address Decoder ( PAD , ).31 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , A8­A10 CSIOPORT A19/CSI A19/CSI ALE/AS PAD A ALE/AS RD AD0­AD7 PAD B WR 13 , Address decoder ( PAD ) I/O · Latched address output · Open-drain or CMOS output t Two Programmable


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PDF 800-TEAM-WSI psd3xx Waferscale Integration PSD301 pmr 210 mb WSI PEP300 PSD3XX PSD311B-15J WSI PSD312-b WSI pro PROGRAMMER PSD/ZPSD PSD312-B-90JI PSD311-B-70J WSI PSD302-B
1996 - 16 bit 8096 microcontroller architecture

Abstract: ARCHITECTURE OF 80186 PROCESSOR intel 80196 microcontroller national semiconductor databook 8096 MICROCONTROLLER ADDRESSING MODES 80c196KB users small signal transistor MOTOROLA DATABOOK 80186 programmer guide 80196 MEMORY INTERFACE intel 80196
Text: port expansion - Zero Power Programmable Address Decoder ( PAD ) I/O - Latched address output - Open drain or CMOS t Two Zero Power Programmable Arrays ( PAD A and PAD B) - Total of 40 Product , equal mappable blocks for optimized mapping 70 ns EPROM access time, including input latches and PAD , access time, including input latches and PAD address decoding t Power Management - CMiser Bit , Security - Locks the ZPSD3XX Configuration and PAD Decoding t Available in a Variety of Packaging -


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PDF ZPSD314R) 16 bit 8096 microcontroller architecture ARCHITECTURE OF 80186 PROCESSOR intel 80196 microcontroller national semiconductor databook 8096 MICROCONTROLLER ADDRESSING MODES 80c196KB users small signal transistor MOTOROLA DATABOOK 80186 programmer guide 80196 MEMORY INTERFACE intel 80196
WSI PEP300 PSD3XX

Abstract: zilog z80 psd303b70j PSD302-B
Text: ). 10 Programmable Address Decoder ( PAD , ).31 16.4 Number ot Product Terms in the PAD Logic. 31 16.5 Composite Frequency of the Input Signals to the PAD Logic , : · · · · Microcontroller I/O port expansion Programmable Address decoder ( PAD ) I/O Latched address output Open-drain or CMOS output Two Programmable Arrays ( PAD A and PAD B) replace your PLD or


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PDF 800-TEAM-WSI 800-TEAM WSI PEP300 PSD3XX zilog z80 psd303b70j PSD302-B
2002 - trimmer 10k

Abstract: 2864 L7 diode WK1D 200S Laser Components iC-WK TS 5225
Text: Diameter 0.7 -0 / +0.1 mm J2 Pad Diameter 1.2 ± 0.05 mm J3 Drill Position vs , mm J5 Drill Position vs. Reference Y (-V) 5.25 ± 0.15 mm J6 Pad Size X (-V,+V) 2.2 ± 0.05 mm J7 Pad Size Y (-V,+V) 2.2 ± 0.05 mm J8 Center Pad vs. Reference X (-V, +V) 1.5 ± 0.3 mm J9 Center Pad vs. Reference Y (+V) 1.5 ± 0.15 J10 Center Pad vs. Reference Y (-V) 4.75 ± 0.15 Laser Connector L1 Center Pad vs. Reference X


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2002 - WK2D

Abstract: 2864 iC-WK 2864 datasheet datasheet ic 2864 200S TS 5225
Text: Diameter 0.7 -0 / +0.1 mm J2 Pad Diameter 1.2 ± 0.05 mm J3 Drill Position vs , mm J5 Drill Position vs. Reference Y (-V) 5.25 ± 0.15 mm J6 Pad Size X (-V,+V) 2.2 ± 0.05 mm J7 Pad Size Y (-V,+V) 2.2 ± 0.05 mm J8 Center Pad vs. Reference X (-V, +V) 1.5 ± 0.3 mm J9 Center Pad vs. Reference Y (+V) 1.5 ± 0.15 J10 Center Pad vs. Reference Y (-V) 4.75 ± 0.15 Laser Connector L1 Center Pad vs. Reference X


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1997 - psd3xx

Abstract: PSD302 PSD303 PSD311 waferscale psd301 programming PSD314R PSD313 PSD312 PSD311 PSD304R
Text: Address Decoder ( PAD ) I/O Latched address output Open drain or CMOS t Two Programmable Arrays ( PAD A and PAD B) - Total of 40 Product Terms and up to 16 Inputs and 24 Outputs - Address Decoding up to , 16 (PSD3X4R) As fast as 70 ns EPROM access time, including input latches and PAD address decoding , fast as 70 ns SRAM access time, including input latches and PAD address decoding t Built-in Page , Security - Locks the device and PAD Decoding configuration Return to Main Menu 4-1 PSD3XX


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Not Available

Abstract: No abstract text available
Text: . 31 16.5 Composite Frequency of the Input Signals to the PAD Logic , €¢ • • • □ Microcontroller I/O port expansion Programmable Address decoder ( PAD ) I/O Latched address output Open-drain or CMOS output Two Programmable Arrays ( PAD A and PAD B) replace , Product terms (13 for PAD A and 27 for PAD B) • Ability to decode up to 1 MB of address without paging , –¡ Built-in security locks the device and PAD decoding configuration □ Wide Operating Voltage Range â


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PDF 800-TEAM-WSI ZPSD313V-B-25L ZPSD313V-B-25M ZPSD313V-B-25U ZPSD313R-B-70J ZPSD313R-B-70M ZPSD313R-B-90JI ZPSD313R-B-90MI ZPSD313R-B-15J ZPSD313R-B-15M
PSD3xx

Abstract: Waferscale Integration PSD301 m60008 psd301 programming PSD304R PSD303 zilog z80 PSD301 MICROCONTROLLER 8031 intel 8098
Text: Address Decoder ( PAD ) I/O Latched address output Open drain or CMOS t Two Programmable Arrays ( PAD A and PAD B) - Total of 40 Product Terms and up to 16 Inputs and 24 Outputs - Address Decoding up to , 16 (PSD3X4R) As fast as 70 ns EPROM access time, including input latches and PAD address decoding , fast as 70 ns SRAM access time, including input latches and PAD address decoding t Built-in Page Logic , Security - Locks the device and PAD Decoding configuration 2-1 PSD3XX Family Key Features t


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psd301-12l

Abstract: PSD302-20XMB PSD312-12J PSD311-20J psd312-12l PSD311-20JI PSD312-12-UI wsi magicpro ii PSD312-20J PSD301-15L
Text: access time, including input latches and PAD address decoding. 16 Kbit Static RAM - M icrocontroller I/O port expansion - Programmable Address Decoder ( PAD ) I/O - Latched address output - Open drain or CMOS Two Programmable Arrays ( PAD A and PAD B) - Configurable as 2K x 8 or as 1K x 16 - 120 ns SRAM access time, Including input latches and PAD address decoding Address/Data Track Mode , PSD3XX Configuration and PAD Decoding Available in a Variety of Packaging - Built-in address latches


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PDF 44-pin 52-pin IL-STD-883C IL-STD-883C psd301-12l PSD302-20XMB PSD312-12J PSD311-20J psd312-12l PSD311-20JI PSD312-12-UI wsi magicpro ii PSD312-20J PSD301-15L
1998 - PSD3xx

Abstract: psd301 programming Waferscale Integration PSD301 SC80C451 PSD301 2Mbit EPROM PSD311 waferscale 80c196KB users PSD312 PSD302
Text: - - - - Microcontroller I/O port expansion Programmable Address Decoder ( PAD ) I/O Latched address output Open drain or CMOS t Two Programmable Arrays ( PAD A and PAD B) - Total of 40 Product , PAD address decoding. t 16 Kbit Static RAM (No SRAM on PSD3XXR versions) - Configurable as 2K x 8 or as 1K x 16 - As fast as 70 ns SRAM access time, including input latches and PAD address decoding , Host Processor t Built-In Security - Locks the device and PAD Decoding configuration For lower


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PAC1000

Abstract: WSI MagicPro II Programmer AP1685
Text: organizations. The M A P I 68 device signifi­ 44-pin Plastic Leaded Chip Carrier package 44-pad Ceram ic , . MAP168 Pin Assignments 44-pin CLDCC Package 44-pin PLDCC Package 44-pad CLLCC Package Pin No , -883C Standard Standard Standard M IL-STD-883C 44-pin PLDCC 44-pin CLDCC 44-pin CPGA 44-pad CLLCC 44-pad CLLCC 44-pad CLLCC 44-pad CLLCC 44-pin PLDCC 44-Pin CLDCC 44-Pin CLDCC 44-pin CLDCC 44-pin CPGA , functional blocks include a Program mable Address Decoder ( PAD ), 16K bytes of high speed EPROM, and 4K


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PDF MAP168 16Kx8 8Kx16 2Kx16 44-pin PAC1000 WSI MagicPro II Programmer AP1685
Not Available

Abstract: No abstract text available
Text: €” Microcontroller I/O port expansion Programmable Address Decoder ( PAD ) I/O — — Latched address output , , including input latches and PAD address decoding. 55 □ — 16 Kbit Static RAM Configurable as 2K x 8 — 120 ns SRAM access time, including input latches and PAD address decoding â , and PAD Decoding Configuration □ □ Two Programmable Arrays ( PAD A and PAD B) May, 1993 , peripheral PSD311 Security Mode Security Mode in the PSD3XX locks the contents of the PAD A , PAD


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PDF PSD311-151 PSD311-20 52-pin 44-pin PSD311-90
1998 - SW7 357

Abstract: HV803 CSI 2702 ausi die attach VP0109ND AF03 VP03 VF01 38495 HV82
Text: for higher operating current densities. Bond pad size represents smaller gate pad . 4. Bond wire size , . Al-Cu-Si is used for higher operating current densities. Bond pad size represents smaller gate pad . 4 , methods may be used with appropriate backmetal option. 6. Drain pad bonding is required. 19-3 18 , attach. Ag backing is optional. 3. Al-Cu-Si is used for higher operating current densities. Bond pad size represents smaller gate pad . 4. Bond wire size and material depends on AuTCB, TSB or Al USB. 5


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PDF VF01/VF06/VF21/VF25 VF22/LND1/LP07 VF05/VF13/VF26/TN07 VF32/LNE1/LP08 HV15/HV16/HV18 HV202 HV204/HV217/HV218/HV227/HV228 HV207 HV208 HV209 SW7 357 HV803 CSI 2702 ausi die attach VP0109ND AF03 VP03 VF01 38495 HV82
PSD311

Abstract: psd3xx T12A T23A PSD311-20 WMCZ philips sc 201
Text: €” Programmable Address Decoder ( PAD ) I/O — Latched address output — Open drain or CMOS □ Two Programmable Arrays ( PAD A and PAD B) — Total of 40 Product Terms and up to 16 Inputs and 24 Outputs â , 8 — 120 ns EPROM access time, including Input latches and PAD address decoding. □ □ 16 Kbit Static RAM Configurable as 2K x 8 120 ns SRAM access time, including input latches and PAD , ) with other Microcontrollers or a Host Processor Built-in Security Locks the PSD311 and PAD Decoding


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PDF PSD311 address/SD311-12KA 44-pin PSD311-12 52-pin PSD311-15 PSD311-151 PSD311 psd3xx T12A T23A PSD311-20 WMCZ philips sc 201
1996 - CMOS 4000 Series family databook

Abstract: 4000 SERIES MOTOROLA DATABOOK small signal transistor MOTOROLA DATABOOK cmos 4000 series databook 16 bit 8096 microcontroller architecture PAL Decoder 8051 intel 8098 intel 8096 microcontroller put databook philips cpbc
Text: Address Decoder ( PAD ) I/O Latched address output Open drain or CMOS t Two Programmable Arrays ( PAD A and PAD B) - Total of 40 Product Terms and up to 16 Inputs and 24 Outputs - Address Decoding up to , 16 (PSD3X4R) As fast as 70 ns EPROM access time, including input latches and PAD address decoding , fast as 70 ns SRAM access time, including input latches and PAD address decoding t Built-in Page , Security - Locks the device and PAD Decoding configuration 2-1 PSD3XX Family Key Features t


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Not Available

Abstract: No abstract text available
Text: □ Two Programmable Arrays ( PAD A & PAD B) — Total of 40 Product Terms and up to 16 , and PAD address decoding. 16 Kbit Static RAM Configurable as 2K x 8 — Programmable Address Decoder ( PAD ) I/O □ — — □ — 19 Individually Configurable I/O pins that can be used , input latches and PAD address decoding □ Address/Data Track Mode — Enables easy , Security Locks the PSD312 and PAD Decoding Configuration — Logic replacement □ — “No


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PDF 44-pin 52-pin PSD312-20I PSD312-20
1997 - psd3xx

Abstract: ZPSD313 ZPSD312 ZPSD311 ZPSD304R ZPSD303 ZPSD302 ZPSD301 M68HC16 SC80C451
Text: - Zero Power Programmable Address Decoder ( PAD ) I/O - Latched address output - Open drain or CMOS t Two Zero Power Programmable Arrays ( PAD A and PAD B) - Total of 40 Product Terms and up to , mappable blocks for optimized mapping 70 ns EPROM access time, including input latches and PAD address , , including input latches and PAD address decoding t Power Management - CMiser Bit: Programmable option , t Built-In Security - Locks the ZPSD3XX Configuration and PAD Decoding t Available in a Variety


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PDF ZPSD314R) psd3xx ZPSD313 ZPSD312 ZPSD311 ZPSD304R ZPSD303 ZPSD302 ZPSD301 M68HC16 SC80C451
1999 - transistor 0882

Abstract: PSD211R CS10 68HC11 68HC05C0 philips 8031 microcontroller N 341 AB hearing aids hearing aid chip HATTELAND
Text: .9 Programmable Address Decoder ( PAD , ).24 16.4 Number of Product Terms in the PAD 16.5 Composite Frequency of the Input Signals to the PAD Logic , A19/CSI A19/CSI ALE/AS ALE/AS RD PAD A WR RESET RD WR 13 P.T. PAD B , expansion Programmable Address decoder ( PAD ) I/O Latched address output t Two Programmable Arrays ( PAD


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PDF PSD211R PSD211R ZPSD211R ZPSD211RV 800-TEAM-WSI transistor 0882 CS10 68HC11 68HC05C0 philips 8031 microcontroller N 341 AB hearing aids hearing aid chip HATTELAND
1998 - 16 bit 8096 microcontroller architecture

Abstract: 8096 microcontroller architecture application 8096 microcontroller features ZPSD301R intel 8096 datasheet hearing aids hearing aid chip 8096/80196 pin diagram 8051 microcontroller DATA SHEET WSI PSD
Text: - Zero Power Programmable Address Decoder ( PAD ) I/O - Latched address output - Open drain or CMOS t Two Zero Power Programmable Arrays ( PAD A and PAD B) - Total of 40 Product Terms and up to , mappable blocks for optimized mapping 70 ns EPROM access time, including input latches and PAD address , 1K x 16 - 70 ns SRAM access time, including input latches and PAD address decoding t Power , Microcontrollers or a Host Processor t Built-In Security - Locks the ZPSD3XX Configuration and PAD Decoding


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PDF ZPSD314R) 16 bit 8096 microcontroller architecture 8096 microcontroller architecture application 8096 microcontroller features ZPSD301R intel 8096 datasheet hearing aids hearing aid chip 8096/80196 pin diagram 8051 microcontroller DATA SHEET WSI PSD
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