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4049 logic gate Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74573

Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
Text: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2-Input NOR Gate Quad 2-Input NAND Gate ( Open collector ) Hex Inverter Hex Inverter ( Open collector ) Hex Inverter ( Open collector ) Hex Buffer Quad 2-Input AND Gate Triple 3-Input NAND Gate Triple 3-Input AND Gate Hex Inverter ( Schmitt trigger ) Dual 4-Input NAND Gate Dual 4-Input AND Gate Triple 3


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1998 - IC 4049

Abstract: CI 4049 cd74hc4049 cd74hc4050 4049 PC 4049 pin diagram
Text: S E M I C O N D U C T O R CD74HC4049, CD74HC4050 High Speed CMOS Logic Hex Buffers, Inverting , silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic supply. For example 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified input protection structure protects the input from negative electrostatic


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PDF CD74HC4049, CD74HC4050 CD74HC4049 CD74HC4050 1-800-4-HARRIS IC 4049 CI 4049 4049 PC 4049 pin diagram
IC 4049

Abstract: 4049 CMOS Inverter CMOS 4049 internal circuit 4049 CMOS hc4050 operation of ic 4049 iC 4049 14 pin LC12480 TA 4049 inverter /74HC/HCT/HCU/4049 hex
Text: M 54/M 74HC 4049 /4050 CIRCUIT SCHEMATIC (Per Gate ) HC4049 HC4050 CHIP CARRIER H C4049 > O O O , DESCRIPTION The M54/74HC4049 and the M54/74HC4050 are high speed CMOS HEX BUFFER fabricated in sili con gate , 74HC 4049 /4050 PIN DESCRIPTION (H C 4 0 4 9 ) PIN No 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 13, 16 8 , Not Connected Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOLS HC4049 1A HC4050 ^ ( 2 , MCBmmETFBWIlKB* 1075 M 54/M 74HC 4049 /4050 RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vi Vo Top tr, tf


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PDF HC4049 54/74HC HC4050 4049B/4050B 74HCXXXXC1R HC4049 HC4050 IC 4049 4049 CMOS Inverter CMOS 4049 internal circuit 4049 CMOS operation of ic 4049 iC 4049 14 pin LC12480 TA 4049 inverter /74HC/HCT/HCU/4049 hex
IC 4049

Abstract: HC 4050 N hct 4049 A104Y
Text: 4050 4049 4049 4050 1Y 1Y 6Y 6Y 2Y 2Y NC 3Y 3Y 5Y Logic , H a rris CD74HC4049, CD74HC4050 High Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting Description The Harris CD74HC4049 and CD74HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic


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PDF CD74HC4049, CD74HC4050 CD74HC4049 CD74HC4050 1-800-4-HARRIS IC 4049 HC 4050 N hct 4049 A104Y
IC 4049

Abstract: ic 4050 pin diagram 4049 logic gate 4049 PC hct 4050 hct 4049 ic 4049 pinout cd74hc4050 4049 pin diagram
Text: LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: N il = 30%, N|h = 30%of Vcc at V CC = 5V CD74HC4049, CD74HC4050 High Speed CM OS Logic Hex Buffers, Inverting and Non-Inverting Description The Harris CD74HC4049 and CD74HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic


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PDF CD74HC4049, CD74HC4050 CD74HC4049 1-800-4-HARRIS IC 4049 ic 4050 pin diagram 4049 logic gate 4049 PC hct 4050 hct 4049 ic 4049 pinout cd74hc4050 4049 pin diagram
IC 4049

Abstract: HC 4050 N cd74hc4050
Text: H a rris CD74HC4049, CD74HC4050 High Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting Description The Harris CD74HC4049 and CD74HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic supply. For example 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified


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PDF CD74HC4049, CD74HC4050 CD74HC4049 CD74HC4050 D74HC4049 1-800-4-HARRIS IC 4049 HC 4050 N
4049 logic gate

Abstract: 4049 cmos
Text: Hex Logic Level Down Converters T - X2.^/ DESCRIPTION The ' 4049 and '4 05 0 have a modified input protection structure that enable them to be used as logic level translators which will convert high level logic to a low level logic while operating from the low logic supply. For exam ple, 0-15V logic can be corverted to 0-5V logic when using a 5V supply. The modified input protection has no diode connected to Vcc , and drive compatibility with 54/74LS logic family · Low power consumption characteristic of CMOS ·


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PDF 54/74LS KS74HCTLS: KS54HCTLS: 300-mil 7Tb414S 90-XO 14-Pin 4049 logic gate 4049 cmos
1998 - Not Available

Abstract: No abstract text available
Text: 1998 - Revised May 2000 High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting structure , Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex , Ld TSSOP Description The 'HC4049 and 'HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic


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PDF CD54/74HC4049, CD54/74HC4050 SCHS205B HC4049 HC4050 SCET004, SCAU001A, SDYZ001A, 5962-8682001EA CD54HC4050F3A
4049 logic gate

Abstract: No abstract text available
Text: 16 3 16 J 13 ] 12 11 ] 10 NC LOGIC DIAGRAMS ' 4049 (2 ) 6Y 14 3 6A ÑC U S* 5A D4 Y , SAMSUNG SEMICON DU CT OR INC 05 4 0 4 9 /4 0 5 1 ) " 7e ! (34145 DGGta?! t . r H ex Logic , input protection structure that enable them to be used as logic level translators which will convert high level logic to a low level logic while operating from the low logic supply. For exam ple, 0-15V logic can be corverted to 0-5V logic when us ing a 5V supply. The modified input protection has no diode


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PDF 7Tb414S 90-XO 14-Pin 4049 logic gate
Not Available

Abstract: No abstract text available
Text: CD74HC4049, CD74HC4050 h a f r f r is S M 0N U T0R E IC D C High Speed CMOS Logic Hex , with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic supply. For example 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified input protection structure protects the input from


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PDF CD74HC4049, CD74HC4050 CD74HC4049 CD74HC4050 1-800-4-HARRIS
1998 - IC 4049

Abstract: pinout diagram of 4049 operation of ic 4049 CD74HC4049 CD54HC4050 CD54HC4049 C4050 C4049 15-V TEXAS INSTRUMENTS 4049
Text: 1Y 1Y 4049 11 3Y 5A 7 5Y 10 3A 4Y 8 9 4A GND Logic Diagrams , [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex CD54HC4049 , CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised July 2004 Features , are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be usedas logic level translators which convert high-level logic to a


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PDF CD74H C4049, C4050) CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 SCHS205H HC4049 IC 4049 pinout diagram of 4049 operation of ic 4049 CD74HC4049 CD54HC4050 CD54HC4049 C4050 C4049 15-V TEXAS INSTRUMENTS 4049
1998 - IC 4049 DATASHEET

Abstract: IC 4049 ic 4049 pinout hct 4049 datasheet CI 4049 HC4049 HC4050 HC4050A TA 4049 15-V
Text: [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex CD54HC4049 , CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised February 2005 , 'HC4049 and 'HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be usedas logic level translators which convert high-level logic to a lowlevel logic while operating off the low-level logic supply. For example, 15-V input pulse


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PDF CD74H C4049, C4050) CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 SCHS205I HC4049 IC 4049 DATASHEET IC 4049 ic 4049 pinout hct 4049 datasheet CI 4049 HC4050 HC4050A TA 4049 15-V
Not Available

Abstract: No abstract text available
Text: CD74HC4049, CD74HC4050 h a f r f r is S M 0N U T0R E IC D C High Speed CMOS Logic Hex , fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic supply. For example 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified input protection structure protects the input from


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PDF CD74HC4049, CD74HC4050 CD74HC4049 CD74HC4050 1-800-4-HARRIS
1998 - IC 4049

Abstract: HC4050 CD74HC4050M CD74HC4049E CD74HC4049 C4050 C4049 15-V CI 4049 IC 4049 DATASHEET
Text: [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex CD74HC4049, CD74HC4050 Data sheet acquired from Harris Semiconductor SCHS205A High-Speed CMOS Logic Hex Buffers , high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which convert high-level logic to a low-level logic while operating off the low-level logic supply. For example, 15-V input pulse levels can be downconverted to 0


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PDF CD74H C4049, C4050) CD74HC4049, CD74HC4050 SCHS205A CD74HC4049 CD74HC4050 IC 4049 HC4050 CD74HC4050M CD74HC4049E C4050 C4049 15-V CI 4049 IC 4049 DATASHEET
1998 - IC 4049

Abstract: IC 4049 DATASHEET C4049 CI 4049 operation of ic 4049 HC4050 ic 4049 pinout TI 4050 hc4049 CD54HC4050F3A
Text: [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex CD54/74HC4049, CD54/74HC4050 Data sheet acquired from Harris Semiconductor SCHS205C High-Speed CMOS Logic Hex , SOP CD74HC4050PW The 'HC4049 and 'HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which convert high-level logic to a lowlevel logic while operating off the low-level logic supply


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PDF CD74H C4049, C4050) CD54/74HC4049, CD54/74HC4050 SCHS205C HC4049 HC4050 IC 4049 IC 4049 DATASHEET C4049 CI 4049 operation of ic 4049 ic 4049 pinout TI 4050 CD54HC4050F3A
1998 - IC 4049

Abstract: ic 4049 pinout CI 4049 HC4050 IC 4049 DATASHEET HC4049 4049 PC C4049 C4050 hct 4049
Text: 1Y 1Y 4049 11 3Y 5A 7 5Y 10 3A 4Y 8 9 4A GND Logic Diagrams , [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex CD54/74HC4049, CD54/74HC4050 Data sheet acquired from Harris Semiconductor SCHS205B High-Speed CMOS Logic Hex , LSTTL Logic ICs CD74HC4049M ­55 to 125 16 Ld SOIC CD54HC4050F3A ­55 to 125 16 Ld , tape and reel. The 'HC4049 and 'HC4050 are fabricated with high-speed silicon gate technology. They


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PDF CD74H C4049, C4050) CD54/74HC4049, CD54/74HC4050 SCHS205B HC4049 HC4050 IC 4049 ic 4049 pinout CI 4049 IC 4049 DATASHEET 4049 PC C4049 C4050 hct 4049
c4049

Abstract: No abstract text available
Text: high-speed Si-gate C M O S device and is pin compatible with the " 4049 " of the "4000B " series. It is specified in compliance with JE D E C standard no. 7 A. The 7 4 H C 4049 provides six inverting buffers with , to 15 V may therefore be used. This feature enables the inverting buffers to be used as logic level translators, which will convert high level logic to low level logic , while operating from a low voltage power supply. For example 15 V logic ("4 0 0 0 B series") can be converted down to 2 V logic . The actual input


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PDF 74HC4049 74HC4049 4000B 7Z93756 c4049
ic 4049 pinout

Abstract: No abstract text available
Text: CD74HC4049, CD74HC4050 High Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting Description The Harris CD74HC4049 and CD74HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic level translators which will convert highlevel logic to a low-level logic while operating off the low-level logic supply. For example 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified input


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PDF CD74HC4049, CD74HC4050 CD74HC4049 CD74HC4050 ic 4049 pinout
1998 - 4049 CMOS Logic ICs

Abstract: HC4050 74hct 4049 Integrated Circuits 4049
Text: 1998 - Revised May 2000 High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting structure , Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V [ /Title (CD74H C4049, CD74H C4050) /Subject (High Speed CMOS Logic Hex , Ld TSSOP Description The 'HC4049 and 'HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be used as logic


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PDF CD54/74HC4049, CD54/74HC4050 SCHS205B HC4049 HC4050 SCAU001A, SDYZ001A, CD54HC4050F3A 5962-8682001EA CD74HC4050 4049 CMOS Logic ICs 74hct 4049 Integrated Circuits 4049
1998 - CD74HC4049NSR

Abstract: CD74HC4049M
Text: SCHS205I February 1998 - Revised February 2005 High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting Description The 'HC4049 and 'HC4050 are fabricated with high-speed silicon gate technology. They have a modified input protection structure that enables these parts to be usedas logic level translators which convert high-level logic to a lowlevel logic while operating off the low-level logic supply. For example, 15-V input pulse levels can be down-converted to 0-V to 5-V logic levels. The modified


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PDF CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050 SCHS205I HC4049 HC4050 inC4049 schm002 sdyu001x CD74HC4049NSR CD74HC4049M
1998 - AN9404

Abstract: PWM 3 phase dc-ac inverter three AN9525 AN9642 AN9611 AN9405 HIP4086
Text: ://www.harris.com. Starting with the HIP4086, the use of negative logic for the high-side input control allows both high and low side MOSFETs of a phase leg to be controlled without added external logic . Undervoltage , Logic Flexibility You can drive the input control logic of the HIP4086 by TTL or CMOS logic . The , pull-up when the inputs are held low. With 5 volts or more at the logic inputs, the input current drops to , a short delay the gate control inputs are again re-enabled. During the delay, the lower MOSFETs are


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PDF AN9642 HIP4086 HIP4086, 1-800-4-HARRIS AN9404 PWM 3 phase dc-ac inverter three AN9525 AN9611 AN9405
1996 - AN9525

Abstract: schematic diagram dc-ac inverter sensor AN9405 AN9642 AN9404 schematic diagram dc-ac inverter three phase schematic diagram dc-ac inverter CMOS 4049 internal circuit HIP4086 AN9611
Text: Starting with the HIP4086, the use of negative logic for the high-side input control allows both high and low side MOSFETs of a phase leg to be controlled without added external logic . This application , , for details. Input Logic Flexibility You can drive the input control logic of the HIP4086 by TTL or CMOS logic . The threshold voltages for input control of the HIP4086 is a guaranteed "one" at or above , more at the logic inputs, the input current drops to less than 1µA. Feature Summary The HIP4086


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PDF AN9642 HIP4086 HIP4086, 1-800-4-HARRIS AN9525 schematic diagram dc-ac inverter sensor AN9405 AN9642 AN9404 schematic diagram dc-ac inverter three phase schematic diagram dc-ac inverter CMOS 4049 internal circuit AN9611
2006 - D1014UK

Abstract: 4049 G200 20swg VG13 VG10
Text: TetraFET D1014UK ROHS COMPLIANT METAL GATE RF SILICON FET MECHANICAL DATA GOLD METALLISED , SUITABLE FOR BROAD BAND APPLICATIONS DP PIN 1 SOURCE PIN 3 PIN 2 DRAIN GATE · LOW , Breakdown Voltage Gate ­ Source Breakdown Voltage Drain Current Storage Temperature Maximum Operating , ://www.semelab.co.uk E-mail: sales@semelab.co.uk 87.5W 70V ±20V 10A ­65 to 150°C 200°C Document Number 4049 , 28V VGS = 0 2 mA VGS = 20V VDS = 0 1 A VGS(th) Gate Threshold Voltage* ID =


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PDF D1014UK 500MHz 100nF 100uF 100pF 1-20pF D1014UK 4049 G200 20swg VG13 VG10
2003 - schematic diagram dc-ac inverter sensor

Abstract: HIP4082 AN9405 schematic diagram dc-ac inverter inductive load Common rail injector driver schematic using ic 4049 BJ10 DC-AC Power Inverter schematic AN9404 HIP4086
Text: 2003 Introduction AN9642.3 Starting with the HIP4086, the use of negative logic for the , external logic . This application note describes the HIP4086 Three Phase MOSFET bridge driver, popular , , for details. Input Logic Flexibility You can drive the input control logic of the HIP4086 by TTL or CMOS logic . The threshold voltages for input control of the HIP4086 is a guaranteed "one" at or , through an internal pull-up when the inputs are held low. With 5V or more at the logic inputs, the input


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PDF HIP4086 AN9642 HIP4086, schematic diagram dc-ac inverter sensor HIP4082 AN9405 schematic diagram dc-ac inverter inductive load Common rail injector driver schematic using ic 4049 BJ10 DC-AC Power Inverter schematic AN9404
1999 - AN9405

Abstract: PWM 3 phase dc-ac inverter three HIP4086 AN9525 AN9404 HIP4082 schematic diagram dc-ac inverter sensor HIP408X AN9611 AN9642
Text: HIP4086, the use of negative logic for the high-side input control allows both high and low side MOSFETs of a phase leg to be controlled without added external logic . Undervoltage Shutdown Undervoltage , of approximately 8.5. See Figure 16 of the HIP4086 [1] data sheet, for details. Input Logic Flexibility You can drive the input control logic of the HIP4086 by TTL or CMOS logic . The threshold , when the inputs are held low. With 5 volts or more at the logic inputs, the input current drops to


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PDF HIP4086 AN9642 AN9405 PWM 3 phase dc-ac inverter three AN9525 AN9404 HIP4082 schematic diagram dc-ac inverter sensor HIP408X AN9611
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