The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
SN74GTL2006PWR Texas Instruments 13-Bit GTL-/GTL/GTL+ To LVTTL Translator 28-TSSOP -40 to 85
SN74GTL2007PW Texas Instruments 12-Bit GTL-/GTL/GTL+ to LVTTL Translator 28-TSSOP -40 to 85
SN74GTL2107PW Texas Instruments 12-Bit GTL-/GTL/GTL+ To LVTTL Translator 28-TSSOP -40 to 85
SN74GTL2107PWR Texas Instruments 12-Bit GTL-/GTL/GTL+ To LVTTL Translator 28-TSSOP -40 to 85
SN74GTL2007PWR Texas Instruments 12-Bit GTL-/GTL/GTL+ to LVTTL Translator 28-TSSOP -40 to 85
SN74GTL2107PWG4 Texas Instruments 12-Bit GTL-/GTL/GTL+ To LVTTL Translator 28-TSSOP -40 to 85
SF Impression Pixel

Search Stock (1)

  You can filter table by choosing multiple options from dropdownShowing 1 results of 1
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
3SK191NI-GTL Murata Manufacturing Co Ltd Bristol Electronics 1,905 - -

No Results Found

3SK191NI-GTL Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1996 - B82 42 004

Abstract: AP-585 AP-589 PGA370 SC242 243332 243658 OA47
Text: .35 GTL + Signal Quality Specifications and Measurement Guidelines .37 Non-GTL , ® CeleronTM Processor System Bus GTL + Decoupling .15 Voltage Identification , .20 GTL + System Bus Specifications , .37 Low to High GTL + Receiver Ringback Tolerance .38 , ® CeleronTM Processor Voltage and Current Specifications . 20 GTL + Signal Groups DC


Original
PDF 32-bit B82 42 004 AP-585 AP-589 PGA370 SC242 243332 243658 OA47
1995 - Not Available

Abstract: No abstract text available
Text: SN74GTL2107 12-BIT GTL ­/ GTL / GTL + TO LVTTL TRANSLATOR www.ti.com SCLS699 ­ JULY 2006 FEATURES · · · · Operates as a GTL ­/ GTL / GTL + to LVTTL or LVTTL to GTL ­/ GTL / GTL + Translator Series Termination , -bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the XeonTM processor GTL ­/ GTL / GTL + I/O , FUNCTION GTL reference voltage Data and enable inputs/outputs (LVTTL) on all inputs and pin 15 output. Remaining outputs are open drain. Data inputs/outputs ( GTL ­/ GTL / GTL +) Ground (0 V) Positive supply voltage


Original
PDF SN74GTL2107 12-BIT SCLS699 000-V A114-B, A115-A) 10AI1 10AI2 10BO1
1996 - celeron B121

Abstract: celeron MOTHERBOARD CIRCUIT diagram 440EX OA47 243335 SCHEMATIC DIAGRAM OF intel 8086 243658 AP-589 AP-585 440LX
Text: Guidelines .37 GTL + Signal Quality Specifications and , Intel CeleronTM Processor System Bus GTL + Decoupling .14 Intel CeleronTM Processor , .20 GTL + System Bus Specifications , Generic Clock Waveform at the Processor Edge Fingers 39 Low to High GTL + Receiver Ringback Tolerance , Specifications .22 GTL + Signal Groups DC Specifications


Original
PDF 32-bit celeron B121 celeron MOTHERBOARD CIRCUIT diagram 440EX OA47 243335 SCHEMATIC DIAGRAM OF intel 8086 243658 AP-589 AP-585 440LX
2002 - GTL2006

Abstract: No abstract text available
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL / GTL + to LVTTL translator Preliminary data 2002 Nov 06 Philips Semiconductors Philips Semiconductors Preliminary data 13-bit GTL / GTL + to LVTTL translator GTL2006 FEATURES translator · Operates as a GTL / GTL + to LVTTL or LVTTL to to GTL / GTL + · , a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the Xeon processor GTL / GTL , FUNCTION GTL reference voltage Data inputs/outputs (LVTTL) Data inputs/outputs ( GTL / GTL +) Ground (0 V


Original
PDF GTL2006 13-bit GTL2006 JESD22-A114, JESD22-A115 JESD22-C101 10AI1 10AI2 10BOI
B92 62 diode

Abstract: atom MOTHERBOARD schematic
Text: . 20 GTL + System Bus Specifications , Measurement Guidelines. 35 GTL + Signal Quality , .37 Low to High GTL + Receiver Ringback Tolerance , . 23 Intel® CeleronTM Processor GTL + Bus Specifications. 23 , ® CeleronTM Processor System Bus AC Specifications ( GTL + Signal Group) at the Processor Edge Fingers


OCR Scan
PDF 32-bit B92 62 diode atom MOTHERBOARD schematic
2000 - CDM 12.6 Philips

Abstract: smd diode marking BN
Text: INTEGRATED CIRCUITS DRAFT ONLY NEEDS NEW ECN NUMBER GTL2004 Quad GTL / GTL + to LVTTL/TTL , Semiconductors Philips Semiconductors Product specification Quad GTL / GTL + to LVTTL/TTL bidirectional latched translator GTL2004 FEATURES · Operates as a quad GTL / GTL + sampling receiver or as a · , protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101 LVTTL/TTL to GTL / GTL + driver , 3.3V system interface with a GTL / GTL + bus. The direction pin allows the part to function as either a


Original
PDF GTL2004 GTL2004 JESD78 JESD22-A114 JESD22-CC101 OT403 CDM 12.6 Philips smd diode marking BN
2005 - GTL2005

Abstract: GTL2005PW GTL2014 JESD22-A114 JESD22-A115 JESD78 TSSOP14 095V
Text: GTL2005 Quad GTL / GTL + to LVTTL/TTL bidirectional non-latched translator Rev. 05 - 6 April 2005 , 3.3 V system interface with a GTL / GTL + bus. The direction pin (DIR) allows the part to function as , 0.8 V. GTL2024 fast tPD GTL2005 medium tPD GTL2014 slow tPD GTL - GTL GTL + 002aab378 Fig 1. GTL2005/GTL2014/GTL2024 positioning 2. Features s Operates as a quad GTL / GTL + sampling receiver or as a LVTTL/TTL to GTL / GTL + driver s Quad bidirectional bus interface s 3.0 V to 3.6


Original
PDF GTL2005 GTL2005 GTL2014 GTL2024 GTL2024 002aab378 GTL2005PW GTL2014 JESD22-A114 JESD22-A115 JESD78 TSSOP14 095V
2001 - k1946

Abstract: 440MX PC core MOTHERBOARD CIRCUIT diagram 243193
Text: -Kbyte write-back data cache On-die second level cache (128-Kbyte) Integrated GTL + termination On-die thermal , .11 2.1.1 On-die GTL + Termination , 2.2.10 GTL + Signals , .35 GTL + AC Signal Quality Specifications , . 54 8.1.1 A[35:3]# (I/O - GTL


Original
PDF 00A/100 16-Kbyte 128-Kbyte) k1946 440MX PC core MOTHERBOARD CIRCUIT diagram 243193
2014 - SCLS746

Abstract: No abstract text available
Text: Documents SN74GTL2014 SCLS746 – FEBRUARY 2014 SN74GTL2014 4-Bits LVTTL to GTL Transceiver 1 , €¢ Operates as a GTL–/ GTL / GTL + to LVTTL or LVTTL to GTL–/ GTL / GTL + Translator The LVTTL Input are Tolerant up to 5.5V Allowing Direct Access to TTL or 5V CMOS The GTL Input/Output Operate up to 3.6V , processor GTL–/ GTL / GTL + I/O. The SN74GTL2014 integrates ESD protection cells on all terminals and is , control Input (LVTTL) B0/1/2/3 2/3/5/6 GTL data input/output A0/1/2/3 13/12/10/9 LVTTL


Original
PDF SN74GTL2014 SCLS746 SN74GTL2014 500mA JESD78 TSSOP14 SCLS746
2009 - GTL2107

Abstract: GTL2107PW JESD22-A114 JESD22-A115 JESD78 TSSOP28
Text: GTL2107 12-bit GTL -/ GTL / GTL + to LVTTL translator Rev. 05 - 23 December 2009 Product data , , GTL -/ GTL / GTL + I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL and GTL signals. 2. Features Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver Operates at GTL , GTL + or GTL - levels EN1 and EN2 enable control 3.0 V to 3.6 V operation LVTTL I/O not 5 , propagation delay GTL2107 NXP Semiconductors 12-bit GTL -/ GTL / GTL + to LVTTL translator 4. Ordering


Original
PDF GTL2107 12-bit GTL2107 JESD22-A114, JESD22-A115, JESD22-C101 JESD78 GTL2107PW JESD22-A114 JESD22-A115 TSSOP28
2009 - Not Available

Abstract: No abstract text available
Text: GTL2005 Quad GTL / GTL + to LVTTL/TTL bidirectional non-latched translator Rev. 07 - 3 February , designed for 3.3 V system interface with a GTL / GTL + bus. The direction pin (DIR) allows the part to , review noise margins. fast tPD GTL2005 GTL2014 slow tPD GTL - GTL GTL + 002aab378 Fig 1. GTL2005/GTL2014 positioning 2. Features I Operates as a quad GTL / GTL + sampling receiver or as a LVTTL/TTL to GTL / GTL + driver I Quad bidirectional bus interface I 3.0 V to 3.6 V operation with 5 V tolerant


Original
PDF GTL2005 GTL2005 GTL2014, GTL2014 002aab378 GTL2005/GTL2014
Not Available

Abstract: No abstract text available
Text: 12-1 : Signal Groups MIOC Pin Group Signals A GTL + Input LOCK#, PHIT(a,b)#, RCM PLT(a,b)#, RHIT(a,b)#, X(0,1)RSTFB#, X(0,1)XRTS#, X(0,1)XSTBN#, X(0,1)XSTBP#, HIT#, HITM # A GTL + Output , )RSTB#, W DEVT# A GTL + I/O Notes A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BPRI , Table 12-2: Signal Groups PXB Pin Group Signals A GTL + Input XBLK#, XH RTS#, XHSTBN#, XHSTBP#, XRST# A GTL + Output XIB, XXRTS#, XXSTBN#, XXSTBP# A GTL + I/O XADS#, XBE[1:0], XD[15:0]#


OCR Scan
PDF
1995 - intel 845 MOTHERBOARD pcb CIRCUIT diagram

Abstract: intel pentium 4 motherboard schematic diagram pentium 4 motherboard CIRCUIT diagram intel 845 MOTHERBOARD CIRCUIT diagram pentium 4 motherboard schematic diagram pentium MOTHERBOARD CIRCUIT diagram intel 845 MOTHERBOARD SERVICE MANUAL 845 motherboard intel pentium 3 motherboard schematic diagram block diagram of processor pentium 1
Text: . 37 1.2. References. 8 3.2. GTL + Signal , . 12 2.4.1. SYSTEM BUS GTL + DECOUPLING . 13 4.2.1. THERMAL SOLUTION PERFORMANCE , . Processor DC Specifications . 20 2.12. GTL + System Bus Specifications . 26 , ) . 85 Figure 2. GTL + Bus Topology. 9 A.1.19 DRDY# (I/O , MHZ, 300 MHZ, AND 333 MHZ Figure 16. Low to High GTL + Receiver Ringback Tolerance


Original
PDF 32-bit intel 845 MOTHERBOARD pcb CIRCUIT diagram intel pentium 4 motherboard schematic diagram pentium 4 motherboard CIRCUIT diagram intel 845 MOTHERBOARD CIRCUIT diagram pentium 4 motherboard schematic diagram pentium MOTHERBOARD CIRCUIT diagram intel 845 MOTHERBOARD SERVICE MANUAL 845 motherboard intel pentium 3 motherboard schematic diagram block diagram of processor pentium 1
Not Available

Abstract: No abstract text available
Text: .12 2.4.1. SYSTEM BUS GTL + DECOUPLING . 13 2.5. Pentium® II Processor System Bus Clock and Processor C , . 20 2.11. Processor DC Specifications. 20 2.12. GTL + System Bus S pecifications , . 37 3.2. GTL + Signal Quality Specifications.39 3.3. Non-GTL+ Signal Quality , . Second Level (L2) Cache Im plem Figure 2. GTL + Bus T , Figure 16. Low to High GTL + Receiver Ringback T olerance


OCR Scan
PDF 32-bit
1995 - A115-A

Abstract: C101 SN74GTL2006
Text: SN74GTL2006 13BIT GTL / GTL / GTL + TO LVTTL TRANSLATOR SCES619 ­ DECEMBER 2004 D Operates as GTL -/ GTL / GTL + to LVTTL or D D D PW PACKAGE (TOP VIEW) LVTTL to GTL -/ GTL / GTL + Translator Series , chipset I/O and the Xeon processor GTL -/ GTL / GTL + I/O. The device is designed for platform health , SYMBOL NAME AND FUNCTION 1 VREF 2­6, 8, 10­13, 15 GTL reference voltage nAn Data inputs/outputs (LVTTL) 7, 9, 16, 17­27 nBn Data inputs/outputs ( GTL -/ GTL / GTL +) 14 GND


Original
PDF SN74GTL2006 13BIT SCES619 000-V A114-B, A115-A) 10AI1 10AI2 SN74GTL2006 A115-A C101
1999 - 400 mhz filter

Abstract: 245112 L-11117 pbga-b615 443BX 440MX 440M 041H diode t40 Mini-Cartridge
Text: microprocessors Low-Power GTL + processor system bus interface Integrated math co-processor , Power GTL + . 8 2.3.1 GTL + Signals , Quality Specifications. 34 4.2 Low Power GTL + Signal Quality Specifications. 35 4.3 Non-Low Power GTL + Signal Quality , BCLK Generic Clock Waveform . 35 Figure 4.2 Low to High, Low Power GTL + Receiver Ringback


Original
PDF 16-Kbyte 128-Kbyte) 400 mhz filter 245112 L-11117 pbga-b615 443BX 440MX 440M 041H diode t40 Mini-Cartridge
2003 - GTL2006

Abstract: No abstract text available
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL -/ GTL / GTL + to LVTTL translator Preliminary data 2003 May 27 Philips Semiconductors Philips Semiconductors Preliminary data 13-bit GTL -/ GTL / GTL + to LVTTL translator GTL2006 FEATURES · Operates as a GTL -/ GTL / GTL + to LVTTL or LVTTL to to GTL -/ GTL / GTL + translator PIN CONFIGURATION VREF 1 1AO 2 2AO 3 5A 4 6A 5 8AI 6 11BI 7 11A 8 9BI 9 , and the Xeon processor GTL -/ GTL / GTL + I/O. The GTL2006 is designed for platform health management in


Original
PDF GTL2006 13-bit GTL2006 10AI1 10AI2 10BOI 10BO2 SW01091 JESD22-A114,
1995 - Not Available

Abstract: No abstract text available
Text: SN74GTL2007 12BIT GTL / GTL / GTL + TO LVTTL TRANSLATOR SCLS609 - MARCH 2005 D Operates as a GTL -/ GTL / GTL + to LVTTL or D D D LVTTL to GTL -/ GTL / GTL + Translator Series Termination on TTL Outputs of 30 , GTL -/ GTL / GTL + I/O. The device is designed for platform health management in dual-processor , GTL reference voltage Data and enable inputs/outputs (LVTTL) Data inputs/outputs ( GTL -/ GTL / GTL , 655303 · DALLAS, TEXAS 75265 1 SN74GTL2007 12BIT GTL / GTL / GTL + TO LVTTL TRANSLATOR SCLS609 -


Original
PDF SN74GTL2007 12BIT SCLS609 000-V A114-B, A115-A) 10AI1 10AI2
1997 - OA79

Abstract: 243191 243341 OA47 AP-585 TagRAM 243335 AP-589 AP-588 Single Edge Contact (S.E.C.) Cartridge:
Text: . 33 1.2. References. 6 3.2. GTL + Signal , . 72 2.12. GTL + System Bus Specifications . 22 6.4. Thermal Specifications , manner as the Pentium Pro processor System Bus. The Pentium II processor System Bus uses GTL + signal , Processor GTL + Guidelines (Order Number 243330) · AP-586, Pentium® II Processor Thermal Design , Gunning Transceiver Logic ( GTL ) signaling technology. The Pentium II processor System Bus specification


Original
PDF 32-bit OA79 243191 243341 OA47 AP-585 TagRAM 243335 AP-589 AP-588 Single Edge Contact (S.E.C.) Cartridge:
1995 - A115-A

Abstract: C101 SN74GTL2107
Text: SN74GTL2107 12-BIT GTL ­/ GTL / GTL + TO LVTTL TRANSLATOR www.ti.com SCLS699 ­ JULY 2006 FEATURES · · · · PW PACKAGE (TOP VIEW) Operates as a GTL ­/ GTL / GTL + to LVTTL or LVTTL to GTL ­/ GTL / GTL + Translator Series Termination on TTL Output of 30 Latch-Up Testing Done to JEDEC Standard , the XeonTM processor GTL ­/ GTL / GTL + I/O. The device is designed for platform health management in dual-processor applications. PIN DESCRIPTION PIN NO. SYMBOL 1 VREF GTL reference voltage NAME


Original
PDF SN74GTL2107 12-BIT SCLS699 000-V A114-B, A115-A) 10AI1 10AI2 A115-A C101 SN74GTL2107
2006 - A115-A

Abstract: C101 SN74GTL2107
Text: SN74GTL2107 12-BIT GTL ­/ GTL / GTL + TO LVTTL TRANSLATOR www.ti.com SCLS699 ­ JULY 2006 FEATURES · · · · PW PACKAGE (TOP VIEW) Operates as a GTL ­/ GTL / GTL + to LVTTL or LVTTL to GTL ­/ GTL / GTL + Translator Series Termination on TTL Output of 30 Latch-Up Testing Done to JEDEC Standard , the XeonTM processor GTL ­/ GTL / GTL + I/O. The device is designed for platform health management in dual-processor applications. PIN DESCRIPTION PIN NO. SYMBOL 1 VREF GTL reference voltage NAME


Original
PDF SN74GTL2107 12-BIT SCLS699 000-V A114-B, A115-A) 10AI1 10AI2 A115-A C101 SN74GTL2107
1996 - B14 diode

Abstract: celeron B121 AP-585 DIODE B36 OA47 celeron MOTHERBOARD CIRCUIT diagram 440EX 243658 AP-589 440LX
Text: Intel CeleronTM Processor System Bus GTL + Decoupling .13 Intel CeleronTM Processor , .20 GTL + System Bus Specifications , Measurement Guidelines .35 GTL + Signal Quality , .37 Low to High GTL + Receiver Ringback Tolerance .38 , Current Specifications .21 GTL + Signal Groups DC Specifications


Original
PDF 32-bit B14 diode celeron B121 AP-585 DIODE B36 OA47 celeron MOTHERBOARD CIRCUIT diagram 440EX 243658 AP-589 440LX
2000 - GTL16612

Abstract: JESD22-A114 JESD22-A115 JESD78
Text: INTEGRATED CIRCUITS GTL16612 18-bit GTL / GTL + to LVTTL/TTL bidirectional universal translator , Jun 19 Philips Semiconductors Product specification 18-bit GTL / GTL + to LVTTL/TTL , bus interface · Translates between GTL / GTL + logic levels (B ports) and The GTL16612 is a , capability: +64 mA/-32 mA on the LVTTL/TTL side (A ports); +40 mA on the GTL / GTL + side (B ports) · TTL , SOT364-1 2 853­2166 23903 Philips Semiconductors Product specification 18-bit GTL / GTL + to


Original
PDF GTL16612 18-bit GTL16612 JESD22-A114 JESD22-A115 JESD78
2003 - GTL2006

Abstract: No abstract text available
Text: INTEGRATED CIRCUITS GTL2006 13-bit GTL -/ GTL / GTL + to LVTTL translator Product data 2003 Dec 18 Philips Semiconductors Philips Semiconductors Product data 13-bit GTL -/ GTL / GTL + to LVTTL translator GTL2006 FEATURES · Operates as a GTL -/ GTL / GTL + to LVTTL sampling receiver or LVTTL to GTL -/ GTL / GTL + driver PIN CONFIGURATION VREF 1 1AO 2 2AO 3 5A 4 6A 5 8AI 6 11BI 7 11A 8 9BI 9 3AO , the 3.3 V LVTTL chip set I/O and the Xeon processor GTL -/ GTL / GTL + I/O. The GTL2006 is designed for


Original
PDF GTL2006 13-bit GTL2006 10BOI 10BO2 SW01091 JESD22-A114, JESD22-A115 JESD22-C101
1996 - Not Available

Abstract: No abstract text available
Text: www.ti.com SN74GTL16923 18-BIT LVTTL-TO-GTL/ GTL + BUS TRANSCEIVER SCBS674G ­ AUGUST 1996 ­ , Enable Translates Between GTL / GTL + Signal Levels and LVTTL Logic Levels Supports Mixed-Mode Signal , / GTL + and GTL /GTL+-to-LVTTL signal-level translation. This device is partitioned as two 9 , logic levels and a backplane operating at GTL / GTL + signal levels. Higher-speed operation is a direct , this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL + (VTT


Original
PDF SN74GTL16923 18-BIT SCBS674G
Supplyframe Tracking Pixel