The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
HA9P2556-9Z Intersil Corporation 57MHz, Wideband, Four Quadrant, Voltage Output Analog Multiplier; SOIC16; Temp Range: -40° to 85°C
HA3-2556-9 Intersil Corporation ANALOG MULTIPLIER OR DIVIDER, 57MHz BAND WIDTH, PDIP16
HA1-2546-5 Intersil Corporation ANALOG MULTIPLIER OR DIVIDER, 30MHz BAND WIDTH, CDIP16
HA1-2556-9 Intersil Corporation ANALOG MULTIPLIER OR DIVIDER, 57MHz BAND WIDTH, CDIP16
CD4089BNSR Texas Instruments CMOS Binary Rate Multiplier 16-SO -55 to 125
MPY100 Texas Instruments ANALOG MULTIPLIER OR DIVIDER, 0.55MHz BAND WIDTH, UUC10

32x32 Multiplier Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
32x32 Multiplier

Abstract: AM29323 block diagram of 32 bit array multiplier
Text: 32x32 MULTIPLIER ARRAY I 0Í32 BIT 1 SHIFTER M 17 BIT ADDER PRODUCT REG BD005250 "IMOX te a , ADVANCED MICRO DEVICES 7t. DE|[)a57SSS G051ÖE1 □ 0257525 ADVANCED MICRO DEVICES 76C 21821 D Am29323 t-*S-O? 32-Bit Parallel Multiplier ADVANCED INFORMATION DISTINCTIVE CHARACTERISTICS 32-Bit Three-Bus Architecture - The device has two 32-bit input ports and one 32-bit output port with maximum , -Bit Parallel Multiplier with 67-Bit Accumulator. The part is designed to maximize system level performance by


OCR Scan
PDF a57SSS Am29323 32-Bit 168-lead 32x32 Multiplier block diagram of 32 bit array multiplier
32x32 Multiplier

Abstract: 74S556 IN3064 IN916 F4732
Text: TO S{ Figure 9 11-34 Monolithic IfliflLI Memories 74S556 Totally Parallel 32x32 Multiplier X - , . The implementation of this twos-complement 32x32 multiplier is shown in Figure 11. The outputs of the , nsec Figure 11. Implementation of the 32x32 Multiplier Monolithic KISD Memories 11 -35 74S556 For , 16x16 Flow-Thru™ Multiplier Slice 74S556 Features/ Benefits • Twos-complement, unsigned , parallel multiplier • Latched or transparent inputs/outputs • Three-state output controls


OCR Scan
PDF 16x16 74S556 32-bit 84-terminal 88-Pin-Grid-Array 16-bit 48-bit 48x48 32x32 Multiplier 74S556 IN3064 IN916 F4732
lm 3933

Abstract: half adder ic number 88-pin-grid 74S556
Text: nsec Figure 11. Implementation of the 32x32 Multiplier Monolithic IfmU M em ories 11-35 , multiplier · Latched or transparent inputs/outputs · Three-state output controls, independent for each half , 16x16 combinatorial multiplier which can multiply two 16-bit unsigned or signed twos-complement numbers , twos-complement number. Additional inputs RS and RU allow the addition of a bit into the multiplier array at the , latches are not required, these control inputs may be tied HIGH, leaving the multiplier fully transparent


OCR Scan
PDF 16x16 32-bit 84-terminal 88-Pin-Grid-Array 74S556 84-te L84-2. 48-bit 48x48 lm 3933 half adder ic number 88-pin-grid
SD4028

Abstract: AM29331 AM29C323 Am29337 Am29325 AM29114 bit-slice ScansUX970 am29c332
Text: -Bit Two-Port Microprogrammable Controller Am29C323 CMOS 32x32 Multiplier Am29325 Bipolar 32-Bit Floating Point


OCR Scan
PDF Am29337 16-Bit 28-Pln KS000010 SD4028 AM29331 AM29C323 Am29325 AM29114 bit-slice ScansUX970 am29c332
link port ts201

Abstract: TS201 ADSP-TS201 FFT TS201 ts201S dab circuitry Architectural innovation in processors "embedded dram" TS101 32X32
Text: DATA 128 L1 IAB 128 128 DAB DAB Y REGISTER FILE 32X32 CLU 128 SHIFTER 128 ALU X REGISTER FILE 32X32 MULTIPLIER MULTIPLIER ALU SHIFTER IN OUT , GENERATION 32 INTEGER J ALU 32X32 32 JTAG 24 MBITS INTERNAL MEMORY MEMORY BLOCKS (PAGE CASHE) INTEGER K ALU 32X32 HOST 4XCROSSBAR CONNECT J-BUS DATA 128 D D SDRAM CTRL 128


Original
PDF TS201, link port ts201 TS201 ADSP-TS201 FFT TS201 ts201S dab circuitry Architectural innovation in processors "embedded dram" TS101 32X32
modified booth circuit diagram

Abstract: carry select adder Modified Booth Multipliers BX232 32 bit booth multiplier for fixed point L64032
Text: X31 X30 Shifting Controlled by CLKX XI _ XO ♦OTIX 32x32 Multiplier Array m o CL. o , Multiplier CLKP > >„ : Temp Y P35:32 P31:0 Architecture The L64032 is a HCMOS 32 x 32-bit fixed point parallel multiplier with a 68-bit accumulator. This device features a three bus architecture to maximize , added to the multiplier output for storage in the P Register. SUB (Negative accumulation) When SUB is HIGH the data in the P Register is subtracted from the multiplier output for storage in the P Register


OCR Scan
PDF L64032 32-Bit 32bit 132-Pin 80nsecs 100nsecs modified booth circuit diagram carry select adder Modified Booth Multipliers BX232 32 bit booth multiplier for fixed point
2008 - ieee embedded system projects free

Abstract: RTC in msp430 i2c application notes ADC10CTL0 cholesterol meter SD16 ADC msp430 MSP430-2274 Flow meter MSP430 ADC10CTL1 Msp430 DSP camera MSP430x2xx
Text: improved voltage reference accuracy ­ Enhanced 32x32 Multiplier · Same tools suite · Major product , ESP430 · Scan IF · · · · · · · LCD/LCD_A DMA Hardware Multiplier Timer A/Timer B USART , · · · · · · · High Performance SoC 60KB Flash / 2.5KB RAM 16MHz CPU 32x32 MPY (4) SD16


Original
PDF MSP430 MSP430 MSP430x2xx/4xx MSP430x5xx C2000TM 16/32-bit TMS470 ieee embedded system projects free RTC in msp430 i2c application notes ADC10CTL0 cholesterol meter SD16 ADC msp430 MSP430-2274 Flow meter MSP430 ADC10CTL1 Msp430 DSP camera MSP430x2xx
74S556

Abstract: DIODE s3l 65 diode S3l 83 max5076 88-pin-grid 54/74S556
Text: bus-organized 16x16 Multiplier / Divider. The device provides both multiplication and division of 2s , multiplier register; X is the multiplicand and divisor register; W is the least-significant half of a , multiplier /divider. These states are represented by a four-bit state counter, where A is the , , Transition Diagram for the 'SS1G Multiplier /Divider Three instruction inputs I 2 . I f . I{). which may , state to state. Thus, the action of the multiplier /divider at any clock period is a function of the


OCR Scan
PDF 16-bit 24-pin 16x16 SN74S516 SN74S516 48x48 64x64 74S556 DIODE s3l 65 diode S3l 83 max5076 88-pin-grid 54/74S556
1999 - FR29

Abstract: FR28 Vector Floating Program Flow Trace architecture st40 Application CPU ST40 SH1 SuperH equivalent led matrix 32X32 hitachi sr 604 FR24 64x32 dram bga
Text: engine sumer products, provides enhanced perfor· Peripherals 37-78 MIPS · 32x32 multiplier · 24 , 128-bit vector · Peripherals 26 MIPS · Peripherals · 32x32 multiplier reduces customers' time to , · 32-bit RISC core · MPU/DSP design TM · Version with PCI · Peripherals · 16x16 multiplier


Original
PDF 64-bit 16/32-bit, 8/16/32-bit PMH15IW001D1 SH-5/ST50-WP FR29 FR28 Vector Floating Program Flow Trace architecture st40 Application CPU ST40 SH1 SuperH equivalent led matrix 32X32 hitachi sr 604 FR24 64x32 dram bga
AM29C323

Abstract: A7 p25 T14X3 AM29C323GC Y0-Y31 32x32 Multiplier PW1232 32-bit adder ScansUX970 Am29C325
Text: Am29C323 CMOS 32-Bit Parallel Multiplier PRELIMINARY DISTINCTIVE CHARACTERISTICS 32-Bit Three-Bus , DESCRIPTION The Am29C323 is a high-speed 32 x 32-Bit CMOS Parallel Multiplier with 67-Bit Accumulator. The , device is housed in a 169-lead pin-grid-array package. SIMPLIFIED BLOCK DIAGRAM PX-BUS PY-BUS 32x32 MULTIPLIER ARRAY 67-BIT ADDER PRODUCT REG | TEMP. REG I I Wlltv I I GEN. I 4-1 Publication # Rev. Amendment , Multiplier Am29C517 CMOS 16x16 Multiplier with Separate I/O DETAILED BLOCK DIAGRAM XSEL YSEL TCX TCY ACCO


OCR Scan
PDF Am29C323 32-Bit 55-ns WF022960 WF022990 A7 p25 T14X3 AM29C323GC Y0-Y31 32x32 Multiplier PW1232 32-bit adder ScansUX970 Am29C325
LH9131-15

Abstract: No abstract text available
Text: MUX 32X32 MULTIPLIER ARRAY - ÊNYÂ -ERIR -ENTR -ERPR FTX - FTY - FTIR - FTPL - FTPR -FA -PSELO , SHARR Data Sheet FUNCTIONAL DESCRIPTION The LH9131 is a 32-bit by 32-bit parallel multiplier , applications. The Multiplier Array provides high speed multiplica tion by using a modified Booth's algorithm , register, and a pipeline register (between the multiplier and accumulator), en ables selection of 0,1, or 2 , supported in the pipeline mode. LH9131 32 x 32 MULTIPLIER / ACCUMULATOR FEATURES · Performs 15/20/23


OCR Scan
PDF LH9131 32-bit 68-bit SMT89001D JAN90 LH9131-15
2010 - RTAX2000

Abstract: leon3 RTAX2000S LEON3FT vhdl code 64 bit FPU IEEE-1754 leon3 processor vhdl AX2000 RTAX*2000 0x81000F
Text: * Multiplication cycle count is 1 clock for the 32x32 multiplier and 4 clocks for the 16x16 version. The processor , . The multiply instructions are performed using a 32x32 pipelined hardware multiplier , or a 16x16 , instruction and data caches, hardware multiplier and divider, on-chip debug support and multiprocessor , / LEON3-FT 2.1.10 Performance Using 8K + 4K caches and a 16x16 multiplier , the dhrystone 2.1 benchmark , interface · Support for 2 - 32 register windows · Hardware multiplier with optional 16x16 bit


Original
PDF 32-bit RTAX2000 leon3 RTAX2000S LEON3FT vhdl code 64 bit FPU IEEE-1754 leon3 processor vhdl AX2000 RTAX*2000 0x81000F
2008 - LEON3FT

Abstract: M Meiko multiplier accumulator MAC code VHDL algorithm leon3 leon processor interrupt vhdl fpu coprocessor IEEE-1754 vhdl code for simple radix-2 SPARC v8 architecture BLOCK DIAGRAM ASR-26
Text: 1 1 1 * Multiplication cycle count is 1 clock for the 32x32 multiplier and 4 clocks for the , reflect the result. The multiply instructions are performed using a 32x32 pipelined hardware multiplier , caches, hardware multiplier and divider, on-chip debug support and multiprocessor extensions. 3 , Performance Using 8K + 8K caches and a 16x16 multiplier , the dhrystone 2.1 benchmark reports 1,500 iteration , windows · Hardware multiplier with optional 16x16 bit MAC and 40-bit accumulator · Radix


Original
PDF 32-bit LEON3FT M Meiko multiplier accumulator MAC code VHDL algorithm leon3 leon processor interrupt vhdl fpu coprocessor IEEE-1754 vhdl code for simple radix-2 SPARC v8 architecture BLOCK DIAGRAM ASR-26
diagram tv Philips plasma 42 logic board

Abstract: MIPS r3000 IBS UART UCB1100 R3000 PR31100ABC PR31100 LQFP208 CS4216 PCMCIA SRAM Card
Text: €¢ high-speed multiplier /accumulator - on-chip hardware multiplier - supports 16x16 or 32x32 multiplier


OCR Scan
PDF PR31100 R3000 PR31100 711GflEb LQFP208: diagram tv Philips plasma 42 logic board MIPS r3000 IBS UART UCB1100 PR31100ABC LQFP208 CS4216 PCMCIA SRAM Card
1996 - MIPS R3000A

Abstract: SN00174 SN00177 R3000A R3000 PR31500ABC PR31500 LQFP208 CS4216 philips monochrome monitor
Text: specification MIPS PR31500 Poseidon embedded processor · high-speed multiplier /accumulator OVERVIEW Each of the on-chip peripherals consist of: ­ on-chip hardware multiplier ­ supports 16x16 or 32x32 multiplier operations, with 64-bit accumulator BIU Module · System memory and PR31500 Bus Interface


Original
PDF PR31500 32-bit R3000 R3000A PR31500 MIPS R3000A SN00174 SN00177 PR31500ABC LQFP208 CS4216 philips monochrome monitor
1996 - mips r3000 pin diagram

Abstract: "ir receiver" preamp UCB1100 R3000 PR31100ABC PR31100 LQFP208 CS4216 R3000 processor PCMCIA SRAM Card
Text: , etc.) ­ on­chip hardware multiplier ­ supports 16x16 or 32x32 multiplier operations, with 64 , physical memory · high­speed multiplier /accumulator ­ supports self­refreshing DRAM and SDRAM ­


Original
PDF PR31100 32-bit R3000 PR31100 mips r3000 pin diagram "ir receiver" preamp UCB1100 PR31100ABC LQFP208 CS4216 R3000 processor PCMCIA SRAM Card
S0123

Abstract: 4x4 bit multipliers Am2505 amd 2500 multiplier diagram Am25LS557 S01-23 7400 fan-out 32x32 Multiplier K217 Am25S05
Text: Am25S05 Four-Bit by Two-Bit Two's Complement Multiplier > 3 ro 01 to o Am2505. GENERAL DESCRIPTION The Am25S05 is a high-speed dig!»»! multiplier that , without correction. The device consists of a 4x2 multiplier that can be connected to form iterative arrays , where the multiplicand and multiplier have different word lengths. The multiplier uses the quaternary , No. Description Am25LS14A 8-Bit Serial/Parallel Multiplier Am25LS557/8 8-Bit by 8-Bit Multiplier


OCR Scan
PDF Am25S05 12-bit 115ns. Am2505. S0123 4x4 bit multipliers Am2505 amd 2500 multiplier diagram Am25LS557 S01-23 7400 fan-out 32x32 Multiplier K217
1998 - TMS320C54x program to multiply two q15 numbers

Abstract: spra454 4 bit left shift circuit for dsp iir filter applications 32x16-bit tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 iIR FILTER implementation in TMS320C54x
Text: . 1 2.1 The 32x32 -bit multiplication , 8 4.1 Extended Precision 32x32 -bit multiplication . , . 22 5.4 Implementation of the 32x32 -bit Direct Form I. 22 , the 32x32 -bit Direct Form II. 24 Extended Precision IIR , the 32x32 -bit Cascade Form . 25 5.6.1 Memory Organization


Original
PDF TMS320C54x SPRA454 TMS320C54x program to multiply two q15 numbers spra454 4 bit left shift circuit for dsp iir filter applications 32x16-bit tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 iIR FILTER implementation in TMS320C54x
AM25S05

Abstract: 4x4 bit multipliers Am25LS14 s0123 71AY K2X x0 multiply 24x24
Text: Am25S05 1 o Four-Bit by Two-Bit Two's Complement Multiplier w DISTINCTIVE CHARACTERISTICS , as compared to Am2505. GENERAL DESCRIPTION The Am25S05 is a high-speed dig!»»! multiplier that , without correction. The device consists of a 4x2 multiplier that can be connected to form iterative arrays , where the multiplicand and multiplier have different word lengths. The multiplier uses the quaternary , No. Description Am25LS14A 8-Bit Serial/Parallel Multiplier Am25LS557/8 8-Bit by 8-Bit Multiplier


OCR Scan
PDF Am25S05 12-bit 115ns. Am2505. 4x4 bit multipliers Am25LS14 s0123 71AY K2X x0 multiply 24x24
Not Available

Abstract: No abstract text available
Text: S0SSZU1V Am25S05 Four-Bit by Two-Bit Two's Complement Multiplier DISTINCTIVE CHARACTERISTICS , multiplier that can multiply numbers represented in the 2 's complement nota­ tion and produce a 2 's complement product without correc­ tion. The device consists of a 4x2 multiplier that can be connected to , therefore be used in arrays where the multiplicand and multiplier have different word lengths. The multiplier uses the quaternary algorithm and performs the function S = XY + K where K is the input field


OCR Scan
PDF Am25S05 115ns. Am2505. 03610B 90SSZUIV
2003 - Architecture of TMS320C67X

Abstract: TMS320C67x C67x Architecture of TMS320C62x C6000 lddw TMS320C6000 programming tms320c6000 SPRA908 architecture tms320c6x
Text: Interrupts Multiplier Test Auxiliary Logic Test Figure 3. TMS320C67x DSP Core Block Diagram The , illustration of these differences. 'C62x CPU 'C67x CPU M-Unit 1 Multiplier Unit M-Unit 1 Multiplier , Arithmetic Logic Unit with Floating Point Register File Register File M-Unit 1 Multiplier , Fetch and Dispatch M-Unit 1 Multiplier Unit with Floating Point Control Register Emulation , MHz · Roadmap to 3 GFLOPS · Roadmap to sub-$50 prices · 24x24-bit and 32x32


Original
PDF SPRA908 TMS320C67x C6000 TMS320C6000 Architecture of TMS320C67X C67x Architecture of TMS320C62x lddw programming tms320c6000 architecture tms320c6x
2010 - matrix circuit VHDL code

Abstract: led matrix 32X32 vhdl code for FFT 32 point vhdl code for cordic LU decomposition 32x32 multiplier verilog code 64x64-bit ieee floating point multiplier verilog vhdl code for cordic multiplication verilog code for matrix multiplication inverse trigonometric function vhdl code
Text: New Levels of DSP Resources The floating-point processing rates are limited by multiplier resources. Altera multiplier densities have progressively increased with each successive family. Figure 1 illustrates the progression of single-precision multiplier density, which has increased over six times from Stratix IV FPGAs to Stratix V FPGAs, and now offers the highest single-precision FPGA multiplier density , optimal floating-point flow. FPGAs, unlike microprocessors, have thousands of hardened multiplier


Original
PDF 28-nm WP-01142-1 28-nm matrix circuit VHDL code led matrix 32X32 vhdl code for FFT 32 point vhdl code for cordic LU decomposition 32x32 multiplier verilog code 64x64-bit ieee floating point multiplier verilog vhdl code for cordic multiplication verilog code for matrix multiplication inverse trigonometric function vhdl code
Not Available

Abstract: No abstract text available
Text: Multiplier ♦ Differential Clock Inputs » Separate 8-bit VGA Port ♦ Programmable 64x64x2 Hardware , 64x64x2 cursor with its own color registers. On-chip 2X dock multiplier doubles the pixel output rate , by MUX rate depending on the operating mode selected. If 2X dock multiplier is selected(CR33-1), the , multiplier is selected(CR33=1), the SCLK output is equal to selected PCLK divided by 1/2,1, or 2 , coefficients are not specified or required. Note 1 : To pipeline data at above 85MHz, the 2X dock multiplier


OCR Scan
PDF 135MHz KDA0485 85MHz 64x64x2 256x8 84-Pin KDA0485/0486 KDA0485L-135 135MHz
1997 - musical applications of microprocessor

Abstract: hitachi sh3 1995 cel hitachi hitachi sh3 SH7042 SH7034 SH7032 120M SH7021 mobile camera interface microcontroller
Text: this is not taken into account. DSP block; a hardware multiplier /accumulator. Unlike most 32 , Integr , 128k(flash)/6k SH2 Core, 32x32 + 64-bit MAC rs, Engine Mgmt ASSP (16 channels), SCI x 3, Time A/D 168-pin 20MIPS/5V SH7042 SH7034 , 128k/4k or 1k I cache SH2 Core, 32x32 + 64 , , 12.5MIPS SH7043 SH7032 , 128k/4k or 1k I cache SH2 Core, 32x32 + 64-bit MAC ASSP A/D, SCI x 2 , Point, 8k Cache SH3 µCBIC Core e rmanc Perfo SH7708 SH3 Core, 8/16/32 bit Bus 32x32 + 64


Original
PDF D-85622 D-85619 musical applications of microprocessor hitachi sh3 1995 cel hitachi hitachi sh3 SH7042 SH7034 SH7032 120M SH7021 mobile camera interface microcontroller
CR331

Abstract: CR21A
Text: Multiplier Differential Clock Inputs Separate 8-bit VGA Port Programmable 64x64x2 Hardware Cursor Triple , -bit DACs, and 64x64x2 cursor with its own color registers. On-chip 2X dock multiplier doubles the pixel , multiplier is selected(CR33-1), the SCLK output is equal to either PCLKO or PCLK1 divide by 4, 2, or 1, or , ,2 , or 4. If 2X dock multiplier is selected(CR33-1), the SCLK output is equal to selected PCLK , coefficients are not specified or required. Note 1 : To pipeline data at above 85MHz, the 2X dock multiplier or


OCR Scan
PDF 35MHz KDA0485 85MHz 64x64x2 256x8 84-Pin KDA0486. KDA0485/0486 CR331 CR21A
Supplyframe Tracking Pixel