The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LT1796IS8#TR Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1796IN8 Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: PDIP; Pins: 8; Temperature Range: -40°C to 85°C
LT1796IS8 Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1796CN8 Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
LT1796IS8#TRPBF Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1796CS8#TR Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C

32x16-bit Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - TMS320C54x program to multiply two q15 numbers

Abstract: spra454 4 bit left shift circuit for dsp iir filter applications 32x16-bit tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 iIR FILTER implementation in TMS320C54x
Text: . 3 2.2 The 32x16-bit multiplication , 8 4.2 Extended Precision 32x16-bit or 16x32- bit multiplication . 9 5 , Implementation of the 32x16-bit Direct Form I. 10 5.1.1 Circular , the 32x16-bit Direct Form II. 13 5.2.1 Memory organization , . 17 5.3 Implementation of the 32x16-bit Cascade Form . 17


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PDF TMS320C54x SPRA454 TMS320C54x program to multiply two q15 numbers spra454 4 bit left shift circuit for dsp iir filter applications 32x16-bit tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 iIR FILTER implementation in TMS320C54x
AN795

Abstract: APP795 MAX4355 MAX4356 MAX4357 MAX4358 video display on-screen programming circuit
Text: then sends a 16- bit word consisting of four chipaddress bits, 11 payload bits, and (to make the word two bytes long) one "don't care" bit . The 11- bit data payload consists of four bits to select the output to be programmed, five bits to select the input to be connected to that output, one bit to set the gain of the output buffer, and one bit to control whether that output is put into disable mode , data word, the first bit is the LSB of the device most remote in the chain, and the last bit is the


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PDF 32x16 com/an795 MAX4355: MAX4356: MAX4357: MAX4358: AN795, APP795, Appnote795, AN795 APP795 MAX4355 MAX4356 MAX4357 MAX4358 video display on-screen programming circuit
2003 - Au1000

Abstract: AMD AU1000 Au1000-266MCI MIPS32 400Mhz MIPS32 Au1000-500MCC MIPS32 instruction set a/S3C9004/P9004/C9014/Reset Software for Alchemy Au1000 Processor
Text: CPU Pipeline · Executes all Integer Multiply and Divide Instructions · 32x16-bit MAC Hardware , MIPS CPU Core · · · · · · 266, 400 or 500MHz MIPS32 Instruction Set 32- bit Architecture


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PDF Au1000TM 400MHz Au1000 MIPS32TM 500MHz. 26328E-US MIPS32 AMD AU1000 Au1000-266MCI MIPS32 400Mhz Au1000-500MCC MIPS32 instruction set a/S3C9004/P9004/C9014/Reset Software for Alchemy Au1000 Processor
2000 - maxim analog design guide 12 3RD

Abstract: MAX4360 MAX4436 MAX453 MAX4416 MAX4415 MAX4414 MAX4413 MAX4412 maxim, analog design guide, interface
Text: ) 3.43 5.16 6.00 18.50 18.50 World's Smallest 16- Bit Accurate, 280MHz Op Amps Settle to 0.0015 , 3.0 LARGE-SIGNAL PULSE RESPONSE INPUT 500mV/div IN 14/16- BIT ADC MAX4430 OUTPUT , wide bandwidth, fast 16- bit settling time, and low-noise/low-distortion operation critical for , 1MHz (4Vp-p), and fast 37ns 16- bit settling time make these amplifiers ideal for driving modern, high-speed 14- and 16- bit ADCs. No. of Amps Minimum Gain Stable Settling Time to 0.0015% (ns


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PDF 32x16 144-Pin 100MHz MAX458 MAX456 140MHz, MAX4138 185MHz, MAX4137 maxim analog design guide 12 3RD MAX4360 MAX4436 MAX453 MAX4416 MAX4415 MAX4414 MAX4413 MAX4412 maxim, analog design guide, interface
AN795

Abstract: MAX4355 MAX4356 MAX4357 MAX4358
Text: the address is set by strapping four external pins on the package. The host then sends a 16- bit word , " bit . The 11- bit data payload consists of four bits to select the output to be programmed, five bits to select the input to be connected to that output, one bit to set the gain of the output buffer, and one bit to control whether that output is put into disable mode. This method programs (configures , are programmed with one long programming word. Within this long data word, the first bit is the


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PDF 32x16 MAX4355: MAX4356: MAX4357: MAX4358: com/an795 AN795 MAX4355 MAX4356 MAX4357 MAX4358
1997 - XC6200

Abstract: XAPP063 32x16-pixel correlator XACT6000 32x16 512X512 "frame grabber"
Text: shifted into the 32 bit long pipeline as the next column is written by the control program to the , extra carry in delayed by three clock cycles to make a 31 bit correlator; and so on, until a 511 pixel , image begins. The overflow or carry appears in the single bit Hit register. 6 A 32x16 , (t); // The hardware comparator works by generating a carry in // a 9 bit addition rather than


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PDF 32x16 XC6200 XC6200 XAPP063 32x16-pixel correlator XACT6000 512X512 "frame grabber"
2008 - 4x2 lcd

Abstract: ISL59532 ISL59910 portable dvd player Video Filter Amplifier KVM SWITCH ISL54100 EL9112 portable dvd player with lcd VIDEO CROSSPOINT SWITCH DIGITAL COLOR TV RECEIVER
Text: bit of equalization, but only Intersil's ISL54100/01/02 feature Clock Data Recovery on each channel , Analog Front Ends Industry's Most Highly Integrated 10- Bit Triple Video Digitizer Intersil's ISL51002 delivers true 10- bit performance at a 165MSPS maximum conversion rate, supporting resolutions up , ABLCTM 10- bit ADC 3 10- bit ADC ABLCTM ABLCTM Color Space Converter 4:1 Mux 3 , 10- bit ADC 3 Digital PLL Digital Signal RED GREEN BLUE ISL51002 3 Speed Grades


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PDF ISL54100/01/02 ISL54100 1-888-INTERSIL LC-042 4x2 lcd ISL59532 ISL59910 portable dvd player Video Filter Amplifier KVM SWITCH ISL54100 EL9112 portable dvd player with lcd VIDEO CROSSPOINT SWITCH DIGITAL COLOR TV RECEIVER
2001 - stk 442 -130

Abstract: STK 442 130 STK 442 - 130 STK 4202 STK 499 stk 442 -120 STk 442 120 MAX4436 stk3535 stk 430 130
Text: 19,74 Kleinste 280MHz OPVs am Markt mit 16- Bit Genauigkeit und 37ns Einschwingszeit auf 0,0015 , 500mV/div EINGANG 14/16- BIT ADC MAX4430 AUSGANGSSIGNAL 500mV/div 10ns/div -5V ·


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PDF 32x16-Videokoppelfeld 32x16-Matrix 144-poliges MAX458 MAX456 140MHz, MAX4138 185MHz, MAX4137 stk 442 -130 STK 442 130 STK 442 - 130 STK 4202 STK 499 stk 442 -120 STk 442 120 MAX4436 stk3535 stk 430 130
2001 - ALCHEMY SEMICONDUCTOR

Abstract: MIPS32 instruction set Au1500 MIPS32
Text: Set 32- Bit Architecture 16KB Instruction and 16KB Data Caches High Speed Multiply-Accumulate (MAC) and Divide unit 1.5-1.8 V Core, 3.3 V I/O Highly-Integrated System Peripherals 33/66 MHz 32- bit PCI , Au1500 Internet Edge Processor TM ® A High Performance/Low Power MIPS SOC SDRAM 32 bit PCI , pipeline Executes all integer multiply and divide instructions 32 x 16- Bit MAC hardware MMU Instruction , Core Configurable as Host or Satellite 32 bit address/data bus 33 MHz/66MHz Source or sink clock


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PDF Au1500 Au1500 MIPS32 Hz/66MHz 400mW 700mW Au1500, ALCHEMY SEMICONDUCTOR MIPS32 instruction set
2000 - Alchemy Semiconductor

Abstract: MIPS32 Au1000 MIPS32TM MIPS32 instruction set a/S3C9004/P9004/C9014/Reset Software for Alchemy Au1000 Processor
Text: , 400 or 500 MHz MIPS32 Instruction Set 32- Bit Architecture 16KB Instruction and 16KB Data Caches , instructions 32 x 16- Bit MAC hardware Caches 16KB Non-Blocking Data Cache 16KB Instruction Cache


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PDF Au1000TM Au1000 MIPS32TM 4KB-16MB Au1000, Alchemy Semiconductor MIPS32 MIPS32 instruction set a/S3C9004/P9004/C9014/Reset Software for Alchemy Au1000 Processor
2006 - ISL59534

Abstract: ISL59534IKEZ ISL59535 V356 IN23D
Text: . AV X1, X2 OUTPUT ENABLE VSDO SDO first and the MSB ( bit 15) is loaded last (see the , incoming data on the SDI pin, delayed by 15.5 SCLKs (an input bit is latched on the rising edge of SLCK , interface. Data on the SDI (serial data input) pin is shifted into a 16- bit shift register on the rising , SLATCH signal.) The LSB ( bit 0) is loaded 16 FN6249.5 February 7, 2007 ISL59534 Serial Timing , (latching B15) to SLATCH rising edge Programming Model The ISL59534 is configured by a series of 16- bit


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PDF ISL59534 FN6249 32x16 ISL59534 300MHz ISL59534IKEZ ISL59535 V356 IN23D
1998 - EHDFD

Abstract: EHFFD1503
Text: No file text available


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PDF 20min 18min) 15min 18min 17min EHDFD EHFFD1503
Not Available

Abstract: No abstract text available
Text: the 32x16-bit write data packet. The write data is then driven to the selected Sense Amp Array Bank , access. A packet is a set of bit windows on the signals of a bus. There are two buses that carry packets , . The RQ11.0 pins receive the request packet. Two 12- bit words are received in one tCYCLE interval , the 24- bit request packet. These 24 bits are loaded into a register (clocked by the 1/tCYCLE clocking , 4- bit operation code that specifies packet format. (Encoded commands are in Table 3 on page 12).


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PDF EDX1032BBBG EDX1032BBBG M01E1007 E1819E20
2011 - E1819E20

Abstract: XDR 1gb EDX1032BBBG
Text: to the 1:16 Demux Block that assembles the 32x16-bit write data packet. The write data is then driven , packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus , present in the actual memory component. The RQ11.0 pins receive the request packet. Two 12- bit words are , Demux Block that assembles the 24- bit request packet. These 24 bits are loaded into a register (clocked , Description 4- bit operation code that specifies packet format. (Encoded commands are in Table 3 on page 12


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PDF EDX1032BBBG EDX1032BBBG EDX1032BBBG, M01E1007 E1819E20 E1819E20 XDR 1gb
2008 - 32x16 LED Matrix

Abstract: EN25 80 LMH1980 LMH6586 LMH6586VS EN19 EN26 JESD22-C101-C
Text: MHz I2C compatible interface with 2- bit programmable slave address Single +5V supply operation , disable the Input Detect Flag feature for video detect, where the register bit for the input channel is , level can be set with a 3- bit programmable register. Video detection may be implemented in an , these configurations, where the register bit for the input channel is set to a logic LOW if loss of , in power save mode by using the appropriate power save bit in the power save registers. By doing so


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PDF LMH6586 32x16 LMH6586 32x16 LED Matrix EN25 80 LMH1980 LMH6586VS EN19 EN26 JESD22-C101-C
1998 - EHDFD

Abstract: EHDFD 1517 us 1640 telephone hybrid 32X16 EHFFD1503
Text: No file text available


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PDF 20min 18min) 15min 18min 17min EHDFD EHDFD 1517 us 1640 telephone hybrid 32X16 EHFFD1503
1996 - Z86193

Abstract: Z86295 Z86C95 Z86C9500ZUSP064 Z86C9501ZUSP064 MICROCONTROLLER 16 bit cmos 16 bit counter
Text: Z86C95 Device UART DIV P3 CPU Z86295 P3 OSC A15-A0 Z86193 88- BIT R-S , : 40 MHz CMOS: 40 MHz t t t t t t t t t 8- Bit Z8 Microcontroller 16- Bit Slave DSP Eight Channel - 8- Bit ADC 8- Bit DAC Three 16- Bit Counter/Timers 16- Bit Multiply/Divide Full-Duplex , Evaluation Board Z8619300ZEM - Macrochip Emulator Z8619300ZCO - Evaluation Board Features 8- Bit Z8 Microcontroller 16- Bit DSP Co-Processor 6 Channel - 10- Bit ADC 10- Bit ADC Serial Peripheral Interface (SPI


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PDF A15-A0 A15-0 Z86C95 Z86295 Z86193 88-BIT Z86018 10-Bit Z86193 Z86295 Z86C95 Z86C9500ZUSP064 Z86C9501ZUSP064 MICROCONTROLLER 16 bit cmos 16 bit counter
Not Available

Abstract: No abstract text available
Text: S-18 ^ S L Q b B lo c k D ia g r a m M ass S torage S 88- BIT R -S ECC SR AM , Channel 8- Bit ADC 8- Bit DAC 16- Bit Multiply/Divide Full-Duplex UART Serial Peripheral Interface (SPI) Three Standby Modes (STOP/HALT/PAUSE) Pulse Width Modulator (PWM) 3 *1 6- Bit Timer 16- Bit D SP Slave Processor 83 ns Multiply/Accumulate Futl-Track Read Automatic Data Transfer (Point & Go®) 88- Bit Reed , Modes (S TO P S . H ALT) Three 16- Bit Counter/Timers SEARC H Machine M ER G E Machine Bus Request Mode


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PDF 88-BIT A15-AO Z86193 A15-A0 Z88C95 Z86018 Z86295 16-Bit
Not Available

Abstract: No abstract text available
Text: No file text available


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PDF LLM21 LLM31
2006 - rgb led matrix circuits 32X16

Abstract: 4 input video multiplexer ISL59534 ISL59534IKEZ ISL59535 V356
Text: on the SDI (serial data input) pin is shifted into a 16- bit shift register on the rising edge of the , .) The LSB ( bit 0) is loaded first and the MSB ( bit 15) is loaded last (see the Serial Timing Diagram). , , delayed by 15.5 SCLKs (an input bit is latched on the rising edge of SLCK, and is output on SDO on the , is configured by a series of 16- bit serial control words. The three MSBs (B15-13) of each serial word , - O3 O2 O1 B0 O0 I4:I0 form the 5- bit word indicating the input channel (0 to 31


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PDF ISL59534 FN6249 32x16 ISL59534 300MHz rgb led matrix circuits 32X16 4 input video multiplexer ISL59534IKEZ ISL59535 V356
2007 - LLM21

Abstract: No abstract text available
Text: No file text available


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PDF LLM21 LLM31 LLM21
2001 - maxim analog design guide 12 3RD

Abstract: MAX4313 MAX4412 MAX4413 MAX4414 MAX4415 MAX4416
Text: No file text available


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PDF 32x16 MAX4452/MAX4352) MAX4412/MAX4413 500MHz 30MHz SC70/SOT23 MAX4412 MAX4413 maxim analog design guide 12 3RD MAX4313 MAX4412 MAX4413 MAX4414 MAX4415 MAX4416
2001 - z405

Abstract: MAX4436 MAX435/MAX436 350MHzAVCL 32x1675 MAX4416 MAX4415 MAX4414 MAX4413 MAX4412
Text: No file text available


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PDF 32x16 144TQFP MAX4452/MAX4352) MAX4412/MAX4413 MAX456 MAX458 100MHz MAX459 90MHz z405 MAX4436 MAX435/MAX436 350MHzAVCL 32x1675 MAX4416 MAX4415 MAX4414 MAX4413 MAX4412
Z8691

Abstract: No abstract text available
Text: P3 8KPROM UART CPU 256 RAM PO P1 P2 P3 DSP 512 RAM|4K ROM 16- BIT MAC DATA RAM I/O M ULT DIV UART , Z86 E2U 8KO TP Z86C21 = 8 K R 0 M C M O S; 1 2 ,16 M Hz Z89C00 16- Bit Digital Signal Processor , Option Low-EMI Option 16- Bit Multiply/Accumulate 75 ns Two Data RAMs (256 Words Each) 4K Word ROM 64Kx16 Ext. ROM 16- Bit I/O Port 74 Instructions Most Single Cycle Two Conditional Branch Inputs, Two User , Full-Duplex U ART Two Standby Modes (STOP and H ALT) Three 16- Bit Counter/Timers P ackage 40-Pin DIP


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PDF 16-BIT Z86C93 Z86C91/Z8691 Z86E21/Z86C21 Z86C21 Z89C00 Z86C91 Z8691 16x16 Z8691
1996 - Z86E61

Abstract: Z8 ROMless Z86C21 Z86C61 Z86C91 Z86C93 Z86E21 EMULATOR UART 40-pin DIP
Text: (STOP and HALT) t 2x8- Bit Counter/Timers t t t t 40-Pin DIP 44-Pin PLCC 44-Pin QFP 40 , HALT) t 3x16- Bit Counter/Timers ZiLOG


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PDF Z86C21/Z86E21 Z86C61/Z86E61 Z86C93 Z86C91 Z86C21 Z86E21 Z86C61 Z86E61 256-Byte Z86C0000ZUSP064 Z86E61 Z8 ROMless Z86C21 Z86C61 Z86C91 Z86C93 Z86E21 EMULATOR UART 40-pin DIP
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