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32-bit, datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
32-Bit Logic Families in LFBGA Packages 32-Bit Logic Families in LFBGA Packages ECAD Model NXP Semiconductors ANLFBGA 32-Bit Logic Families in Low-profile Fine-pitch Ball Grid Array (LFBGA) Packages Original PDF

32-bit, Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
68b50

Abstract: 68b09 68B21 Motorola 68A09 motorola 6809 8 bit Instruction set 68hc811e2 6802 processor motorola 68A21 68hc000-10 68A50
Text: Integrated Circuits 8- BIT MICROPROCESSORS & MICROCONTROLLERS 32- BIT CONTROLLERS AND PERIPHERALS MIL-STD-883C 8- Bit Microprocessors, 32- Bit Controllers & Microcontrollers 883C Package Type and Lead Finish Device 883C Description Pins DIL FP LCCC CLCC 6800 /B 8- Bit Microprocessor 40 QA 6802 /B 8- Bit Microprocessor with Clock and Optional RAM 40 QA 6809 /B 8- Bit Microprocessor with Clock 40 QA 68A09 IB 1,5 MHz 8- Bit Microprocessor with Clock 40 QA 68B09 IB 2.0 MHz 8- Bit Microprocessor with Clock 40


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PDF 32-BIT MIL-STD-883C 68A09 68B09 68A21 68B21 68b50 Motorola 68A09 motorola 6809 8 bit Instruction set 68hc811e2 6802 processor motorola 68hc000-10 68A50
1998 - register file

Abstract: ADSP-2100 ADSP-21000 ADSP-21160 RND32
Text: '$7$$&&(66(6 Figure 5-0. Table 5-0. Listing 5-0. 2YHUYLHZ The ADSP-21160s 64- bit data width , the typical data width supported by the ADSP-21160 architecture is 32-bits, the 64- bit DM and PM , of long word accesses. Mode selectable support of 40- bit extended precision floating-point , -21160s internal SRAM memory accommodates the following word types: 48- bit instructions 40- bit extended precision floating-point data 32- bit floating-point data 16- bit short word data The ADSP


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PDF ADSP-21160s 64-bit ADSP-21160 32-bits, 40-bit register file ADSP-2100 ADSP-21000 RND32
1996 - 7 bit hamming code

Abstract: FCT245 IDT39C60 32-bit microprocessor architecture IDT49C460 IDT49C465 IDT49C466 IDT74FCT244
Text: PROTECTING YOUR DATA WITH THE IDT49C465 32- BIT Flow-thruEDCTM UNIT APPLICATION NOTE AN-64 PROTECTING YOUR DATA WITH THE IDT49C465 32- BIT Flow-thruEDCTM UNIT APPLICATION NOTE AN , Error-Free Memories With the advent of high-performance 32- bit RISC and CISC microprocessors, general , Controller /WR Check Bit Memory Main Memory PROTECTING YOUR DATA WITH THE IDT49C465 32- BIT Flow-thruEDCTM UNIT APPLICATION NOTE AN-64 PROTECTING YOUR DATA WITH THE IDT49C465 32- BIT Flow-thruEDCTM


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PDF IDT49C465 32-BIT AN-64 64-bit 7 bit hamming code FCT245 IDT39C60 32-bit microprocessor architecture IDT49C460 IDT49C465 IDT49C466 IDT74FCT244
KU80386EXTC33

Abstract: TN80C188EB20 FA80386EXTC33 TS80C188EB-20 KU80386EXTC25 FA80386EXTB25 A80486DX4WB100 TS80C188EC20 386SX TA80C186XL20
Text: , 16- Bit , 80C186XL Microprocessor, 5V .68-PLCC 25MHz, 16- Bit , 80C186XL Microprocessor, 5V .68-PLCC 12MHz, 16- Bit , 80C188XL Microprocessor, 5V .68-PLCC 20MHz, 16- Bit , 80C188XL Microprocessor, 5V .68-PLCC 20MHz, 16- Bit , 80C186XL Microprocessor, 5V .68-LCC 25MHz, 16- Bit , 80C186XL Microprocessor, 5V .68-LCC 12MHz, 16- Bit , 80C186XL Microprocessor, 5V .80-MQFP 20MHz, 16- Bit


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PDF N80C186XL20 803140-ND N80C186XL25 803256-ND N80C188XL12 N80C188XL20 R80C186XL20 R80C186XL25 S80C186XL12 803698-ND KU80386EXTC33 TN80C188EB20 FA80386EXTC33 TS80C188EB-20 KU80386EXTC25 FA80386EXTB25 A80486DX4WB100 TS80C188EC20 386SX TA80C186XL20
2002 - MB89135L

Abstract: MB89P637 MB89P131 MB89P133A FR30 MB89121 MB89123A MB89125A MB89131 MB89133A
Text: Entire Site Site map Support Microcontrollers F2MC 8 Bit Series 16 Bit Series FR 32- Bit , 3 4 128 (32) 8 Power- Pin Saving Count Modes 2 x 8 bit 11 or 11 1 x 16 bit 3 2 X 8 bit 3 or on-chip STOP 256 11 1 x 16 bit Remote , 16 bit 12 bit CLOCK MB89146 130/A 3 MB89144 120/A 24 768 Programmable , Features 36 1x8 bit 1x8 bit Yes 4x8 bit (A-Version with SLEEP on-chip STOP


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PDF 32-Bit MB89xxx MB89121 MB89123A MB89125A MB89131 MB89P131 MB89P985 MB89997 MB90Pxxx MB89135L MB89P637 MB89P131 MB89P133A FR30 MB89121 MB89123A MB89125A MB89131 MB89133A
2013 - IVOR33

Abstract: No abstract text available
Text: Freescale Semiconductor Application Note Document Number: AN4648 Rev. 1, 3/2013 VLE 16- bit and 32- bit Instruction Length Decode Algorithm by: Pavel Bohacik Contents 1 Introduction , MPC56xx 32- bit microcontroller family built on Power Architecture ® technology provides a mechanism by , .2 4 Book E or VLE instruction decoding.2 5 Decoding 16- bit or 32- bit , use both variable length encoding (VLE) 16- bit and 32- bit instructions and Book E 32- bit instructions


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PDF AN4648 16-bit 32-bit MPC56xx IVOR33
82358

Abstract: No abstract text available
Text: .1-301 Figure 3-1 386 CPU Host Master to 16- Bit IS A /H o s t/E IS A /H o s t Slave , Cycles . 1-309 Figure 3-3 Host Master to 32- Bit EISA Memory I/O Slave Standard R ead/W rite Cycles . 1-310 Figure 3-4 Host Master to 32- Bit EISA Memory Slave Two Standard Read C y c le s . 1-311 Figure 3-5 Host M aster to 32- Bit EISA Memory Slave Locked Read Cycle . 1-312 Figure 3-6 Host Master to 16- Bit EISA Memory Slave


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PDF 16-Bit 32-Bit 82358
2005 - PPC970

Abstract: PowerPC 970 register set ppc970 data PowerPC 970 64-BIT 970fx Introduction to 64-bit computing and PowerPC 970xx Processors
Text: Application Note An Introduction to 64- bit Computing and PowerPC 970xx Processors Introduction 64- bit computing is well established on IBM's zSeries and POWER-based pSeries systems. However, with the introduction of the PowerPC 970xx processor family, 64- bit computing is now available on the desktop, on value priced servers, and to the embedded community. This paper will give an overview of 64- bit computing and discuss the advantages of a 64- bit operating system environment. Designed for 32- bit and 64- bit


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PDF 64-bit 970xx 970xx 64-bit 32-bit PPC970 PowerPC 970 register set ppc970 data PowerPC 970 970fx Introduction to 64-bit computing and PowerPC 970xx Processors
Hitachi DSAUTAZ005

Abstract: No abstract text available
Text: (channel) Supply Voltage Address Space 32- bit Timer 16- bit Timer 8- bit Timer PWM Timer Watch Dog , -80C 4.5 - 5.5 4k no no 63 5 1 1 1 8x 10 bit 1 2 8x 10 bit 5 1 2 8x 10 bit 1 1 1 8x 10 bit 1 1 1 8x 10 bit 1 1 1 8x 10 bit 1 3 8x 10 bit 1 3 8x 10 bit 5 1 2 8x 10 bit 1 1 2 8x 10 bit 1 1 1 8x 10 bit 1 1 2 8x 10 bit no no 16 25,5 no 2x 8 bit 2x 8 bit no 4 16 27,7 no no , no 16 25,5 no 2x 8 bit 2x 8 bit 2x 8 bit no 4 16 36,7 no 4 16 36,7 no no 16


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PDF 32-bit 16-bit H8/300H H8/3037 H8/3008 H8/3061 H8/3036 Hitachi DSAUTAZ005
2001 - AN601

Abstract: DIV32 DS80C390 IEEE754
Text: Application Note 601 Accelerating 16/32- Bit Math Operations with the DS80C390 www.maxim-ic.com OVERVIEW Performance advances in the 8051 microcontroller market have increasingly led users to consider 8- bit devices in applications that once required processing power only available from 16- bit devices. Some of , involving 16- bit data. The DS80C390 addresses this need on two levels. First, the DS80C390 uses the , to applications doing intensive 16- bit math is the inclusion of dedicated hardware for 16/32- bit


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PDF 16/32-Bit DS80C390 16-bit DS80C390 40Mov 40Mhz AN601 DIV32 IEEE754
x86 addressing mode

Abstract: 32-bit microprocessor architecture intel x86 processor architecture x86 processor architecture intel x86-64 gprs abstract interrupts of x86 microprocessor how to define amd athlon 64 app abstract
Text: The need for 64- bit computing is driven by applications that address large amounts of data and memory , tools. Although this increased demand on the high-end along with technical advances is making 64- bit a reality, it is anticipated that the industry as a whole will not fully embrace the 64- bit world entirely for many more years. Existing 32- bit environments and applications will continue to serve a majority , to transition to 64- bit computing, yet maintain their existing knowledge base and investment in the


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PDF X86-64TM 64-bit x86-64 x86 addressing mode 32-bit microprocessor architecture intel x86 processor architecture x86 processor architecture intel x86-64 gprs abstract interrupts of x86 microprocessor how to define amd athlon 64 app abstract
2000 - Map 6808

Abstract: MAP 6810 motorola 6810 memory C004 MPC555 MPC556 QADC64 INSTRUCTION SET motorola 6800 6058 S 6C46
Text: 32 S MSR S MSR Machine State Register. See Table 3-12 for bit descriptions SPR 1 U XER Integer Exception Register. See Table 3-10 for bit descriptions 32 U SPR 8 U LR Link Register. See 3.7.6 Link Register (LR) for bit descriptions. 32 U SPR 9 U CTR Count Register. See 3.7.7 Count Register (CTR) for bit descriptions. 32 U SPR , Service Register (DSISR) for bit descriptions. 32 U SPR 19 S DAR Data Address Register


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PDF MPC555 MPC556 QADC64 MPC556 Map 6808 MAP 6810 motorola 6810 memory C004 QADC64 INSTRUCTION SET motorola 6800 6058 S 6C46
2007 - TIM12

Abstract: TS timer ARM926EJ-S C6000 TMS320C6000 PSC34 CLKSRC34 TINT34
Text: TMS320DM646x DMSoC 64- Bit Timer User's Guide Literature Number: SPRUER5 December 2007 2 , . 8 64- Bit Timer Mode Block Diagram . 10 Dual 32- Bit Timers Chained Mode Block Diagram . 12 Dual 32- Bit Timers Chained Mode Example . 12 Dual 32- Bit Timers Unchained Mode Block Diagram


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PDF TMS320DM646x 64-Bit TIM12 TS timer ARM926EJ-S C6000 TMS320C6000 PSC34 CLKSRC34 TINT34
2007 - SPRUE26

Abstract: ARM926EJ-S C6000 TIM12 TDDR34 64-Bit Microcontrollers PSC34
Text: TMS320DM644x DMSoC 64- Bit Timer User's Guide Literature Number: SPRUE26 March 2007 2 , . 9 64- Bit Timer Mode Block Diagram . 10 Dual 32- Bit Timers Chained Mode Block Diagram . 12 Dual 32- Bit Timers Chained Mode Example . 12 Dual 32- Bit Timers Unchained Mode Block Diagram


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PDF TMS320DM644x 64-Bit SPRUE26 SPRUE26 ARM926EJ-S C6000 TIM12 TDDR34 64-Bit Microcontrollers PSC34
2010 - MX25L25635E

Abstract: MX25L256 mx25l25635 mxic MX25L25 MXIC serial Flash macronix an053
Text: .2 . 2. Two Address Modes: 24- bit Address Mode and 32- bit Adress Mode.3 Figure 1. 32- bit Address Protocol , Flash Application in System Reset 1. Introduction MX25L25635E provides 24- bit and 32- bit address modes by command definition. Once the device enters 32- bit address mode by B7 command, command E9 or power-off cycle is required to exit the 32- bit address mode. After the flash switches to 32- bit address


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PDF MX25L25635E 256Mb MX25L25635E 24-bit 32-bit MX25L256 mx25l25635 mxic MX25L25 MXIC serial Flash macronix an053
1998 - MB89121

Abstract: MB89123A MB89125A MB89131 MB89133A MB89135A MB89144 MB89145 MB89146 MB89XXX
Text: Timer Counter UART Ser. I/O A/D Conv. LCD Contr. 36 - - 2 x 8 bit or 1 x 16 - 1 x 8 bit - - (A-Version with on-chip Remote Contr.) 4.2 (32) 36 - - 2 x 8 bit or 1 x 16 - 1 x 8 bit 4 x 8 bit - (A-Version with on-chip Remote Contr.) 8 (32) 55 3 11 11 3 11 11 2 1 x 8 bit - 2 x 8 bit or 1 x 16 - 1 x 8 bit 8 x10 bit - VFD Driver 4.2 (32) 43 12 - - 2 x 8 bit or 1 x 16 - 1 x


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PDF MB89xxx 120/A MB89951 MB89953 MB89965 MB89997 MB89121 MB89123A MB89125A MB89131 MB89133A MB89135A MB89144 MB89145 MB89146 MB89XXX
4194304-WORD

Abstract: dram 88 pin dram module
Text: . 57 [168-pin Buffered DIMM] HB56UW3273 Series 33554432-word x 72- bit DRAM Module. 59 HB56UW3272 Series 33554432-word x 72- bit DRAM Module. 88 HB56UW1673E Series 16777216-word x 72- bit DRAM Module. 104 HB56UW1672E Series 16777216-word x 72- bit DRAM Module. 117 HB56AW1672E Series 16777216-word x 72- bit DRAM Module. 130 HB56UW873E Series 8388608-word x 72- bit DRAM Module


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Not Available

Abstract: No abstract text available
Text: -50/-60/-70 322035S/GS -50/-60/-70 1 M x 32- Bit Dynamic RAM 5 V .41 1 M x 32- Bit Dynamic RAM 5 V .51 1 M x 32- Bit Dynamic RAM 5 V EDO. 61 2 2 2 2 2 M M M M M x 32- Bit x 32- Bit x 32- Bit x 32- Bit x 32- Bit Dynamic Dynamic Dynamic Dynamic Dynamic RAM RAM RAM RAM RAM 5 5 5 5 5 V V , (L) -50/-60 HYM 324000GD -50/-60 HYM 328000GD -50/-60 HYM 328020GD -50/-60 4 M x 32- Bit Dynamic


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PDF B116-H6557-G3-X-7600,
Not Available

Abstract: No abstract text available
Text: Family TMS320F28020 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F280200 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F28021 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F28022 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F280220 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F28023 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F280230 Piccolo Microcontroller C2000™ 32- bit Real-time MCUs TMS320F28026 Piccolo


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PDF TMS320F28069 TMDXCNCD28069ISO TMDXCNCD28069ISO C2000 TMS320F28062 C2000â 32-bit TMS320F28063
1994 - ds5 2502

Abstract: DS5 2502 MARK mc68150 motorola PD23-PD16
Text: MC68150/D DATA SHEET NOT RECOMMENDED FOR NEW DESIGNS 32Bit to 32/16/8Bit 32- Bit to 32/16/8- Bit , allow the 32- bit MC68/LC/EC040 bus, or other 16- to 32- bit processors, to communicate bi-directionally with 32-, 16-, or 8- bit peripherals and memories. It dynamically recognizes the size of the selected , , respectively. Typical operations which call for bus sizing are booting up instructions from 8- bit ROM (EPROM, EEPROM, etc.) and communicating with 8- bit SRAM's for scratch pad memory storage during interrupt


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PDF MC68150/D 32Bit 32/16/8Bit 32-Bit 32/16/8-Bit MC68150 MC68/LC/EC040 68/EC040 ds5 2502 DS5 2502 MARK mc68150 motorola PD23-PD16
2004 - 32-Bit Microcontrollers

Abstract: Microcontrollers ARM7 32 bit processor semico AT91SAM7S "32-Bit Microcontrollers" CMOS Single Chip 32-Bit Microcontrollers
Text: Facilitating the Migration from 8- bit to 32- bit Microcontrollers By Jacko Wilbrink, ARM Product , in order to reduce the total effort required. This paper describes how Atmel's Smart ARM 32- bit RISC , ) 441-0311 · FAX (408) 487-2600 · Web Site: http://www.atmel.com FACILITATING THE MIGRATION FROM 8- BIT TO 32- BIT MICROCONTROLLERS Table of Contents The move from 8- bit to 32- bit microcontrollers is in , . 8 2 3323A-ATARM-10/04 FACILITATING THE MIGRATION FROM 8- BIT TO 32- BIT MICROCONTROLLERS


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PDF 32-bit 323A-ATARM-10/04 32-Bit Microcontrollers Microcontrollers ARM7 32 bit processor semico AT91SAM7S "32-Bit Microcontrollers" CMOS Single Chip 32-Bit Microcontrollers
2004 - 4-bit even parity checker circuit diagram

Abstract: BAR53 4-bit parity/generator checker design S 1854 4-bit parity checker BUS BAR specification BAR13 BAR43 PCI-MT32-XP-N1 PCI-MT32-XP-N2
Text: PCI Core January 2004 IP Data Sheet Features Available as 32/64- Bit PCI Bus and 32/64- Bit Local Bus Available in Master/Target and Target Versions PCI SIG Local Bus Specification, Revision 2.2 Compliant 64- Bit Addressing Support Capabilities List Pointer Support Parity , stopn devseln idsel reqn gntn Error Reporting ad[63:32] 64- Bit Extension Interrupts , _64bit_transn lm_hdata_xfern lm_ldata_xfern lm_cben_in[7:4] 64- Bit Extension lm_burst_length[11:0] lm_data_xfern


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PDF 32/64-Bit 32/64-Bit 64-Bit 66MHz 32-bit 64-bit) 32-Bit PCI-T32-5X-N2 LC5768MV-5F484C 4-bit even parity checker circuit diagram BAR53 4-bit parity/generator checker design S 1854 4-bit parity checker BUS BAR specification BAR13 BAR43 PCI-MT32-XP-N1 PCI-MT32-XP-N2
1995 - solar wind hybrid controller

Abstract: TMDXDOCKH52C1 32-BIT H52C1 C2000TM microcontroller docking station united states 2011 CONTROLSUITE F28M35E20C
Text: Devices (30) Name Concerto Microcontroller Product Family C2000TM 32- bit Real-time MCUs http , Microcontroller Concerto Microcontroller Concerto Microcontroller C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs C2000TM 32- bit Real-time MCUs


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PDF H52C1 TMDXDOCKH52C1 TMDXDOCKH52C1 C2000 com/tool/tmdxdockh52c1 solar wind hybrid controller 32-BIT C2000TM microcontroller docking station united states 2011 CONTROLSUITE F28M35E20C
1998 - 32Kx16bit

Abstract: 00000x7 00000x4
Text: into the bit bucket. An ADSP-21160 2-Mbit block of memory that contains 48- bit instruction words can store a maximum of 42.67K words, and a 2-Mbit block that contains 32- bit data words can store a maximum , data storage memory is also provided through the external port. 32- bit memory words are used for single-precision IEEE floating-point data. 48- bit words contain either instructions or 40- bit extended-precision floating-point data. In addition, the ADSP-21160 supports a 16- bit short word format which can be used for


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PDF ADSP-21160 ADSP-21160, 48-bit 32-bit 32-bit 16-bit ADSP-21160s 32Kx16bit 00000x7 00000x4
1994 - 32-bit microprocessor architecture

Abstract: MIPS 32-bit bus architecture "64-Bit Microprocessor" 64 bit microprocessor 79R4600 IDT79R4600 R3000 64-BIT
Text: 32- AND 64- BIT OPERATION OF THE IDT79R4600TM TECHNICAL NOTE TN-21 Integrated Device Technology, Inc. By Phil Bourekas operation, the R4600 offers two virtual addressing modes: - 32- bit virtual addressing mode. In this case, all virtual addresses are considered to be 32- bit values. This , or all "1" are considered invalid addresses and will cause an address error. - 32- bit virtual , status register. When operating in 32- bit virtual addressing mode: - 64- bit operations (the MIPS


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PDF 64-BIT IDT79R4600TM TN-21 R4600 32-bit 32-bits 64bit 32-bit microprocessor architecture MIPS 32-bit bus architecture "64-Bit Microprocessor" 64 bit microprocessor 79R4600 IDT79R4600 R3000
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