The Datasheet Archive

Top Results (4)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
ADSP-2191MKCAZ-160 ADSP-2191MKCAZ-160 ECAD Model Analog Devices Inc 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM
ADSP-2191MBSTZ-140 ADSP-2191MBSTZ-140 ECAD Model Analog Devices Inc 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM
ADSP-2191MBCAZ-140 ADSP-2191MBCAZ-140 ECAD Model Analog Devices Inc 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM
ADSP-2196MKSTZ-160 ADSP-2196MKSTZ-160 ECAD Model Analog Devices Inc 16-bit Fixed-Point DSP, 160 MIPS, 40 Kbytes RAM
SF Impression Pixel

Search Stock

Balluff Inc
BES M30MI-PSC10B-S04K BALLUFF Inductive Barrel-Style Proximity Sensor, M30 x 1.5, 10 mm Detection, PNP Output, 12 30 V dc, IP68, EA
BES M30MI-PSC10B-S04K ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
RS BES M30MI-PSC10B-S04K Bulk 20 1 $58.952 $56.552 $56.552 $56.552 $56.552 More Info
Balluff Inc
BES M30MI-PSC15B-S04G BALLUFF Inductive Barrel-Style Proximity Sensor, M30 x 1.5, 15 mm Detection, PNP Output, 10 30 V dc, IP67, EA
BES M30MI-PSC15B-S04G ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
RS BES M30MI-PSC15B-S04G Bulk 27 1 $63.101 $60.528 $60.528 $60.528 $60.528 More Info
TME Electronic Components BES M30MI-PSC15B-S04G 18 1 $38.85 $33.84 $33.84 $33.84 $33.84 More Info
Balluff Inc
BES M30MI-PSC15B-S04K BALLUFF Inductive Barrel-Style Proximity Sensor, M30 x 1.5, 15 mm Detection, PNP Output, 10 30 V dc, IP67, EA
BES M30MI-PSC15B-S04K ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
RS BES M30MI-PSC15B-S04K Bulk 88 1 $63.101 $63.101 $63.101 $63.101 $63.101 More Info
Balluff Inc
BES M30MI-PSC10B-S04G Sensor: inductive; OUT: PNP / NO; 0÷10mm; 12÷30VDC; M30; IP67; 200mA
BES M30MI-PSC10B-S04G ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
TME Electronic Components BES M30MI-PSC10B-S04G 11 1 $35.02 $30.5 $30.5 $30.5 $30.5 More Info

30-MIPS Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
C5440

Abstract: TPS543xx TMS320C5510 DSK tms320C5402 C5000 rj11 plug to 3.5mm TPS70758 C5402 BGA 144 C55X
Text: : The world's lowest mW/ MIPS DSPs TI C64xTM DSP Core: The world's highest performance DSPs TI C28xTM DSP Core: The world's first control optimized DSPs · Up to 400 extended precision MIPs · , / MIPs for longest battery life · Best code density · Software compatible with C54xTM DSP · , DSP, 1 core ) Lower C5000 MIPS Higher C5000 Personal DSP Desirable Power Efficiency Critical C5000 Personal DSP C5000 Catalog DSP Portfolio MULTI-CORE SINGLE CORE Features MIPS


Original
PDF TMS320C5000 C5000TM C5000 C2000TM C6000TM C55xTM C64xTM C28xTM C5440 TPS543xx TMS320C5510 DSK tms320C5402 rj11 plug to 3.5mm TPS70758 C5402 BGA 144 C55X
hifn 7751

Abstract: MPPC 001 TC59S6408BFT-10 7811-PB3 93C46 R4300 R4310 "L2TP" hifn lzs hifn mppc
Text: Memory Maps . 37 5.1 5.2 MIPS , .97 MIPS Interrupt MIPS Interrupt , .102 MIPS SDRAM1 Address Register .103 MIPS SDRAM2 Address Register .104 MIPS Group 1 Address Register .105 MIPS Group 1 Address Register .106 MIPS PCI1 Address Register


Original
PDF DS-0018-01 hifn 7751 MPPC 001 TC59S6408BFT-10 7811-PB3 93C46 R4300 R4310 "L2TP" hifn lzs hifn mppc
2000 - TMS320C55X

Abstract: C55X HR C5000 BIOS ic2 GSM PIC 4266fa 41AO C5000 C5409 C5410
Text: MIPS 1/ 5 C54x DSP TMS320C55x DSP TMS320C55x DSP TITMS320C55x DSP CORE 400MHz0.05mW/ MIPS 3×16 C55x DSPC54 DSP 2×16 , MIPS 30-160 140-800 5X MMACs 30-160 140-800 5X MIPS1/6 0.05mW/MIPS0.9v 0.08mW/MIPS1.2/1.5v 30% mW/ MIPS 1 1 2 0 2 2 4 , DSP 30% MIPS C55x 300MHz vs C54x 120MHz@1.8V -us C55x


Original
PDF TMS320C55x 05mW/MIPS0 140800MIPS TITMS320C55x 400MHz0 05mW/MIPS DSPC54 40-bit C55X HR C5000 BIOS ic2 GSM PIC 4266fa 41AO C5000 C5409 C5410
1997 - TC59S6408BFT-10

Abstract: 7811 hifn 7751 7811-PB3 93C46 R4300 R4310 mppc 01 m 7811 "L2TP"
Text: 30 5.2 MIPS Memory Map . , . 125 12.3 MIPS Interface Timing . , . 28 Figure 14. Recommended terminations if MIPS processor is not used . 29 Figure 15 , MIPS memory space by the 7811. 33 Figure 18. EEPROM memory map , . 88 Figure 75. MIPS Interrupt register


Original
PDF DS-0018-00 TC59S6408BFT-10 7811 hifn 7751 7811-PB3 93C46 R4300 R4310 mppc 01 m 7811 "L2TP"
2000 - MIPS64 20Kc

Abstract: MIPS Technologies MIPS64 TSMC 0.18um IEEE754 MIPS32 R20K prefetch "data history table"
Text: floating-point performance of 1500 MIPS and 3.0 GFLOPS with the ability to scale to over 1 GHz in future process technologies. · The MIPS -3DTM enhanced floating-point unit achieves 3D geometry processing performance of 37 , process. 64-bit processor IP from MIPS Technologies ­ Your license to innovateTM P R O D , Integer Execution Unit Instruction Dispatch Unit MIPS -3DTM SIMD FPU Pipe A MIPS64 20Kc Core: High-Performance Standard for SOC Cores Registers Registers is capable of 1500 MIPS and 3 GFLOPS. It


Original
PDF MIPS64 64-bit 20KcTM R20KTM MIPS32, MIPS64, 0600/2K/Rev0 MIPS64 20Kc MIPS Technologies TSMC 0.18um IEEE754 MIPS32 R20K prefetch "data history table"
Seminar

Abstract: C64x C64X CPU description TMS320C55X C62xTM c6000benchmarks C6000 asm TMS320C55xTM viterbi convolution Natural Microsystems
Text: Efficiency: C55xTM ! ! ! 0.05 mW / MIPS Cut power consumption of C54xTM by 85% 5X performance of , Slashes power consumption to 0.05 mW per MIPS Performs up to 800 MIPS Software compatible with C54x DSPs TMS320C55xTM DSP Core ! ! ! Slashes power consumption to 0.05 mW per MIPS Performs up to 800 MIPS Software compatible with C54x DSPs TMS320C64xTM DSP Core ! ! ! Speeds up to 1.1 GigaHertz (GHz) Performs nearly 9000 MIPS Software compatible with C62x DSPs Customer Testimonials "


Original
PDF TMS320C64xTM TMS320C55xTM C64xTM C62xTM 000rax Seminar C64x C64X CPU description TMS320C55X C62xTM c6000benchmarks C6000 asm viterbi convolution Natural Microsystems
2009 - V850E2

Abstract: V850ES TFT LCD NEC 6,4" green hills compiler NEC 9001
Text: reliability and better features. Performance · Low power consumption · High speed ( MIPS ) Reliability , High-performance from a proprietary CPUs ­ 8-bit microcontrollers: up to 2 MIPS ­ 16-bit microcontrollers: up to 13 MIPS at 20 MHz ­ 32-bit microcontrollers - Up to 96 MIPS with the V850ESTM core - Up to 400 MIPS with the V850E2TM core 1.8 to 5.5V operation over the full industrial temperature range (extended , 32-bit V850ES/Jx3-L MCUs · High CPU performance (45­64 MIPS at clock speed of 32 MHz) · High


Original
PDF U18254EE1V1PFU1 V850E2 V850ES TFT LCD NEC 6,4" green hills compiler NEC 9001
1997 - "64-Bit Microcontrollers"

Abstract: 64-Bit Microcontrollers R36100 IDTR36100 GSM Base Station lucent bts-2000
Text: Technology, Inc. (IDT), the designer and manufacturer of the broadest line of MIPS ® RISC microprocessors, today announced that the IDT R36100TM MIPS RISC microcontroller powers Lucent Technologies' Compact BTS-2000/2C Base Transceiver Station. IDT's R36100 offers a unique combination of MIPS processing power and , ) World Conference in Cannes, France. "With IDT's R36100, we can incorporate more than 30 MIPS processing , 's powerful MIPS RISC processors are playing, not only in the data communications market with extensive use in


Original
PDF R36100TM 1997--Integrated BTS-2000/2C R36100 "64-Bit Microcontrollers" 64-Bit Microcontrollers IDTR36100 GSM Base Station lucent bts-2000
1996 - vhdl code for 8 bit barrel shifter

Abstract: 16 bit single cycle mips vhdl MOTOROLA DSP56300 architecture pga 132 packaging architectural block diagram of motorola 563xx vhdl code for 16 bit barrel shifter TQFP112 563xx 32 bit single cycle mips vhdl 32 bit barrel shifter vhdl
Text: Division DSP56300 Architecture MIPS · First programmable DSP architecture with true single clock cycle instruction · Double the MIPS without increasing clock speed · Most fundamental DSP architectural , MIPS /80 MHz with migration to 100 MIPS and beyond 7 Digital Signal Processing Division Comparison of Available DSP MIPS MIPS 80 5 volts 3 volts 70 60 50 40 30 20 10 0 Motorola , 25-40% more functionality per MIPs · Effectively increases relative MIPS differential 80 MIPS x


Original
PDF 24-bit DSP56300 563xx 56xxx PQFP/132 56xxx 6001A vhdl code for 8 bit barrel shifter 16 bit single cycle mips vhdl MOTOROLA DSP56300 architecture pga 132 packaging architectural block diagram of motorola 563xx vhdl code for 16 bit barrel shifter TQFP112 563xx 32 bit single cycle mips vhdl 32 bit barrel shifter vhdl
2002 - circuit diagram "dolby digital"

Abstract: fci dh 22 TC9446F AD10 AD11 AD12 AD14 IEC958 tc944
Text: upto 6th times for DSP clock · Instruction cycle: 20 ns/1 instruction at 50 MIPS operation · , of the DLL clock, and processing speed can correspond a maximum of 75 MIPS . The clock outputted from , Clock 12.288 MHz (48 kHz*256) 73.728 MHz (36 MIPS operation) 49.152 MHz (24 MIPS operation) 38.864 MHz (18 MIPS operation) 18.432 MHz (48 kHz*384) 110.592 MHz (55 MIPS operation) 73.728 MHz (36 MIPS operation) 55.296 MHz (27 MIPS operation) 24.576 MHz (48 kHz*512) 147.456 MHz


Original
PDF TC9446F TC9446F circuit diagram "dolby digital" fci dh 22 AD10 AD11 AD12 AD14 IEC958 tc944
2005 - Not Available

Abstract: No abstract text available
Text: : 20 ns/1 instruction at 50 MIPS operation DSP Processor: 24 bit × 24 bit + 51 bit multiplier and adder , operation is a half divided clock of the DLL clock, and processing speed can correspond a maximum of 75 MIPS , (asynchronous) 36.864 MHz (48 kHz*768) 6th Times Clock 73.728 MHz (36 MIPS operation) 110.592 MHz (55 MIPS operation) 147.456 MHz (73 MIPS operation) to 150 MHz (75 MIPS operation) Not available Not available Not available 4th Times Clock 49.152 MHz (24 MIPS operation) 73.728 MHz (36 MIPS operation) 98.304 MHz (49 MIPS


Original
PDF TC9446FG TC9446FG AD0-AD16 P-QFP100-1420-0
2002 - Not Available

Abstract: No abstract text available
Text: : 20 ns/1 instruction at 50 MIPS operation DSP Processor: 24 bit × 24 bit + 51 bit multiplier and adder , divided clock of the DLL clock, and processing speed can correspond a maximum of 75 MIPS . The clock , and DLL Clock 6th Times Clock 73.728 MHz (36 MIPS operation) 110.592 MHz (55 MIPS operation) 147.456 MHz (73 MIPS operation) to 150 MHz (75 MIPS operation) Not available Not available Not available 4th Times Clock 49.152 MHz (24 MIPS operation) 73.728 MHz (36 MIPS operation) 98.304 MHz (49 MIPS operation


Original
PDF TC9446F TC9446F
2012 - MIPSTZ

Abstract: No abstract text available
Text: Inductance(uH) 5 4 3 2 1 0 0 200 400 600 800 1000 1200 DC bias current(mA) MIPS TZ2520D4R7 MIPS TZ2520D2R2 MIPS TZ2520D1R5 MIPS TZ2520D1R0 MIPS TZ2520D0R5 7 6 Frequency vs. Indctance MIPS TZ2520D4R7 MIPS TZ2520D2R2 MIPS TZ2520D1R5 MIPS TZ2520D1R0 MIPS TZ2520D0R5 Inductance(uH) 5 4 3 2 1 0 0.1 1 10


Original
PDF CD-TCE073-201204 MIPSTZ2520D TZ2520D4R7 TZ2520D2R2 TZ2520D1R5 TZ2520D1R0 TZ2520D0R5 MIPSTZ
2001 - VR4122

Abstract: VR4120 VR4121 VR4100 VRC4173 U14327EJ1V0UM00 U14327E
Text: VR4122 VR family 64-bit MIPS RISC Microprocessor Product Letter Description The 64 , information systems, webphones, digital cameras and other embedded systems. It uses the MIPS ® RISC architecture developed by MIPS Technologies and offers excellent power consumption and performance in a highly integrated, low-cost system on a chip. Features · · · · · · · VR4120 CPU CORE MIPS I, II, III and MIPS 16 instruction set Performance up to 216 Mips at 180 MHz Fast single cycle MAC instruction


Original
PDF VR4122 64-bit PD30122) VR4120 VR4122 VR4121 VR4100 VRC4173 U14327EJ1V0UM00 U14327E
LF2407

Abstract: program of GSM with ccs c compiler C28x C6711 DSP kit C5416 lc2402 TMS320TM 3G equipments dsl 500b st er C548
Text: Core: The world's first control optimized DSPs · Up to 400 extended precision MIPs · Best C/C , 's lowest mW/ MIPS DSPs · As low as 0.05mW/ MIPs for longest battery life · Best code density · , Core C28x Core 400 MIPS 400 MIPS LC2404,6 F243 F243 F240 F240 C240 C240 LF2407 LF2407 , 's Lowest mW/ MIPS DSPs Software Compatible C548 80 MIPS C542 50 MIPS C5420 200 MIPS C5410 100 MIPS 1st Generation C5402 100 MIPS C5421 200 MIPS C5409 C5416 100 MIPS 160 MIPS


Original
PDF C2000TM C5000TM C6000TM TMS320 1960s 1970s 1980s 1990s 2000s LF2407 program of GSM with ccs c compiler C28x C6711 DSP kit C5416 lc2402 TMS320TM 3G equipments dsl 500b st er C548
2004 - TC9446FG

Abstract: AD10 AD11 AD12 AD14 000Ah-007Fh
Text: at 50 MIPS operation · DSP Processor: 24 bit × 24 bit + 51 bit multiplier and adder, 51 bit , of the DLL clock, and processing speed can correspond a maximum of 75 MIPS . The clock outputted from , 12.288 MHz 73.728 MHz 49.152 MHz 38.864 MHz (48 kHz*256) (36 MIPS operation) (24 MIPS operation) (18 MIPS operation) 18.432 MHz 110.592 MHz 73.728 MHz 55.296 MHz (48 kHz*384) (55 MIPS operation) (36 MIPS operation) (27 MIPS operation) 24.576 MHz 147.456 MHz


Original
PDF TC9446FG TC9446FG P-QFP100-1420-0 AD10 AD11 AD12 AD14 000Ah-007Fh
2000 - MIPS R4000

Abstract: mips r4000 block diagram mips iii ejtag 2.0 MIPS MIPs datasheet EZ4030 R4000
Text: Corporation. The EZ4030 uses CoreWare® system-on-a-chip methodology and executes the MIPS III Instruction Set , High-Performance RISC CPU MIPS III Instruction Set Architecture ­ Single issue, 5-stage pipeline ­ ­ 250 native MIPS , 275 Dhrystone MIPS , and 160 Whetstone MIPS at 250 MHz MIPS III ISA supporting 64 , (Tj = 125 °C, VDD = 1.71 V, WC process) MIPS CPU standard interrupt exceptions (one nonmaskable , 1.8 V Core VDD ­ MIPS EJTAG 2.0 ­ ­ Instruction and data breakpoints G12TM CMOS


Original
PDF EZ4030 EZ4030 64-bit MIPS R4000 mips r4000 block diagram mips iii ejtag 2.0 MIPS MIPs datasheet R4000
2001 - TC9446F

Abstract: No abstract text available
Text: /1 instruction at 50 MIPS operation DSP Processor: 24 bit × 24 bit + 51 bit multiplier and adder, 51 , divided clock of the DLL clock, and processing speed can correspond a maximum of 75 MIPS . The clock , and DLL Clock 6th Times Clock 73.728 MHz (36 MIPS operation) 110.592 MHz (55 MIPS operation) 147.456 MHz (73 MIPS operation) to 150 MHz (75 MIPS operation) Not available Not available Not available 4th Times Clock 49.152 MHz (24 MIPS operation) 73.728 MHz (36 MIPS operation) 98.304 MHz (49 MIPS operation


Original
PDF TC9446F TC9446F
1999 - TMS320C5410

Abstract: ST c542 TLC320AD90 TMS320C5000 ADSP-2171 ADSP-2187L ADSP-2189L ADSP-218X C5000 C5402
Text: Efficient MIPS and on-chip memory/peripherals. while minimizing power/space/cost Optimized performance (channels/ MIPS ) Lower power (channels/watt) Reduced space (channels/in2) Lower , by available MIPS (1 Channel = G.723.1 + Echo Cancellation + VOP processing) 8 CONSTRAINTS Total MIPS 16 18 channels 16 16 On-chip Memory $10/channel Budget 2.35"x1.35" Space 18 , consumption? How does TI enable power-efficient performance at lower cost? 'C549: 100 MIPS in production


Original
PDF C6000? C5000? TMS320C5000 C5000 C5000: optimi00 ADI2189L TMS320C5420 C5420: TMS320C5410 ST c542 TLC320AD90 TMS320C5000 ADSP-2171 ADSP-2187L ADSP-2189L ADSP-218X C5402
2005 - uPD70F3766

Abstract: uPD70F35 uPD70F3824 uPD70F3453 uPD70F3793 uPD70F3740 QB-V850ESJG3U-TB uPD70F3746 V850E2 MN4 uPD70F3767
Text: 1 V850E/IH4-H V850ES/JJ3 2 V850 All FlashV850E2/MN4 , 1024 MIPS 200 MHz , , 16 , 2.1 32 V850E2/MN4 V850E2 2 7 V850E2M 1.42.56 MIPS /MHzCPU 2 MHz 1024 MIPS 200 60%0.88 mW/ MIPS MIPS 1200 FL-PR5 NET IMPRESS 1024 , 512 K 124 K RAM 10/100 Base MAC, CPU50 MHz103 MIPS 1.1 2. MAC IEEE802 , 1.42.56 MIPS /MHz MIPS 1200 2.1 1024 1000 800 CPU V850E2M 400 1024 MIPS


Original
PDF V850E, V850ES R01CL0006JJ0200 V850ES/HE3 V850ES/HG3 V850ES/HJ3 64-pin V850ES/HF3 80-pin 100-pin uPD70F3766 uPD70F35 uPD70F3824 uPD70F3453 uPD70F3793 uPD70F3740 QB-V850ESJG3U-TB uPD70F3746 V850E2 MN4 uPD70F3767
1998 - VR4305

Abstract: VR4310 NEC VR4310 VR43xx IEEE754 VR4300 fpu coprocessor accelerated technologies uPD30200 upd30210gd
Text: VR43xx VR family 64-bit MIPS RISC Microprocessor Product Letter Description The 64 , . Features · 64-bit MIPS RISC architecture · MIPS I, II and III instruction set · High-speed execution , clock supply · 1.4 W typical power consumption, VR4310 @ 100 MHz · Performance up to 221 Mips , Description CPU VR43xx devices employ a powerful 64-bit core with MIPS RISC architecture, capable of executing 32-bit MIPS I, II, and III instruction sets. Because of its 5-stage pipeline, one instruction can


Original
PDF VR43xx 64-bit VR43xx VR4300TM VR4300 VR4305 VR4310 NEC VR4310 IEEE754 fpu coprocessor accelerated technologies uPD30200 upd30210gd
1997 - voice recorder chip

Abstract: VOICE RECORDER playback system TMS320C54x SPEECH PROCESSING voice activated recorder circuit Message Management ISD33000 VOICE RECORDED playback system voice recording chip ISD recorder GMSK substitution ISD33000
Text: MIPS usage of the DSP. In order to perform these tasks within the required time frame requires a , there is pressure to reduce the MIPS requirements for longer battery life. PRAGMATIC COMMUNICATIONS , estimate the MIPS requirements for various functions. DSP performs channel encoding/decoding (4.5 MIPS ), GMSK modem and data filtering (15 MIPS ), Viterbi decoding and channel equalization (6 MIPS ), speech encoding/decoding (5 MIPS ), voice activity detection (0.5 MIPS ), etc.iii Thus a minimum of 35-40 MIPS is


Original
PDF ISD33000 TMS320C54X ISD33K voice recorder chip VOICE RECORDER playback system TMS320C54x SPEECH PROCESSING voice activated recorder circuit Message Management ISD33000 VOICE RECORDED playback system voice recording chip ISD recorder GMSK substitution
2000 - VR4121 mips

Abstract: VR4121 NEC AMC VR4111 VR4120 VRC4172 EDO RAM
Text: VR4121 VR family 64-bit MIPS RISC Microprocessor Family Product Letter Description , VxWorks based industrial and consumer applications. Designed around the popular MIPS ® RISC architecture , operating systems. Features · · · · · · · · VR4120 MIPS RISC CPU core MIPS I, II, III and MIPS 16 instruction set Performance up to 224 Mips at 168 MHz Fast single-cycle MAC instructions (DSP , 64-bit architecture that executes 32-bit MIPS I, II, III or 16-bit MIPS 16 instruction sets without


Original
PDF VR4121 64-bit VR4121TM VR4121 VR4120TM VR4121 mips NEC AMC VR4111 VR4120 VRC4172 EDO RAM
1998 - ColdFire v5

Abstract: asm68k 68ec040 XC68307 MCF5206EFT54 xcf5307 MCF5206FT33 0A31 DIAB data MCF5307FT90
Text: ColdFire Roadmap and Device Overview -8- ColdFire® Core Performance Roadmap V5 55xx 300 MIPS , frequency of operation ­ Software powerdown Write Back s Performance ­ 44 Dhrystone 2.1 MIPs @ 40 MHz , frequency of operation ­ Software powerdown s Performance * ­ MCF5202: 25 MIPS @ 33MHz ­ MCF5203: 24 MIPS @ 33MHz Debug Module JTAG Interface s Technology ­ ­ ­ ­ ­ ­ 0.8µm TLM CMOS 100 pin , + 5202 Daughter card avail. NOW * Dhrystone 2.1 MIPS using Diab 3.6f compiler - 13 -


Original
PDF 32-bit 16-bit MC680xl ColdFire v5 asm68k 68ec040 XC68307 MCF5206EFT54 xcf5307 MCF5206FT33 0A31 DIAB data MCF5307FT90
1999 - VR4121 mips

Abstract: VR4120 VR4121 VR4111 VRC4171A FPBGA NEC 1999
Text: VR4121 VR family 64-bit MIPS RISC Microprocessor Family Product Letter Description , based industrial and consumer applications. Designed around the popular MIPS ® RISC architecture, the , · · · · VR4120 MIPS RISC CPU core MIPS I, II, III and MIPS 16 instruction set Performance up to 224 Mips at 168 MHz Fast single-cycle MAC instructions (DSP) Memory management unit SDRAM , VR4120 core with a 64-bit architecture that executes 32-bit MIPS I, II, III or 16-bit MIPS 16


Original
PDF VR4121 64-bit VR4121TM VR4121 VR4120TM VR4121 mips VR4120 VR4111 VRC4171A FPBGA NEC 1999
Supplyframe Tracking Pixel