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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC2450CDC-1#TRMPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC2450IDC#PBF Linear Technology LTC2450 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC2450CDC#TRPBF Linear Technology LTC2450 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC2450CDC-1#PBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
LTC2450IDC-1#TRMPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: -40°C to 85°C
LTC2450CDC-1#TRPBF Linear Technology LTC2450-1 - Easy-to-Use, Ultra-Tiny 16-Bit Delta Sigma ADC; Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C

3 to 8 line decoder using 8051 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2003 - 8051 microcontroller based Digital clock with alarm

Abstract: Digital Alarm Clock using 8051 digital clock with alarm using 8051 compact flash interface with 8051 3 to 8 line decoder using 8051 data acquisition 8051 microcontrollers EPM7032V 8583 rtc RTC-8583 305E3
Text: Figure 2: Overview of the microMODUL- 8051 Low Power . 5 Figure 3 : Pin Layout of the , .10 Table 3 : J1 Access to External or Internal Program Memory .11 Table 4: J2 RAM , operated without protection circuitry if connections to the product's pin header rows are longer than 3 m , . © PHYTEC Meßtechnik GmbH 2003 L-305e_3 3 microMODUL- 8051 Low Power The microMODUL- 8051 Low Power , overloading through connected peripherals. As Figure 3 indicates, all controller signals extend to


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PDF microMODUL-8051 microMODUL-8051 L-305e D-55135 8051 microcontroller based Digital clock with alarm Digital Alarm Clock using 8051 digital clock with alarm using 8051 compact flash interface with 8051 3 to 8 line decoder using 8051 data acquisition 8051 microcontrollers EPM7032V 8583 rtc RTC-8583 305E3
2001 - 8051 microcontroller based Digital clock with alarm

Abstract: digital clock with alarm using 8051 compact flash interface with 8051 mini project with 8051 programs Digital Alarm Clock using 8051 80C323 3 to 8 line decoder using 8051 RTC-8583 EPM7032V DS80C323
Text: , the microMODUL- 8051 Low Power has 8 solder jumpers, some of which have been configured prior to , Figure 2: Overview of the microMODUL- 8051 Low Power . 5 Figure 3 : Pin Layout of the , .10 Table 3 : J1 Access to External or Internal Program Memory .11 Table 4: J2 RAM , longer than 3 m. © PHYTEC Meßtechnik GmbH 2001 L-305e_2 1 microMODUL- 8051 Low Power PHYTEC , typically draws power via 3 - 4 mignon cells. It can be populated with various 8051


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PDF microMODUL-8051 microMODUL-8051 L-305e D-55135 8051 microcontroller based Digital clock with alarm digital clock with alarm using 8051 compact flash interface with 8051 mini project with 8051 programs Digital Alarm Clock using 8051 80C323 3 to 8 line decoder using 8051 RTC-8583 EPM7032V DS80C323
1996 - 74LS00

Abstract: 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA HCTL1100
Text: such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s. Read , OSC Figure 1. Interfacing the HCTL-1100 to the 8051 Using I/O Ports , ;* RD1100: SETB P2.0 ; SET R/W LINE TO READ MOV CLR SETB MOV P1,B P2. 3 P2. 3 P1,#0FFH ; LATCH , HCTL-1100 P2.4 ; BRING RESET LINE HIGH RET 2-243 1 2 3 4 5 6 7 8 9 AD0 , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL1100 HCTL1100. HCTL-1100s 74LS00 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s microcontroller 8051s interfaces 74LS138 DATASHEET WR1100 74LS00 DATA
2007 - 3 to 8 line decoder using 8051

Abstract: 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET HCTL-1100 74LS138 HCTL-1100 M-015 HCTL-1100s
Text: chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four , ;* RD1100: SETB P2.0 ; SET R/W LINE TO READ MOV CLR SETB MOV P1,B P2. 3 P2. 3 P1,#0FFH ; LATCH , HCTL-1100 P2.4 ; BRING RESET LINE HIGH RET 3 1 2 3 4 5 6 7 8 9 AD0 AD1 , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 , Figure 2. Interfacing the HCTL-1100 to the 8051 Using the Address/Data Bus. 4 R/W OE CS ALE


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PDF HCTL-1100 M-015 HCTL-1100/8051 HCTL-1100 HCTL-1100. WR1100: CS1100 3 to 8 line decoder using 8051 74LS00 74LS00 DATA TTL 74ls00 74LS00 TTL 74LS138 DATASHEET 74LS138 HCTL-1100 M-015 HCTL-1100s
Not Available

Abstract: No abstract text available
Text: decoder , all 8 bits are transferred without modification from the input to both the serial and parallel , input is a multi­ plexed encoder/ decoder input to provide interleaved signals. The transfer rate of , mode; then the decoder path PSIG[0] must be left open or connected to ground. Embedded Coding The B , always provides the maximum number of bits (up to 5) defined by the code selected. The decoder requires , decoder input. This input signal is applied to bits 1 and 2 o f the parallel input bus. If embedded


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PDF Bt8110 MIL-STD-883C, JC-40 Bt8110
Not Available

Abstract: No abstract text available
Text: E N high. The serial input is a multiplexed encoder/ decoder input to provide interleaved signals , given channel for either an encoder or a decoder , all 8 bits are transferred without modification from , 5) defined by the code selected. The decoder requires up to 5 A D PC M bits and a 2-bit encoded input that indicates how many bits are present at the decoder input. This input signal is applied to , ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] A[ 3 ] A[4] A[5] D[0] D[1] D[2] D[ 3 ] VCC GND D[4] D[5] D[6] D[7] A[6] A[7] A[ 8 ] GND


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PDF Bt8110/ix t8110/8110B L8110B
tl3101

Abstract: 68HCll 68HC11 PCM-123 68hc11 l6
Text: decoder , all 8 bits are transferred without modification from the input to both the serial and parallel , Pin Description. 3 Functional Description. 8 , serial input is a multiplexed encoder/ decoder input to provide interleaved signals. The transfer rate of , mode; then the decoder path PSIG[0] must be left open or connected to ground. Embedded Coding The , number of bits (up to 5) defined by the code selected. The decoder requires up to 5 ADPCM bits and a 2


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PDF Bt8110 tl3101 68HCll 68HC11 PCM-123 68hc11 l6
2006 - HCTL-20XX

Abstract: intel 8051 microcontroller memory allocation of 8051 8051 reset circuit microcontroller 8051s interfaces hctl 3 circuit for 8051 interface with memory HCTL-2020 HCTL-2000 8051 address decoder
Text: decoder in this circuit consists of a single 8 -input NAND gate which is used to decode the base address , circuitry to select any arbitrary address in the 8051 's external address space. The SEL line can also be , 12 OE 5 RST 2 8 1 2 74LS32 CLK 3 (OPTIONAL) 12 MHz OSC Figure 2. 8051 , IS 0FE00H ;2) THE SEL LINE IS CONNECTED TO A8 : 3 ) THE RESET LINE IS CONNECTED TO P1 , LINE IS ;CONNECTED TO P1.0 ON THE 8051


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PDF HCTL-20XX M-017 HCTL-2000, HCTL-2000 12-bit HCTL-2016 HCTL-2020 16-bit RS2000 intel 8051 microcontroller memory allocation of 8051 8051 reset circuit microcontroller 8051s interfaces hctl 3 circuit for 8051 interface with memory HCTL-2020 HCTL-2000 8051 address decoder
1996 - intel 8051 microcontroller

Abstract: 8051 address decoder memory allocation of 8051 HCTL-20XX 8051 reset circuit what is 74LS32 M-017 microcontroller 8051s interfaces hctl 3 HCTL-2020
Text: their own address decoder circuitry to select any arbitrary address in the 8051 's external address , CHB TO ENCODER Vcc 16 8 RST 2 CLK 74LS32 8 1 2 3 (OPTIONAL) 12 MHz OSC , IS 0FE00H ;2) THE SEL LINE IS CONNECTED TO A8 : 3 ) THE RESET LINE IS CONNECTED TO P1 , LINE IS ;CONNECTED TO P1.0 ON THE 8051 , H Interfacing the HCTL-20XX to the Intel 8051 Application Brief M-017 Introduction The


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PDF HCTL-20XX M-017 HCTL-2000, HCTL2000 12-bit HCTL-2016 HCTL-2020 16-bit HCTL-20XX RD2000: intel 8051 microcontroller 8051 address decoder memory allocation of 8051 8051 reset circuit what is 74LS32 M-017 microcontroller 8051s interfaces hctl 3 HCTL-2020
1999 - intel 8051 microcontroller

Abstract: intel 8051 031H 8051 reset circuit 8051 address decoder HCTL-2016 hctl 3 microcontroller 8051s interfaces 74ls30 datasheet INTEL 8051 DATASHEET
Text: their own address decoder circuitry to select any arbitrary address in the 8051 's external address , ) THE SEL LINE IS CONNECTED TO A8 : 3 ) THE RESET LINE IS CONNECTED TO P1 , LINE IS ;CONNECTED TO P1.0 ON THE 8051 , Interfacing the HCTL-20XX to the Intel 8051 Application Brief M-017 Introduction The HCTL , the HCTL-20XX family to an Intel 8051 microcontroller bus. The hardware interface is shown in


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PDF HCTL-20XX M-017 HCTL-2000, HCTL2000 12-bit HCTL-2016 HCTL-2020 16-bit HCTL-20XX H2000H intel 8051 microcontroller intel 8051 031H 8051 reset circuit 8051 address decoder hctl 3 microcontroller 8051s interfaces 74ls30 datasheet INTEL 8051 DATASHEET
1999 - 8051 microcontroller block diagram

Abstract: DS80C320 user manual 8051 microcontroller block diagram details SAB-C504 SAB-C502 SAB-C501 PLCC-44 DS80C320 COM20051 80C32
Text: microMODUL- 8051 8 © PHYTEC Meßtechnik GmbH 1999 L-168e_5 Jumper 3 Jumpers For configuration , header rows are longer than 3 m. © PHYTEC Meßtechnik GmbH 1999 L-168e_5 1 microMODUL- 8051 , to be put into circulation. The microMODUL- 8051 is one of a series of PHYTEC nano/micro/miniMODULs , enables a COM20051 based microMODUL- 8051 to run at up to 255 nodes in an ARCnet network. Precise , 1999 L-168e_5 3 microMODUL- 8051 The microMODUL- 8051 offers the following features: · · ·


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PDF microMODUL-8051 L-168e D-55135 8051 microcontroller block diagram DS80C320 user manual 8051 microcontroller block diagram details SAB-C504 SAB-C502 SAB-C501 PLCC-44 DS80C320 COM20051 80C32
1999 - 80C51

Abstract: APEX20K APEX20KC APEX20KE DP80C51 FLEX10KE vhdl code for rs232 receiver altera
Text: 8051 Pipelined RISC architecture enables to execute instructions up to 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster addition Up , line Read/write of single line and 8 -bit group Two 16-bit timer/counters Timers clocked by , control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller , connected to appropriate pins of P3 port. Ports - Block contains 8051 's general purpose I/O ports. Each


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PDF DP80C51 DP80C51 DP80C51: 80C51 APEX20K APEX20KC APEX20KE FLEX10KE vhdl code for rs232 receiver altera
1999 - 80C154

Abstract: fc01h 8051 microcontroller interface with rs485 RS485 INTERFACE WITH 8051 SAB-C504 SAB-C502 SAB-C501 PLCC-44 DS80C320 user manual COM20051
Text: header rows are longer than 3 m. © PHYTEC Meßtechnik GmbH 1999 L-168e_5 1 microMODUL- 8051 , to be put into circulation. The microMODUL- 8051 is one of a series of PHYTEC nano/micro/miniMODULs , enables a COM20051 based microMODUL- 8051 to run at up to 255 nodes in an ARCnet network. Precise , 1999 L-168e_5 3 microMODUL- 8051 The microMODUL- 8051 offers the following features: · · · , port pins. For further details please refer to the Data Sheet of the controller on the microMODUL- 8051


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PDF microMODUL-8051 L-168e D-55135 80C154 fc01h 8051 microcontroller interface with rs485 RS485 INTERFACE WITH 8051 SAB-C504 SAB-C502 SAB-C501 PLCC-44 DS80C320 user manual COM20051
1997 - 3 to 8 line decoder using 8051

Abstract: 1-wire 8051 code
Text: "steals" least 60 s to provide a timing margin power from the data line allows a verfor worst-case , half-wave rectifier to proshown in Figure 1, when the data line vide parasitic power for a line of prodis , pulls the bus low to signal a a unique individual identification code and each 1-wire bit, using short , the MicroLAN and describes its fea- 14.4 kbps data rate (115.2 / 8 = 14.4 kbps), the data line again , a logic level zero any slave connected to the line . The master A clever circuit technique that


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PDF DS9097 3 to 8 line decoder using 8051 1-wire 8051 code
1997 - microcontroller 8051 dallas semi datasheet

Abstract: 1-wire 8051 code DS2401 3 to 8 line decoder using 8051 DS1990A DS1986 DS2502 DS9097 internal and external memories of 8051 memory con DS0621-SDK
Text: power from the data line allows a verleast 60 s to provide a timing margin satile new communication , half-wave rectifier to proshown in Figure 1, when the data line vide parasitic power for a line of prodis , pulls the bus low to signal a a unique individual identification code and each 1-wire bit, using short , the MicroLAN and describes its fea- 14.4 kbps data rate (115.2 / 8 = 14.4 kbps), the data line again , indicating a logic level zero any slave connected to the line . The master S DS9097 COM PORT ADAPTER


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PDF
1996 - PCM61

Abstract: E1 PCM encoder PCM-59 circuit diagram of speech to text with 8051 Bt8110B 8110b PCM encoder tellabs transcoder tellabs PCM-122
Text: the input PSIGEN high. The serial input is a multiplexed encoder/ decoder input to provide interleaved , channel for either an encoder or a decoder , all 8 bits are transferred without modification from the , encoder always provides the maximum number of bits (up to 5) defined by the code selected. The decoder , decoder input. This input signal is applied to bits 1 and 2 of the parallel input bus. If embedded coding , are detailed in Table 1-2. 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VCC PSIGEN


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PDF Bt8110/8110B Bt8110 Bt8110B PCM61 E1 PCM encoder PCM-59 circuit diagram of speech to text with 8051 8110b PCM encoder tellabs transcoder tellabs PCM-122
2013 - Not Available

Abstract: No abstract text available
Text: controlled by an internal 8051 -compatible microprocessor. This is connected to 3 internal memories. The , . 8 3 Pin diagram , Core and I/O ground S S S 1.8 3.3 0 3.3 Crystal GPP’s 3 , 8 ,16,17,18 GPP(7:0) 19 , four 30 MHz cycles. There are 3 timers in the 8051 . There are no serial ports. There are 7 interrupts , , for example, 45.0 MHz. Conversion of the 45.0 MHz signal to the OFDM sample rate is achieved using


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PDF PS20230 PS20230C1L1A5
1999 - verilog code for 32 bit risc processor

Abstract: verilog code for 16 bit risc processor 8051 16bit addition, subtraction verilog code for TCON verilog code for 32-bit alu with test bench 16 bit single cycle mips vhdl 8 BIT ALU design with vhdl code 8051 8bit microcontroller verilog code for 32 BIT ALU implementation 3 bit alu using verilog hdl code
Text: architecture enables to execute instructions 6.7 times faster compared to standard 8051 12 times faster , module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. All , High Performance Configurable 8 -bit Microcontroller ver 3.01 OVERVIEW CPU FEATURES DR8051CPU is a high performance, area optimized soft core of a single-chip 8 -bit embedded controller , . DR8051CPU soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are


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PDF DR8051CPU DR8051CPU: verilog code for 32 bit risc processor verilog code for 16 bit risc processor 8051 16bit addition, subtraction verilog code for TCON verilog code for 32-bit alu with test bench 16 bit single cycle mips vhdl 8 BIT ALU design with vhdl code 8051 8bit microcontroller verilog code for 32 BIT ALU implementation 3 bit alu using verilog hdl code
PCM-59

Abstract: PCM58
Text: ] PSIG[0] Encoder In Sign Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Decoder In 1 1 I2 13 14 , ] Bt8110 Decoder Out Sign Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Encoder Out 1 1 I2 I3 I4 I5 , Registers B t 8 110 EN_TRPT CODE[ 3 :0] Enable Transparent O peration- Uses the B t8 110 to transfer the 8 -bit input to the output w ith out any m odifications for both encoder and decoder channels , / decoder input to provide interleaved signals. The transfer rate of the serial input is one-half the input


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PDF t8110 L811001 PCM-59 PCM58
2006 - DVB-T Schematic set top box

Abstract: CE6353 ce6353 design manual ce6230 tuner sd 1228 ce6353 registers IR remote control ce6230 dvb-t usb schematic diagram CE6231 8051 microcontroller
Text: IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY , IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR , , life sustaining applications. Intel may make changes to specifications and product descriptions at any , responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This manual


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PDF CE6231 D73701-003 ITU-656 DVB-T Schematic set top box CE6353 ce6353 design manual ce6230 tuner sd 1228 ce6353 registers IR remote control ce6230 dvb-t usb schematic diagram 8051 microcontroller
1999 - vhdl code mips code

Abstract: No abstract text available
Text: standard 8051 Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster addition Up to 256 bytes of internal (on-chip , Four 8 -bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8 , connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface ­ , DP8051 Pipelined High Performance 8 -bit Microcontroller ver 4.05 OVERVIEW DP8051 is an ultra


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PDF DP8051 DP8051 DP8051: vhdl code mips code
1996 - PCM-59

Abstract: No abstract text available
Text: / decoder input to provide interleaved signals. The transfer rate of the serial input and output is one-half , operation is selected for a given channel for either an encoder or a decoder , all 8 bits are transferred , code selected. The decoder requires up to 5 ADPCM bits and a 2-bit encoded input that indicates how many bits are present at the decoder input. This input signal is applied to bits 1 and 2 of the , AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT VCC GND AD[ 3 ] RESET SYNC CS MICREN AD[4] AD[5] VCC 9 8 7


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PDF Bt8110/B Bt8110/8110B Bt8110 Bt8110B PCM-59
1996 - PCM-59

Abstract: Bt8200EVM-T1 syn 7580 8110b PCM-122 PCM-123 tellabs transcoder circuit diagram of traffic 3 led only PCM63 PCM61
Text: Estimate DECODER Adaptive Predictor Brooktree ® Convert to PCM Synchronous Coding , expected to result in personal injury or death. Brooktree customers using or selling Brooktree products , the input PSIGEN high. The serial input is a multiplexed encoder/ decoder input to provide interleaved , channel for either an encoder or a decoder , all 8 bits are transferred without modification from the , always provides the maximum number of bits (up to 5) defined by the code selected. The decoder requires


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PDF Bt8110/8110B Bt8110 Bt8110B PCM-59 Bt8200EVM-T1 syn 7580 8110b PCM-122 PCM-123 tellabs transcoder circuit diagram of traffic 3 led only PCM63 PCM61
2004 - "7 Segment Display using 8051

Abstract: keyboard interfacing with 8051 keypad security system using 8051 with 8051 interfacing lcd keypad IR switch using 8051 with eprom 2416 8051 with lcd led interface with 8051 Digital Clock LCD 8051 KEYPAD 8051
Text: high to low. The rotating 1-of-16 decoder will stop and interrupt the 8051 signalling a key has been , -2416) handle the character generation and refresh, and require the 8051 only to write ASCII data through an 8 , ,000 writes/s to sustain this display. This is easly handled by the 16MHz 8051 . Other types of , latched. An 8 character hex display using these devices would use 4 GPOUT pins and 8 KSO lines. Using the 95x's mailbox registers, or parallel port access, the Host CPU can write POST codes to the 8051


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PDF FDC37C95x FDC37C957FR "7 Segment Display using 8051 keyboard interfacing with 8051 keypad security system using 8051 with 8051 interfacing lcd keypad IR switch using 8051 with eprom 2416 8051 with lcd led interface with 8051 Digital Clock LCD 8051 KEYPAD 8051
2005 - NX5850

Abstract: LCD 128x64 8051 mp3 player circuit diagram 0xFF03 NX5855 graphical lcd 128X64 8051 free AVDD115 AVDD111 AGND112
Text: . 8051 Port 2 P2 is an 8 -bit bidirectional I/O port. 8051 Port 3 P3 is an 8 -bit bidirectional I/O port , i 8051 8 -bit CPU General IO ports (Port 1, 2, 3 ) 64Kbyte external RAM on the chip (Compatible , 8 . SYSTEM CONTROL BLOCK . 3 , encoder MP3 Encoder for MPEG1/2 Audio Layer 3 and MP3 Decoder for MPEG1/2/2.5 Audio Layer 3 Includes , of NX5850 8 RTC NX5850 Preliminary Digital Audio SoC 3 . Signal Descriptions 9


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PDF NX5850 NX5850 LCD 128x64 8051 mp3 player circuit diagram 0xFF03 NX5855 graphical lcd 128X64 8051 free AVDD115 AVDD111 AGND112
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