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2SK103-L2 datasheet (1)

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Not Available

Abstract: No abstract text available
Text: No file text available


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PDF 2SK103
Not Available

Abstract: No abstract text available
Text: No file text available


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PDF 2SK103L2
FET 2SK125

Abstract: FET 2SK109 2SK109 2SK97 2SK105 2SK104 2sk109a 2SK120 2SK107 2SK124
Text: No file text available


OCR Scan
PDF 2SK84 2SK85 2SK87 2SK89 2SK92 2SK93 2SK94 2SK97 2SK103 2SK104 FET 2SK125 FET 2SK109 2SK109 2SK105 2sk109a 2SK120 2SK107 2SK124
2sk129

Abstract: 2sk150 datasheet 2SK101 2SK107 data sheet 2sk122 2SK105 Datasheet 2SK109 2SK182E 2sk146 datasheet 2SK131
Text: No file text available


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PDF 2SK101 2SK102 2SK103 2SK104 2SK105 2SK106 2SK107 2SK108 2SK109 2SK109A 2sk129 2sk150 datasheet 2SK101 2SK107 data sheet 2sk122 2SK105 Datasheet 2SK109 2SK182E 2sk146 datasheet 2SK131
irf1740

Abstract: IRL244 IRF1740A ks 0550 IRL244A SSH6N80A IRFZ34A IRLR034A IRFS640 irfs750
Text: !.1 Vol.1 Vol.1 V o l.2 V o l.2 V o l.2 V o l.2 V o l.2 V o l.2 V o l.2 Voi .2 V o l.2 V o l.2 V o l.2 V o l.2 Vol. 2 V o l.2 V o l.2 Vol.1 Vol.1 Vol.1 Vol.1 Vol.1 Vol.1 Vol.1 V o l.2 V o l.2 V o l.2 V o l.2 V o l.2 V o l.2 V o l.2 Vol. 2 Vol. 2 V o l.2 V o l.2 V o l.2 ; Rds(oo) Package Remark ,Qo , 2.78 2.50 P D (W) 28 44 49 45 50 45 50 Page Vol. 2 V o l.2 V o l.2 67 73 79 85 [ Ros(on) ,Qg: Package , 18 18 30 42 22 35 46 21 33 48 Page Vol.1 Vol.1 Vol.1 Vol.1 Vol.1 Vol.1 Vol.1 V o l.2 Vol. 2 Vol. 2


OCR Scan
PDF SSR3055A IRFR014A IRFR024A IRFR034A IRFR110A IRFR120A IRFR130A IRFR210A IRFR220A IRFR230A irf1740 IRL244 IRF1740A ks 0550 IRL244A SSH6N80A IRFZ34A IRLR034A IRFS640 irfs750
CDT3400-02

Abstract: CDT3400 CDT-3400-1 CDT3400-01 CDT3400-03 CDT-3400-14 L2L3 CDT-3400-07 CDT-3400-09 3400-02
Text: KEY A U TO V D D S5 S4 S4 S3 CdS OSCO KEY S5 S3 S2 L1 L2 , 4 L2 3 L1 16 PIN DIP VSS 2 1 16 VSS 2 3 4 15 14 13 OFF TEST VDD 5 6 7 12 11 10 S2 S3 S4 KEY OSCO OSCO 8 9 S5 L1 L2 L3 1 , 3 3 L1 175 125 LED 4 4 L2 415 125 LED 5 5 L3 640 , CDT3400 P. 3 3 LED IC : (L1, L2 ,L3) VDD IOP Min 1.5 30 ILED


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PDF CDT3400 00VDC CDT-3400-14 CDT-3400 CDT-3400 CDT3400-02 CDT3400 CDT-3400-1 CDT3400-01 CDT3400-03 CDT-3400-14 L2L3 CDT-3400-07 CDT-3400-09 3400-02
2002 - WED3C7410E16M-400BX

Abstract: WED3C750A8M-200BX WED3C7558M-XBX 7410E
Text: 7410E AltiVec RISC processor FEATURES · Dedicated 2MB SSRAM L2 cache, configured as 256Kx72 n , set · Maximum L2 Cache frequency = 200MHz n Optional, high-bandwidth MPX bus interface · , Reservation Station 64- 32-Bit L2 Data Bus 32-Bit + 64-Bit Data Bus 32-Bit Address Bus L2PMCR L2CR L2 Tags L2 Controller . . L2 Data Transaction Queue + x Interger Unit 2 Interger Unit 1 GPR File 6 Rename Buffers Vector Touch Queue . . L2 Castout


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PDF WED3C7410E16M-400BX WED3C7410E16M-400BX 7410E/SSRAM 7410E 16Mbits 7410E WED3C750A8M-200BX WED3C7558M-XBX
2003 - Not Available

Abstract: No abstract text available
Text: Dedicated 2MB SSRAM L2 cache, configured as 256Kx72 · 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) · Maximum Core frequency = 400MHz @ 1.8V · Maximum L2 Cache frequency = 200MHz · Maximum 60x Bus frequency = , Operations 64-Bit 64-Bit + x . . FPSCR VSCR 128-Bit 128-Bit Completion Unit L2 Tags L2CR L2PMCR L2 Data Transaction Queue L2 Controller Bus Interface Unit L2 Miss Data Transaction Queue L2 , to complete up to two instructions per clock 19-Bit L2 Address Bus 64- 32-Bit L2 Data Bus 32


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PDF WED3C7410E16M-400BX 7410E/SSRAM WED3C7410E16M-400BX 7410E 256Kx72 21mmx25mm, 400MHz 200MHz 100MHz
PT2559B-L2-A6

Abstract: PT2559B 24 L2 diode a7 L3 code transistor A7 PT5529B
Text: lead frame product leg Item Original Part Number Revised part number 1 PT5529B / L2 (YK) PT5529B/L2-F(YK) 2 PT5529B/ L2 PT5529B/L2-F 3 PT5529B/ L2 (A10) PT5529B/L2-F(A10) 4 PT5529B/ L2 (A12) PT5529B/L2-F(A12) 5 PT5529B/ L2 (A2) PT5529B/L2-F(A2) 6 PT5529B/ L2 (A3) PT5529B/L2-F(A3) 7 PT5529B/ L2 (A4) PT5529B/L2-F(A4) 8 PT5529B/ L2 (A4)(CDS) PT5529B/L2-F(A4)(CDS) 9 PT5529B/ L2 (A5) PT5529B/L2-F(A5) 10 PT5529B/ L2 (A5)(CDS) PT5529B/L2-F(A5)(CDS


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PDF PCN070131001 Min17 PT2559B/L2-F PT2559B/L2 PT2559B/L2/H2 PT2559B-L2-A6 PT2559B 24 L2 diode a7 L3 code transistor A7 PT5529B
AL205

Abstract: AL207 AL212 L23C 68319A l22f 4166C3 B5D04 AL262 L25D
Text: L2 _0 0 L2 _02 L2 _0 3 L2 _04 L2 _0 5 L2 _0 6 L2 _0 7 L2 -08 L2 -09 L2 -0A L2 _0B L2 _0C L2 _0D L2 _0E L2 _0F L2 _10 L2_ll L2 _12 L2 _13 L2 _14 L2 _15 L2 _16 L2 _17 L2_l 8 L2 _19 L2 _1A L2 _1B L2 _1C L2 _1D L2 _1E L2 _1F L2 _2 0 L2 _21 L2 _2 2 L2 _2 3 L2 _2 4 L2 _25 L2 _2 6 L,2_2 7 L2 _2 8 L2 _2 9 L2 _2A L2 _2B I;2_2C L2 _2D L2 _2E « -1 o 1 C N , -0.5653718 DC$B8B2 5 ? -0 .5570565 L2 _2F L2 _3 0 L2 _31 L2 _3 2 L2 _33 L2 _34 L2 _35 L2 _36 L2 _3 7 L2 _38 L2 _39 L2 _3A L2 _3B L2 _3C. L2 _3D L2 _3E L2 _3F L2 _4 0 L2 _41 L2 _4 2 L2 _4 3 L2 _4 4 L2 _4 5 L2 _4 6 L2 _4 7 L2 _4 8 L2 _4 9


OCR Scan
PDF L2-08 L2-09 816FE5 82DCF3 85AEB5 87137F 89D518 8B31FB 8C8C51 91DCD2 AL205 AL207 AL212 L23C 68319A l22f 4166C3 B5D04 AL262 L25D
1998 - G5 SOT 23

Abstract: L2 SOT23
Text: ) (mOhms) @4.5V @10V HUF76145P3 HUF76145S3 TO-220 TO-262 N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 , -251 N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) N ( L2 ) 30 30 30 30 30 30 30 30 30 30


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PDF HUF76145P3 HUF76145S3 O-220 O-262 LC-98030 G5 SOT 23 L2 SOT23
2002 - WED3C750A8M-200BX

Abstract: No abstract text available
Text: White Electronic Designs WED3C750A8M-200BX RISC Microprocessor Module OVERVIEW Maximum L2 , L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) NO TR EC OM , DIAGRAM, L2 INTERCONNECT 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com , , F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 Pin Number High I/O AACK L2 , including during power-on reset. 5. L2 AVdd is internally tied to AVdd. L2 OVdd is internally tied to OVdd


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PDF WED3C750A8M-200BX 100MHz 750/SSRAM 66MHz WED3C750A8M-200BX
2002 - 16X16 BIT RISC PROCESSOR

Abstract: No abstract text available
Text: processor · Dedicated 2MB SSRAM L2 cache, configured as 256Kx72 · 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) · Maximum Core frequency = 400MHz @ 1.8V · Maximum L2 Cache frequency = 200MHz · Maximum 60x Bus , VSCR 128-Bit Completion Unit L2 Tags L2CR L2PMCR L2 Data Transaction Queue L2 Controller Bus Interface Unit L2 Miss Data Transaction Queue L2 Castout Memory Subsystem Data Reload Data Reload Table Buffer Completion Queue (8 Entry) Ability to complete up to two instructions per clock 19-Bit L2


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PDF WED3C7410E16M-400BX 7410E/SSRAM WED3C7410E16M-400BX 7410E 256Kx72 21mmx25mm, 400MHz 200MHz 100MHz 16X16 BIT RISC PROCESSOR
1992 - a798

Abstract: AL207 AL205 74242 AL233 0647d transistor B541 AL235 D604 e17a
Text: .4 LOG2 X TABLE (X DATA ROM) _ORG X: $0100 L2 _00 DC $800000 L2 _01 DC $816FE5 L2 _02 DC $82DCF3 L2 _03 DC $844734 L2 _04 DC $85AEB5 L2 _05 DC $87137F L2 _06 DC $88759C L2 _07 DC $89D518 L2 -08 DC $8B31FB L2 -09 DC $8C8C51 L2 -0A DC $8DE421 L2 _0B DC $8F3976 L2 _0C DC $908C59 L2 _0D DC $91DCD2 L2 _0E DC $932AEA L2 _0F DC $9476AA L2 _10 DC $95C01A L2 _11 DC $970743 L2 _12 DC $984C2C L2 _13 DC $98EDD L2 _14 DC $9ACF5E L2 _15 DC $9C0DB7 L2 _16 DC $9D49EE L2 _17 DC $9E840C L2 _18 DC $9FBC17 L2 _19 DC $A0F216 L2


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PDF DSP56004 DSP56004ROM BE31E2 C3A946 C67323 C945E0 CC210D CF043B D7D947 a798 AL207 AL205 74242 AL233 0647d transistor B541 AL235 D604 e17a
2007 - 7410E

Abstract: WED3C7410E16M-XBHX WED3C7410E16M-XBX WED3C750A8M-200BX WED3C7558M-XBX
Text: 2MB SSRAM L2 cache, configured as 256Kx72 21mmx25mm, 255 HiTCETM Ball Grid Array (CBGA , , high-bandwidth MPX bus interface Maximum L2 Cache frequency = 200MHz HiTCETM interposer for TCE , Station 64- 32-Bit L2 Data Bus 32-Bit + L2PMCR L2CR L2 Tags 64-Bit Data Bus 32-Bit Address Bus L2 Data Transaction Queue L2 Controller . . GPR File 6 Rename Buffers Vector Touch Queue . . L2 Castout L2 Miss 32-Bit PA Data Transaction Queue Bus


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PDF WED3C7410E16M-XBHX 7410E WED3C7410E16M-XBHX 7410E/SSRAM 7410E 133MHz WED3C7410E16M-XBX WED3C750A8M-200BX WED3C7558M-XBX
2002 - Not Available

Abstract: No abstract text available
Text: package consists of: · 755 RISC processor (E die revision) · Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 · 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) · Core Frequency/ L2 Cache Frequency (300MHz , WED3C755E8M-XBX FIG. 3 BLOCK DIAGRAM, L2 INTERCONNECT SSRAM 1 L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA L2DP0-3 L2 CLK_OUT A L2WE L2CE DQa DQb DQc DQd DP0-3 K SGW SE1 SE2 U1 FT SBd SBc SBb SBa SW ADSP ADV L20Vdd , DQc DQd DP0-3 ZZ L2ZZ SE3 LBO G FIG. 4 BLOCK DIAGRAM, L2 INTERCONNECT TDI 755E TDO TMS TCK TRST


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PDF WED3C755E8M-XBX 755E/SSRAM WED3C755E8M-XBX 128Kx72 21mmx25mm, 300MHz/ 150MHz, 350MHz/175MHz) 66MHz
2001 - MPC745

Abstract: MPC755 WED3C750A8M-200BX WED3C7558M-XBX
Text: . The WED3C7558M-XBX multichip package consists of: · 755 RISC processor · Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 · 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) · Core Frequency/ L2 Cache , Rename Buffers L2 Cache BIU L2 Cache Bus SSRAM White Electronic Designs Corporation · (602 , , L2 Interconnect SSRAM 1 L2pin_DATA DQa L2pin_DATA DQb L2pin_DATA DQc L2pin_DATA , L2 CLK_OUT A L2WE L2CE ADSC SE3 LBO SA0-16 G ZZ µP 755 A0-16 SSRAM 2 SA0


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PDF WED3C7558M-XBX WED3C7558M-XBX 755/SSRAM MPC745 MPC755 WED3C750A8M-200BX
2001 - Not Available

Abstract: No abstract text available
Text: . The WED3C7558M-300BX multichip package consists of: · 755 RISC processor · Dedicated 1MB SSRAM L2 , 300MHz · Maximum L2 Cache frequency = 150MHz · Maximum 60x Bus frequency = 66MHz PRELIMINARY * The , L2 Cache BIU 60x BIU L2 Cache Bus 60x Bus SSRAM SSRAM White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com 2 WED3C7558M-300BX FIG. 3 Block Diagram, L2 Interconnect SSRAM 1 L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA L2DP0-3 L2 CLK_OUT A L2WE L2CE DQa DQb DQc


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PDF WED3C7558M-300BX 755/SSRAM WED3C7558M-300BX 128Kx72 21mmx25mm, 300MHz 150MHz 66MHz
2006 - ppc460

Abstract: embedded powerpc 460 powerpc 460 il2d PPC440 mtdcrx a/a/a/PPC440
Text: PPC440 core. The PPC460 cores are available in configurations with and without a coherent L2 cache (L2C). Configurations without a coherent L2 cache utilize the PLB4 on-chip interconnect bus. Configurations with a coherent L2 cache utilize the PLB5 bus and support additional coherent synchronization , introduction discussing the section's relevance to configurations with and without a coherent L2 cache , cores both with and without a coherent L2 cache implement the new extended DCR functionality. Updates


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PDF 460migrate ppc460 embedded powerpc 460 powerpc 460 il2d PPC440 mtdcrx a/a/a/PPC440
2000 - Not Available

Abstract: No abstract text available
Text: WED3C7558M-300BX multi-chip package consists of: · 755 RISC processor · Dedicated 1MB SSRAM L2 cache , Maximum L2 Cache frequency = 150MHz · Maximum 60x Bus frequency = 66MHz FEATURES s Footprint , LSU FPRs FPU Rename Buffers 32K DCache L2Tags L2 Cache BIU 60x BIU L2 Cache Bus , 2 WED3C7558M-300BX FIG. 3 Block Diagram, L2 Interconnect SSRAM 1 L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA L2DP0-3 L2 CLK_OUT A L2WE L2CE DQa DQb DQc DQd DP0-3 K SGW SE1 SE2 U1 FT SBd SBc SBb


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PDF WED3C7558M-300BX WED3C7558M-300BX 755/SSRAM
2012 - Not Available

Abstract: No abstract text available
Text: die revision) * This product is subject to change without notice. ï®ï€ Dedicated 1MB SSRAM L2 , processor die). ï®ï€ 21mmx25mm, 255 HiTCE™ Ball Grid Array (CBGA) ï®ï€ Core Frequency/ L2 Cache , €¢ www.microsemi.com/pmgp www.whiteedc.com WED3C755E8MC-XBHX FIGURE 3 – BLOCK DIAGRAM, L2 INTERCONNECT , # SBc# SBb# SBa# SW# ADSP# ADV# DP0-3 L2DP0-3 SE2 K SGW SE1 L2 CLK_OUT A L2WE , , H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 A10 L1 B6 B1 E1 D8 A6 D7 J14 N1 H15 G4 P14


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PDF WED3C755E8MC-XBHX 755E/SSRAM WED3C7558MC-XBX WED3C755E8MC-XBHX 128Kx72
2008 - PPC750

Abstract: ppc750L addis 0x00001040
Text: ® Testing the L2 Cache in PPC750xx Processors Application Note Nov 18, 2008 , Microelectronics Division home page can be found at http://www.ibm.com/chips Application Note Testing the L2 , to verify the proper operation of the L2 cache tag memory, external SRAM, and overall L2 cache system. The PowerPC 750xx family of processors contains features to enable L2 cache testing. This , description of methods for testing the cache, and in many cases sample code. L2 Cache Test Features and


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PDF PPC750xx PPC750 ppc750L addis 0x00001040
2012 - Not Available

Abstract: No abstract text available
Text: reliability ï®ï€ Dedicated 2MB SSRAM L2 cache, configured as 256Kx72 ï®ï€ Available with eutectic , configuration core frequency is 400MHz. ï®ï€ Core frequency = 450 or 400MHz ï®ï€ Maximum L2 Cache , -Bit SSRAM Reservation Station 64- 32-Bit L2 Data Bus 32-Bit + 64-Bit Data Bus 32-Bit Address Bus L2PMCR L2CR L2 Tags L2 Controller . . L2 Data Transaction Queue + x Interger Unit 2 Interger Unit 1 GPR File 6 Rename Buffers Vector Touch Queue . . L2


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PDF WED3C7410E16MC-XBHX 7410E 7410E/SSRAM WED3C7410E16M-XBX, WED3C7558M-XBX WED3C750A8M-200BX WED3C7410E16MC-XBHX 63Pb/37SN) 63Sn/37Pb)
2005 - MPC755

Abstract: WED3C750A8M-200BX WED3C7558M-XBX e7 adn
Text: package consists of: 755 RISC processor Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 * This , Core Frequency/ L2 Cache Frequency (300MHz/ 150MHz, 350MHz/175MHz) Footprint compatible with , www.wedc.com White Electronic Designs WED3C7558M-XBX FIGURE 3 ­ BLOCK DIAGRAM, L2 INTERCONNECT SSRAM , # ADV# DQb L2pin_DATA DQd L2DP0-3 DP0-3 L2 CLK_OUT A L2WE# L2CE# L20VCC U1 , # G# DP0-3 L2DP4-7 ZZ L2ZZ FIGURE 4 ­ BLOCK DIAGRAM, L2 INTERCONNECT TDI 755 STDI


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PDF WED3C7558M-XBX WED3C7558M-XBX 755/SSRAM 128Kx72 350MHz/175MHz 300MHz/150MHz MPC755 WED3C750A8M-200BX e7 adn
2004 - 7410E

Abstract: WED3C7410E16M-XBHX WED3C7410E16M-XBX WED3C750A8M-200BX WED3C7558M-XBX 90Pb10Sn block diagram of automatic flush system
Text: 2MB SSRAM L2 cache, configured as 256Kx72 21mmx25mm, 255 HiTCETM Ball Grid Array (CBGA , , high-bandwidth MPX bus interface Maximum L2 Cache frequency = 200MHz HiTCETM interposer for TCE , 2004 Rev. 0 2 128-Bit SSRAM Reservation Station 64- 32-Bit L2 Data Bus 32-Bit + L2PMCR L2CR L2 Tags 64-Bit Data Bus 32-Bit Address Bus L2 Data Transaction Queue L2 Controller . . GPR File 6 Rename Buffers Vector Touch Queue . . L2 Castout L2 Miss


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PDF WED3C7410E16M-XBHX 7410E WED3C7410E16M-XBHX 7410E/SSRAM 400MHz 450MHz 16Mbits 200MHz WED3C7410E16M-XBX WED3C750A8M-200BX WED3C7558M-XBX 90Pb10Sn block diagram of automatic flush system
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