The Datasheet Archive

25-ns datasheet (24)

Part ECAD Model Manufacturer Description Type PDF
25NS10 25NS10 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS100 25NS100 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS120 25NS120 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS140 25NS140 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS160 25NS160 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS20 25NS20 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS40 25NS40 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS60 25NS60 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NS80 25NS80 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NSEV22M6.3X5.5 25NSEV22M6.3X5.5 ECAD Model Rubycon Capacitors - Aluminum Electrolytic Capacitors - CAP ALUM 22UF 20% 25V SMD Original PDF
25NSEV33M4X55 25NSEV33M4X55 ECAD Model Rubycon Miniature Aluminum Electrolytic Capacitor Original PDF
25NSEV4R7M5X5.5 25NSEV4R7M5X5.5 ECAD Model Rubycon Capacitors - Aluminum Electrolytic Capacitors - CAP ALUM 4.7UF 20% 25V SMD Original PDF
25NSGG 25NSGG ECAD Model Altech Fuse 25A 415V BRITISH Original PDF
25NSKV33M4X55 25NSKV33M4X55 ECAD Model Rubycon Miniature Aluminum Electrolytic Capacitor Original PDF
25NSR10 25NSR10 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NSR100 25NSR100 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NSR120 25NSR120 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NSR140 25NSR140 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NSR160 25NSR160 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF
25NSR20 25NSR20 ECAD Model Naina Semiconductor Rectifier Diode, Standard Rectifier Diode, Current IF=25A Original PDF

25-ns Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1989 - j6916

Abstract: idt7132 CY7C136-55JC cy7c136 7C13 CY7C132 CY7C146 c1322 C13220 cy7c146-35jc
Text: and 25-ns version available in PQFP and PLCC packages only. 4. Shaded area contains preliminary , High-speed access: 15 ns · Low operating power: ICC = 90 mA (max.) · Fully asynchronous operation · , A3R A4R A5R A6R A7R A8R A9R NC I/O7R C132-4 Selection Guide Maximum Access Time ( ns , INT R2 347 GND 10% 90% 10% 90% < 5 ns < 5 ns ] Switching Characteristics , tOHA Data Hold from Address Change 25 15 0 30 25 0 ns 30 0 ns ns tACE


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PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) j6916 idt7132 CY7C136-55JC cy7c136 7C13 CY7C132 CY7C146 c1322 C13220 cy7c146-35jc
1995 - schematic 80386

Abstract: e174 ALS6311 80386 microprocessor PAL20R4D AN619 DP8421A C1995 DP8420A DP8422A
Text: for READ WRITE tRAH 15 ns and tASC 0 ns RAS and CAS Configuration Refresh Clock Divider Refresh , tAA I Timing Calculation for Design 1 25 MHz tCP e 40 ns with light load $400b ADS Asserted Setup to CLK tCP b PAL20R4E CLK tp max b PAL20R4E tp max e 40 ns b 7 ns b 8 ns e 25 ns ( 25 MHz , Decoder tp max e 80 ns a 4 ns a 6 ns b 21 ns b 9 ns e 40 ns ( 25 MHz) $416 AREQ Negated to ADS Asserted 2 tCP a PAL20R6E CLK tp min a Skew of CLK2 and CLK min b 6 Address Valid b HSA tp max e 80 ns


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PDF DP8422A DP8420A 386PAL1 20-3A schematic 80386 e174 ALS6311 80386 microprocessor PAL20R4D AN619 DP8421A C1995
uPD70280

Abstract: No abstract text available
Text: 62.5 tCYCK/2-15 tCYCK/2-15 Conditions MIN. 31.25 12 12 /¿PD70280 M AX. DC Units ns ns ns © 0 © (i) 5 5 DC ns ns ns ns ns © © © © © 15 15 20 DC ns ns ns ns ns ns © © © © © © © © 15 15 20 DC ns ns ns ns ns ns © © © © © © 25 25 ns ns ns ns ® © © © © © © © 30 25 ns ns ns 25 ns ns 40 35 25 ns ns ns R e m a rk s : Figures in the sym bol column , bol Conditions MIN. ¿¿PD70280 M AX. 25 25 25 25 Units ns ns ns ns ns ns ns ns ns


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PDF uPD70280 PD70280 MA0-MA10 ADO-AD15 D0-D15
2Kx8 Dual-Port Static RAM

Abstract: idt7132 CY7C132 CY7C136 CY7C146
Text: contains preliminary information. Notes: 3. 15 and 25-ns version available in PQFP and PLCC packages only , ns • Low operating power: lcc = 110 mA (max.) • Fully asynchronous operation • Automatic , 7C142-45 7C146-45 7C132-55 7C136-55 7C142-55 7C146-55 Maximum Access Time ( ns ) 15 25 30 35 45 55 Maximum , EQUIVALENT 3.0V ALL INPUT PULSES OUTPUTo- 250Í2 —WW— -0 1.4V GND jt 90% 1 o°/oY < 5 ns ■90% 10% 5 ns Switching Characteristics Over the Operating Range16'11] Parameter Description


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PDF 65-micron CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) 2Kx8 Dual-Port Static RAM idt7132 CY7C132 CY7C136 CY7C146
1989 - j6916

Abstract: 7C13 CY7C132 CY7C136 CY7C146 C13220 CY7C136-55NC Master Selection Guide
Text: contains preliminary information. Notes: 3. 15 and 25-ns version available in PQFP and PLCC packages only , High-speed access: 15 ns · Low operating power: ICC = 110 mA (max.) · Fully asynchronous operation · , A3R A4R A5R A6R A7R A8R A9R NC I/O7R C132-4 Selection Guide Maximum Access Time ( ns , GND 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over the Operating , Address Change 25 15 0 30 25 0 ns 30 0 ns ns tACE CE LOW to Data Valid


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PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) j6916 7C13 CY7C132 CY7C136 CY7C146 C13220 CY7C136-55NC Master Selection Guide
1989 - j6916

Abstract: idt7132 CY7C132 CY7C136 CY7C146 C1328 C1329
Text: and 25-ns version available in PQFP and PLCC packages only. 4. 2 TA is the "instant on" case , 2K x 8 organization · 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low , Guide Maximum Access Time ( ns ) Maximum Operating Com'l/Ind Current (mA) Maximum Operating , BUSY OR INT GND 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over , Data Hold from Address Change tACE tDOE CE LOW to Data Valid 15 0 ns ns 25 30


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PDF Y7C136 CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin j6916 idt7132 CY7C132 CY7C136 CY7C146 C1328 C1329
2001 - CY7C132

Abstract: CY7C136 CY7C146 2Kx8 Dual-Port Static RAM C132-10 CY7C136-55JC
Text: Outputs (LOW) .20 mA Notes: 3. 15 and 25-ns version available in PQFP and , 2K x 8 organization · 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low , 5L C132-4 Selection Guide Maximum Access Time ( ns ) Maximum Operating Com'l/Ind Current , INT GND 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over the , from Address Change tACE tDOE 15 0 25 0 ns 30 0 ns ns 15 25 30 ns


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PDF 32/CY7C136 CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132 CY7C136 CY7C146 2Kx8 Dual-Port Static RAM C132-10 CY7C136-55JC
5200 CY7C131 1K x 8 Dual-Port Static RAM

Abstract: CY7C130 CY7C131 CY7C140 CY7C141
Text: into Outputs (LOW).20 mA Notes: 3. 15 and 25-ns version available only in , €¢ High-speed access: 15 ns • Low operating power: lcc = 110 mA (max.) • Fully asynchronous operation â , 7C131-45 7C140-45 7C141-45 7C130-55 7C131-55 7C140-55 7C141-55 Maximum Access Time ( ns ) 15 25 30 35 45 55 , (CY7C130/CY7C131 ONLY) % 10% 90% < 5 ns - C130-6 <5ns Switching Characteristics Over the Operating , Cycle Time 15 25 30 ns *AA Address to Data Valid[12] 15 : 25 30 ns toHA Data Hold from Address


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PDF 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin IDT7130/IDT7140 5200 CY7C131 1K x 8 Dual-Port Static RAM CY7C130 CY7C131 CY7C140 CY7C141
1989 - CY7C130

Abstract: CY7C131 CY7C140 CY7C141
Text: Outputs (LOW) . 20 mA Notes: 3. 15 and 25-ns version available only in PLCC , organization · 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low operating power , 170 170 120 45 45 35 65 65 45 [3] Maximum Access Time ( ns ) Maximum , 281 BUSY OR INT 3.0V GND 10% 90% 10% 90% C130-6 5ns 5 ns Switching , ns ns ns 15 0 25 ns ns 15 15 ns ns 30 15 10 CE HIGH to Power-Down


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PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron CY7C130/CY7C131 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin CY7C130 CY7C131 CY7C140 CY7C141
2005 - CY7C132

Abstract: CY7C136 CY7C146
Text: 45 Shaded areas contain preliminary information. Note: 3. 15 and 25-ns version available in PQFP , : 15 ns · Low operating power: ICC = 110 mA (max.) · Fully asynchronous operation · Automatic , ns Maximum Access Time 15 25 30 35 45 Maximum Operating Current Com'l/Ind 190 , 281 BUSY OR INT 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over , CE LOW to Low tHZCE tPU CE LOW to Power-Up[9] tPD CE HIGH to 0 3 20 15 ns


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PDF CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136/CY7C142 CY7C146 CY7C132/ CY7C136 16-bit CY7C132
2004 - CY7C132-55PI

Abstract: CY7C136-55NC 128959
Text: preliminary information. Note: 3. 15 and 25-ns version available in PQFP and PLCC packages only. 7C132-30 , -micron CMOS for optimum speed/power · High-speed access: 15 ns · Low operating power: ICC = 110 mA (max.) · , 7C136-55 7C142-55 7C146-55 55 110 120 35 45 Unit ns mA mA mA 15 190 75 25 170 65 Document # , (CY7C132/CY7C136 Only) ALL INPUT PULSES 10% 90% 90% 10% < 5 ns OUTPUT 250 1.4V GND < 5 ns , 15 0 15 0 30 25 25 2 0 25 15 0 15 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data CE


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PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) CY7C132-55PI CY7C136-55NC 128959
2001 - C1303

Abstract: CY7C131 CY7C130 CY7C140 CY7C141
Text: . 15 and 25-ns version available only in PLCC/PQFP packages. 4. TA is the "instant on" case , 1K x 8 organization · 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low , [3] Maximum Access Time ( ns ) Maximum Operating Current (mA) Com'l/Ind Maximum Standby , -6 5ns 5 ns Switching Characteristics Over the Operating Range[5,10] [3] 7C131-15 7C141-15 , Power-Up tPD WRITE CYCLE 0 0 3 5 10 0 20 3 15 5 0 15 ns ns ns 15


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PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron CY7C130/CY7C131 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin C1303 CY7C131 CY7C130 CY7C140 CY7C141
Not Available

Abstract: No abstract text available
Text: 20 mA Notes: 3. 4. 5. 15 and 25-ns version available only in PLCC /PQ FP packages. Shaded , High-speed access: 15 ns Low operating power: lcc = 90 mA (max.) Fully asynchronous operation Automatic , Selection Guide 7C131-15I3'4] 7C131-25[3] 7C141-15 7C141-25 Maximum Access Time ( ns ) 7C130-30 , < 5 ns - Switching Characteristics Over the Operating Range16’11] 7 C I 3 I - I 5 !34] 7C141-15 , ns 30 0 ns ns *ACE ÜE LOW to Data Valid!12] 15 25 30 ns tDOE ÖE LOW


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PDF 130/C 140/C 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin
1989 - C1303

Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7c130 CY7C131-35JC C1307
Text: Outputs (LOW) . 20 mA Notes: 3. 15 and 25-ns version available only in PLCC , access: 15 ns · Low operating power: ICC = 110 mA (max.) · Fully asynchronous operation · Automatic , 7C131-15[3,4] 7C131-25[3] 7C141-15 7C141-25 Maximum Access Time ( ns ) 7C130-30 7C131-30 7C140-30 , 281 BUSY OR INT R2 347 3.0V GND 10% 90% 10% 90% C130-6 5ns 5 ns , to Data tOHA Data Hold from Address Change 25 15 0 30 25 0 ns 30 0 ns


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PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron CY7C130/CY7C131 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin C1303 CY7C130 CY7C131 CY7C140 CY7C141 7c130 CY7C131-35JC C1307
2005 - 7C131

Abstract: TwB 75 CY7C131-15JXI 1K x 4 static ram ttl CY7C141 7C130 CY7C130 CY7C131 CY7C140 7c130-55
Text: preliminary information. Note: 3. 15 and 25-ns version available only in PLCC/PQFP packages. Document # , : 15 ns · Low operating power: ICC = 110 mA (max.) · Fully asynchronous operation · Automatic , Time 15 25 30 35 45 55 ns Maximum Operating Com'l/Ind Current Military 190 , ONLY) ALL INPUT PULSES 10% 5 ns 90% 90% 10% 5ns Page 4 of 19 CY7C130/CY7C131 , 30 0 ns ns 15 25 30 ns 10 15 20 ns OE LOW to Data Valid Z[9, 13


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PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131/CY7C140 CY7C141 CY7C130/ CY7C131 CY7C140/CY7C141 16-bit CY7C130/CY7C131/CY7C140/CY7C141 52-pin 7C131 TwB 75 CY7C131-15JXI 1K x 4 static ram ttl 7C130 CY7C130 CY7C140 7c130-55
2004 - Not Available

Abstract: No abstract text available
Text: Shaded area contains preliminary information. Note: 3. 15 and 25-ns version available in PQFP and PLCC , x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns â , 7C132-45 7C136-45 7C142-45 7C146-45 7C132-55 7C136-55 7C142-55 7C146-55 Unit 55 ns , OR INT GND 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over the , to Data tOHA Data Hold from Address Change 25 15 0 30 25 0 ns 30 0 ns


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PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142)
2003 - CY7C136-55NI

Abstract: CY7C146 idt7132 CY7C132 CY7C136 PC TO IDT7132 CY7C136-55NC
Text: 110 120 35 45 Unit ns mA mA mA Shaded area contains preliminary information. Note: 3. 15 and 25-ns version available in PQFP and PLCC packages only. Document #: 38-06031 Rev. *A , organization · 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low operating power , INT GND 10% 90% 10% 90% < 5 ns < 5 ns Switching Characteristics Over the , ns tDOE OE LOW to Data Valid[11] 10 15 20 ns OE LOW to Low Z[9, 12] OE


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PDF CY7C132/CY7C136 CY7C142/CY7C146 65-micron CY7C132/CY7C136 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) CY7C136-55NI CY7C146 idt7132 CY7C132 CY7C136 PC TO IDT7132 CY7C136-55NC
893Q

Abstract: CY7C131-55JI bit-slice t913 CY7C1312
Text: and 25-ns version available only in PLCC/PQFP packages. Shaded area contains preliminary information , 0.65-micron CMOS for optimum speed/power · High-speed access: 15 ns · Low operating power: lcc = 90 mA , 7C131-15E34] 7C 141-15 Maximum Access Time ( ns ) Maximum Operating Current (mA) Maximum Standby Current (mA , ) 10 % . V 90% s 90% \ L 10% <5ns < 5 ns - Sw itching C haracteristics Over the , 25 ns ns ns ns ns ns ns ns ns ns ns *HZOE t|_ZCE ÏHZCE tpu tpD W RITE C Y C L E ^ tw c ^SCE


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PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron Y7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin 893Q CY7C131-55JI bit-slice t913 CY7C1312
2004 - Not Available

Abstract: No abstract text available
Text: information. Notes: 3. 15 and 25-ns version available only in PLCC/PQFP packages. Document #: 38-06002 , x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns â , 7C131-30 7C140-30 7C141-30 Maximum Access Time ( ns ) 15 25 30 35 45 55 Maximum , . *B 1.40V 281Ω 3.0V GND 10% ≤ 5 ns 90% 90% 10% C130-6 ≤5ns Page , Power-Up[9] CE HIGH to 0 0 10 ns ns 15 5 15 0 15 ns 20 15 10 0 ns


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PDF CY7C130/CY7C131 CY7C140/CY7C141 65-micron CY7C130/CY7C131 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin
CY7C136

Abstract: CY7C132 CY7C146 2Kx8 Dual-Port Static RAM z1013 CY7C132-55PI CY7C136-55NC
Text: Military 65 65 45 Shaded area contains preliminary information. Notes: 3. 15 and 25-ns version available , access: 15 ns • Low operating power: lcc = 110 mA (max.) • Fully asynchronous operation • Automatic , 7C146-35 7C132-45 7C136-45 7C142-45 7C146-45 7C132-55 7C136-55 7C142-55 7C146-55 Maximum Access Time ( ns , EQUIVALENT 3.0V ALL INPUT PULSES OUTPUTo- 250Í2 —WW— -0 1.4V GND Je 90% 1 o°/oY < 5 ns ■90% 10% 5 ns Switching Characteristics Over the Operating Range16'11] Parameter Description 7C136-15[3'4


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PDF 65-micron CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) CY7C136 CY7C132 CY7C146 2Kx8 Dual-Port Static RAM z1013 CY7C132-55PI CY7C136-55NC
3246A

Abstract: No abstract text available
Text: Output Current into Outputs (LO W ).20 mA Notes: 3. 4. 15 and 25-ns , access: 15 ns Low operating power: lcc = 110 mA (max.) Fully asynchronous operation Automatic power-down , 3 1 7C141-15 Maximum Access Time ( ns ) Maximum Operating Current (mA) Maximum Standby Current (mA , 7C131-30 7C140-30 7C141-30 Min. 30 I Max. Unit Ó ns 30 0 30 20 3 15 5 15 0 25 30 25 25 2 0 25 15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 0 ns ns Description Read Cycle Tims Address to


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PDF 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin IDT713CVIDT7140 3246A
Not Available

Abstract: No abstract text available
Text: and 25-ns version available only in PLCC /PQ FP packages. Shaded area contains prelim inary inform , optimum speed/power High-speed access: 15 ns Low operating power: lcc = 110 mA (max.) Fully asynchronous , 7C130-55 7C131-55 7C140-55 7C141-55 55 110 120 35 45 7C131-15I3'4] 7C141-15 Maximum Access Time ( ns , 15 15 Description Min. Max. 25 25 0 25 15 3 15 5 15 0 25 30 30 0 30 20 3 15 5 15 0 25 ns ns ns ns ns ns ns ns ns ns ns CE HIGH to Power-Downi9] tpD WRITE CYCLE!15] %c tsCE *AW ^HA tsA tpWE


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PDF 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin IDT7130/IDT7140
2008 - Z912

Abstract: CY7C136-35JI CY7C136-55NC
Text: 45 7C132-45 7C136-45 7C142-45 7C146-45 45 120 45 7C132-55 7C136-55 Unit 7C142-55 7C146-55 55 ns 110 mA 35 mA Note 3. 15 and 25-ns version available in PQFP and PLCC packages only. Document # , memory location 2K x 8 organization 0.65-micron CMOS for optimum speed and power High speed access: 15 ns , ) ALL INPUT PULSES 90% 90% 10% < 5 ns [5, 10] OUTPUT < 5 ns Switching Characteristics Over the , 15 10 3 10 3 10 0 15 15 12 12 2 0 12 10 0 10 0 ns 30 ns ns 30 20 ns ns ns 15 ns ns 15 ns ns 25 ns


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PDF CY7C142/CY7C146, CY7C132/CY7C136 CY7C132/CY7C136/CY7C142 CY7C146 CY7C132/ CY7C136 CY7C142/CY7C146 16-bit Z912 CY7C136-35JI CY7C136-55NC
Zl14

Abstract: C1306 cy7c130-55pc CY7C130 CY7C131 CY7C140 CY7C141 C1303
Text: into Outputs (LOW).20 mA Notes: 3. 15 and 25-ns version available only in , access: 15 ns • Low operating power: lcc = 110 mA (max.) • Fully asynchronous operation • Automatic , 7C141-35 7C130-45 7C131-45 7C140-45 7C141-45 7C130-55 7C131-55 7C140-55 7C141-55 Maximum Access Time ( ns , BUSY Output Load ALL INPUT PULSES (CY7C130/CY7C131 ONLY) % 10% 90% < 5 ns - C130-6 <5ns Switching , tRC Read Cycle Time 15 25 30 ns *AA Address to Data Valid[12] 15 : 25 30 ns toHA Data Hold from


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PDF 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin IDT7130/IDT7140 Zl14 C1306 cy7c130-55pc CY7C130 CY7C131 CY7C140 CY7C141 C1303
sv 281

Abstract: No abstract text available
Text: Into Outputs (LOW).20 mA N otes: 3. 15 and 25-ns version available in , ns · Low operating power: lcc = 110 mA (max.) · Fully asynchronous operation · Automatic power-down · , 7C132-55 7C136-55 7C142-55 7C146-55 55 110 120 35 45 Maximum Access Time ( ns ) Maximum Operating Com'l , . BUSY and tfJT p* ns only. Duration of the short circuit should not exceed 30 seconds. A t f=fMAx , 250C2 OUTPUT» - o 1 .4V GND ' A L L IN P U T P U L S E S 10%J f jÇ 9 0 % < .5 ns - Switching


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PDF 65-micron CY7C132/CY7C136 CY7C142/CY7C146 CY7C132/CY7C136; 52-pin 48-pin CY7C132/142) sv 281
Supplyframe Tracking Pixel