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Part Manufacturer Description Datasheet Download Buy Part
LTC2930CDD#PBF Linear Technology LTC2930 - Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C
LTC2930HDD#PBF Linear Technology LTC2930 - Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2930CDD#TRPBF Linear Technology LTC2930 - Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C
LTC2930HDD#TRPBF Linear Technology LTC2930 - Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2930IDD#PBF Linear Technology LTC2930 - Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
LTC2930IDD#TRPBF Linear Technology LTC2930 - Configurable Six Supply Monitor with Adjustable Reset Timer, Manual Reset; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C

24c02 wp reset Datasheets Context Search

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24c02 wp

Abstract: 24C16 application 24c02 wp reset 24c02 eeprom circuit diagram 24C02 24c16 wp 24C16 eeprom 24c08 24C04 wp 24C04
Text: negative edge clock data out of each device. WRITE PROTECT ( WP ): The 24C02 / 24C04/ 24C08/ 24C16 has a , Protect WP Pin Status At VCC Part of the Array Protected 24C02 Full (2K) Array At GND , 24C02 / 24C04 / 24C08 / 24C16 Features ¡Wide Voltage Operation ¡1 MHz (5V), 400 kHz (1.8V , : - 24C02 , 256 X 8 (2K bits) - 24C04, 512 X 8 (4K bits) - 24C08, 1024 X 8 (8K bits) - Endurance , General Description The 24C02 / 24C04/ 24C08/ 24C16 provides 2048/4096/8192/16384 bits of serial


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PDF 24C02 24C04 24C08 24C16 16-byte 24C02, 24C04, 24C08, 24C16, 24c02 wp 24C16 application 24c02 wp reset 24c02 eeprom circuit diagram 24c16 wp 24C16 eeprom 24c08 24C04 wp
24c02 wp

Abstract: 24c02 wp reset IC 24C02 memory 24c02 24C02 do ic 24C02 free eeprom 24c02 24c01 wp how to reset 24C02 24C01
Text: care' bit. POWER ON RESET : The Turbo IC 24C01/ 24C02 has a Power On Reset circuit (POR) to prevent , Turbo IC, Inc. 24C01/ 24C02 PRODUCT INTRODUCTION CMOS I²C 2-WIRE BUS 1K/2K ELECTRICALLY , / 24C02 is a serial 1K/2K EEPROM fabricated with Turbo's proprietary, high reliability, high performance , applications. The Turbo IC 24C01/ 24C02 uses the I²C addressing protocol and 2-wire serial interface which , faster 8-byte page write. The Turbo IC 24C01/ 24C02 is assembled in either a 8-pin PDIP or 8-pin SOIC


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PDF 24C01/24C02 24C01/24C02 24c02 wp 24c02 wp reset IC 24C02 memory 24c02 24C02 do ic 24C02 free eeprom 24c02 24c01 wp how to reset 24C02 24C01
24c02 wp

Abstract: 24c02 wp reset IC 24C02 do ic 24C02 free 24C01 how to reset 24C02 24C02 24C02 line TU24C02CS3 memory 24c02
Text: care' bit. POWER ON RESET : The Turbo IC 24C01/ 24C02 has a Power On Reset circuit (POR) to prevent , Turbo IC, Inc. 24C01/ 24C02 PRODUCT INTRODUCTION CMOS I²C 2-WIRE BUS 1K/2K ELECTRICALLY , / 24C02 is a serial 1K/2K EEPROM fabricated with Turbo's proprietary, high reliability, high performance , applications. The Turbo IC 24C01/ 24C02 uses the I²C addressing protocol and 2-wire serial interface which , faster 8-byte page write. The Turbo IC 24C01/ 24C02 is assembled in either a 8-pin PDIP or 8-pin SOIC


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PDF 24C01/24C02 24C01/24C02 24c02 wp 24c02 wp reset IC 24C02 do ic 24C02 free 24C01 how to reset 24C02 24C02 24C02 line TU24C02CS3 memory 24c02
24c02 wp

Abstract: 24c02 wp reset IC 24C02 24C02 24C01 how to reset 24C02 memory 24c02 24c02 eeprom eeprom 24c02 24C01/24C02
Text: care' bit. POWER ON RESET : The Turbo IC 24C01/ 24C02 has a Power On Reset circuit (POR) to prevent , Turbo IC, Inc. 24C01/ 24C02 PRODUCT INTRODUCTION CMOS I²C 2-WIRE BUS 1K/2K ELECTRICALLY , / 24C02 is a serial 1K/2K EEPROM fabricated with Turbo's proprietary, high reliability, high performance , applications. The Turbo IC 24C01/ 24C02 uses the I²C addressing protocol and 2-wire serial interface which , faster 8-byte page write. The Turbo IC 24C01/ 24C02 is assembled in either a 8-pin PDIP or 8-pin SOIC


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PDF 24C01/24C02 24C01/24C02 24c02 wp 24c02 wp reset IC 24C02 24C02 24C01 how to reset 24C02 memory 24c02 24c02 eeprom eeprom 24c02
2006 - csi 24c02

Abstract: CSI 24C08 CSI 24C04 24c16 csi 24C04 CSI 24C16 example code application 24C02 csi csi 24c16 24c16n 24c02 wp
Text: / A0 / A0 1 8 VCC NC / NC / A1 / A1 / A1 2 7 WP NC / A2 / A2 / A2 / A2 3 6 SCL VSS 4 5 SDA SCL 1 VSS 2 SDA 3 5 WP 4 VCC SCL A2, A1, A0 CAT24Cxx SDA WP For the location of Pin 1, please consult the corresponding , Input WP Write Protect Input VCC Power Supply VSS Ground NC VSS Device , CIN(3) Input Capacitance (other pins) VIN = 0 V 6 pF IWP(5) WP Input Current VIN


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PDF CAT24C01/02/04/08/16 16-Kb CAT24C01/02/04/08/16 16-Byte csi 24c02 CSI 24C08 CSI 24C04 24c16 csi 24C04 CSI 24C16 example code application 24C02 csi csi 24c16 24c16n 24c02 wp
2005 - 24LC02

Abstract: No abstract text available
Text: data. Pin #6 is the serial clock (SCL) input pin. Pin #7 is the write protect ( WP ) pin used to protect , power applications. VCC WP SCL SDA A0 A1 A2 GND 8 pin SOIC 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8 pin PDIP PIN DESCRIPTION DEVICE ADDRESS (A0 & A1 & A2) A0, A1, and A2 are , . If the address input pin is left unconnected, it is interpreted as zero. WRITE PROTECT ( WP ) SERIAL , , WP is interpreted as zero. 深圳市科威創新元器件有限公司 電話:0755-83573495


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PDF 24LC01/24LC02 24LC01/24LC02 24LC02
2001 - 24C02W

Abstract: 24c02 wp 24c02 eeprom circuit diagram 24LC028 24lc02w 24LC016 24C02 program eeprom 24c02w 24c016 24C02 code example c
Text: unless WP is switched to VSS. The 24C02 /24LC02' s communication protocol uses CLOCK (SCL) and DATA I/O , PROTECTION Programming the upper half of the memory will not take place if the WP pin of the 24C02 /24LC02 is , Unlimited read cycles ² Durable and Reliable ² 2 wire I2C serial interface ² ² ² ² 24C02 7 or 3 24LC02 6 4 5 Dual-In-Line package A0 A1 A2 VSS 1 2 3 4 TSSOP 24C02 or 24LC02 8 7 6 5 VCC N.C. SCL SDA GENERAL DESCRIPTION The 24C02 /24LC02 is low cost,non-volatile,2048-bit serial EEPROM with


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PDF 24LC02 2048-Bits CP24C02 CP24LC02 24C02 24LC02 24C02W 24c02 wp 24c02 eeprom circuit diagram 24LC028 24lc02w 24LC016 program eeprom 24c02w 24c016 24C02 code example c
2001 - 24c02 wp reset

Abstract: 24c02 wp 1010S2 X4043S8I X4043S8 X4043M8I X4043M8 X4043 X24C02 X24C04
Text: WP SCL SDA Designers Notes (NC or Vcc or Vss) (NC or Vcc or Vss) Reset / open drain-can be , Xicor X24C04 + X24C02 Conversion Assistant Replace X24C04/ 24C02 with X4043/X4045 - As little as , allows write protection of sections of memory. Power on RESET (POR) (4043 active low, 4045 active high , Vss 1 2 3 4 8 7 6 5 8 Pin SOIC X4043/X4045 (or MSOP) NC NC Reset / Vss Vcc Test , select) A2 (slave address select) X4043/X4045 Function NC NC Reset / Reset (X4043 Reset / is open


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PDF X24C04 X24C02 X24C04/24C02 X4043/X4045 X24C02 X4043S8 X4043S8I X4043M8 24c02 wp reset 24c02 wp 1010S2 X4043M8I X4043 X24C04
2006 - CSI 24C08

Abstract: csi 24c02 CSI 24C04 24c02 wp reset 24c16 csi 24c16 wp csi 24c16 24C04 CSI 24C16 program csi 24C01
Text: VCC WP SCL SDA SCL VSS SDA 1 2 3 4 VCC 5 WP FUNCTIONAL SYMBOL VCC TSOT-23 (TD) SCL A2, A1, A0 WP CAT24Cxx SDA For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTIONS A0, A1, A2 SDA SCL WP VCC VSS NC Device Address Inputs Serial Data Input/Output , ) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V VIN = , ) Page Mode, VCC = 5 V, 25°C (5) When not driven, the WP pin is pulled down to GND internally. For


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PDF CAT24C01/02/04/08/16 16-Byte 16-Kb CAT24C01/02/04/08/16 CSI 24C08 csi 24c02 CSI 24C04 24c02 wp reset 24c16 csi 24c16 wp csi 24c16 24C04 CSI 24C16 program csi 24C01
24C02 wp st

Abstract: 24c02 wp 24C02 application notes Fairchild 24C02 24C02 24c02 eeprom circuit diagram 24c02 st 24C02 line 24c02 eeprom IC block diagram
Text: Protected) by connecting the WP pin to Vc c . This section of m em ory then becomes unalterable unless WP is , ), SO Package (M8), and TSSOP Package (MT8) AO_ _ A1 1 2 NM 24C 03 8 - Vcc - 7 - WP 6 - , Protect Power Supply SDA SCL WP o o < 2 N M 24C 02/03 Rev. D.2 w w w .fairchildsem i.com , Operating Tem perature N M 24C02 /03 NM 24C02E/03E NM 24C02V/03V Positive Power Supply NM 24C02 /03 NM 24C02L/03L N M 24C02 LZ/03 LZ 0°C to +70°C -40°C to +85°C -40°C to +125°C 4.5V to 5.5V 2.7V to 4.5V 2.7V to


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PDF NM24C02/03 24C03 24C02 wp st 24c02 wp 24C02 application notes Fairchild 24C02 24C02 24c02 eeprom circuit diagram 24c02 st 24C02 line 24c02 eeprom IC block diagram
24c02 wp

Abstract: 24c02 eeprom IC block diagram 24C028 IC 24C02 24C02 application notes 24c02 eeprom circuit diagram 24c02 m8
Text: Protected) by connecting the WP pin to Vc c . This section of m em ory then becomes unalterable unless WP is , Package (M8), and TSSOP Package (MT8) AO_ _ A1 1 2 NM 24C 03 8 - Vcc - WP - 7 A2 - V SS , Protect Power Supply SDA SCL WP o o < 2 w w w .fa irc h ild s e m i.c o m NM24C02/03 - , Package (N), SO Package (M8), and TSSOP Package (MT8) AO_ _ A1 1 2 NM 24C 03 8 - Vcc - WP - , input W rite Protect Power Supply SDA SCL WP o o < 4 w w w .fa irc h ild s e m i.c o m


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PDF NM24C02/03 2048-Bit 24C03 24c02 wp 24c02 eeprom IC block diagram 24C028 IC 24C02 24C02 application notes 24c02 eeprom circuit diagram 24c02 m8
2009 - 24c02 wp reset

Abstract: 24c16 wp 24c02 wp CAT24C16 CAT24C08 CAT24C04 CAT24C02 CAT24C01 948AL memory 24c02
Text: CASE 511AK MSOP 8 Z SUFFIX CASE 846AD PIN CONFIGURATIONS TSOT-23 SCL VSS 4 3 WP , /01 NC/NC/NC/A0/A0 1 8 VCC NC/NC/A1/A1/A1 2 7 WP NC/A2/A2/A2/A2 3 6 , Address Input SDA WP WP Power Supply Ground NC SDA Write Protect Input VSS , overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the , at GND or VCC 2 mA -0.5 0.3 x VCC V A0, A1, A2 and WP 0.7 x VCC VCC + 0.5


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PDF CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16 16-Kb CAT24C01/02/04/08/16 CAT24C01/D 24c02 wp reset 24c16 wp 24c02 wp CAT24C16 CAT24C08 CAT24C04 CAT24C02 CAT24C01 948AL memory 24c02
2009 - 24c02 wp reset

Abstract: 24C04
Text: 3 4 VCC 5 WP · · · · · · · · · · Supports Standard and Fast I2C Protocol 1.7 V to 5.5 V Supply , ) CAT24C16/08/04/02/01 NC/NC/NC/A0/A0 NC/NC/A1/A1/A1 NC/A2/A2/A2/A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA , Serial Clock Input Write Protect Input Power Supply Ground No Connect SCL A2, A1, A0 WP CAT24Cxx SDA SDA SCL WP VCC VSS NC VSS Figure 1. Functional Symbol ORDERING INFORMATION See detailed , overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the


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PDF CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16 16-Kb CAT24C01/02/04/08/16 CAT24C01/D 24c02 wp reset 24C04
Not Available

Abstract: No abstract text available
Text: upper half of the m em ory of the 24C03 can be disabled (Write Protected) by connecting the WP pin to Vc c . This section of m em ory then becomes unalterable unless WP is switched to Vss. ■l2C , €” 2 A1 — Vcc 7 — WP NM 24C 03 A2 — V SS 8 4 6 — SCL 5 — SDA D S 5 , < C O C O A0,A1 ,A2 Ground SDA Serial Data I/O SCL Serial Clock input WP W , perature Am bient O perating Tem perature NM 24C02 /03 NM 24C02E/03E NM 24C02V/03V -6 5 °C to


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PDF NM24C02/03 2048-Bit 500nA 24C03
2010 - 24c02 wp reset

Abstract: 24c16 wp CAT24C16 CAT24C02 program eeprom 24c04 6 CAT24C01 948AL CAT24C04 CAT24C08 memory 24c02
Text: CASE 511AK MSOP 8 Z SUFFIX CASE 846AD PIN CONFIGURATIONS TSOT-23 SCL VSS 4 3 WP , / 04 / 02 / 01 8 NC / NC / NC / A0 / A0 1 VCC NC / NC / A1 / A1 / A1 2 7 WP NC , A0, A1, A2 Function Device Address Input SDA WP WP Power Supply Ground NC SDA , for more than 20 ns. Voltage overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more , A0, A1, A2 and WP 0.7 x VCC VCC + 0.5 V SCL and SDA 0.7 x VCC 5.5 ISB Standby


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PDF CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16 16-Kb CAT24C01/02/04/08/16 CAT24C01/D 24c02 wp reset 24c16 wp CAT24C16 CAT24C02 program eeprom 24c04 6 CAT24C01 948AL CAT24C04 CAT24C08 memory 24c02
24C01

Abstract: 24C01 pin configuration 24c02 p Q67100-H3217 Q67100-H3218 Q67100-H3496 Q67100-H3543 Q67100-H3544 24c02d
Text: -8-3 - 40°C . + 125 °C 4.5 V.5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 - 40 "C . + 85 °C 4.5 V.,5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 - 40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 - 40 °C . + 85 °C 2.7 V.5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 -40 'C . + 85 °C 2.7 V.,5.5 V SLE 24C02 -D Q67100-H3220 P-DIP-8-4 - 40°C . + 125 °C 4.5 V.5.5 V SLE 24C02 -S Q67100-H3221 P-DSO-8-3 - 40°C . + 125 °C 4.5 V.5.5 V Other types are available on request


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PDF fl23Sbà 24C01/02 623SbDS 023SbD5 24C01 24C01 pin configuration 24c02 p Q67100-H3217 Q67100-H3218 Q67100-H3496 Q67100-H3543 Q67100-H3544 24c02d
1999 - Not Available

Abstract: No abstract text available
Text: 24C01-D-3, SLA 24C01-S-3, SLA 24C02 -D-3 and SLA 24C02 -S-3 deleted. 4 5 Voltage changed from , , 6 CS0, CS1 and CS2 were replaced by n.c. 5 6 WP = VCC protects the upper half entire , -8-2 – 40˚C … + 125 ˚C 2.7 V.5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-3 – 40 ˚C … + 85 ˚C 2.7 V.5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-2 – 40 ˚C … + 85 ˚C 2.7 V.5.5 V SLE 24C02 -D Q67100-H3220 P-DIP-8-3 – 40˚C … + 125 ˚C 2.7 V.5.5 V SLE 24C02


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PDF 24C01/02 IED02127 GPD05696 GPS05473
1999 - 24C01

Abstract: and/nrf 24c01
Text: programming time 5 ms for up to 8 bytes". SLA 24C01-D-3, SLA 24C01-S-3, SLA 24C02 -D-3 and SLA 24C02 , . CS0, CS1 and CS2 were replaced by n.c. WP = VCC protects the upper half entire memory. The paragraph , 24C01-D SLE 24C01-S SLA 24C02 -D SLA 24C02 -S SLE 24C02 -D SLE 24C02 -S Ordering Code Q67100-H3543 , -8-3 N.C. N.C. N.C. 1 2 3 4 8 7 6 5 IEP02515 P-DSO-8-2 V CC WP SCL SDA N.C. N.C. N.C. VSS 1 2 3 4 8 7 6 5 IEP02514 VCC WP SCL SDA VSS Figure 1 Pin Configuration (top view) Semiconductor


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PDF 24C01/02 24C01/02 IED02127 GPS05473 GPD05696 24C01 and/nrf 24c01
1997 - 24C01

Abstract: Q67100-H3538 Q67100-H3543 24c02 wp
Text: Version) Version) Subjects (major changes since last revision) 5 5 WP = VCC protects upper , SLE 24C01-S Q67100-H3492 P-DSO-8-3 ­ 40°C . + 125 °C 4.5 V.5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 ­ 40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 ­ 40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 ­ 40 °C . + 85 °C 2.7 V.5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 ­ 40 °C . + 85 °C 2.7 V.5.5 V


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PDF 24C01/02 IED02127 GPD05583 GPS09032 24C01 Q67100-H3538 Q67100-H3543 24c02 wp
Not Available

Abstract: No abstract text available
Text: + 125 °C 4.5 V.5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 - 40 "C . + 85 "C 4.5 V.,5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 - 40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 - 40 °C . + 85 ”C 2.7 V.,5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 - 40 "C . + 85 "C 2.7 V.,5.5 V SLE 24C02 -D Q67100-H3220 P-DIP-8-4 - 40°C . . + 125 "C 4.5 V.5.5 V SLE 24C02 -S Q67100-H3221 P-DSO-8-3 - 40°C . . + 125 °C 4.5 V.5.5 V


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PDF fl23Sb05 24C01/02 106cycles1 fl23Sfc05
Not Available

Abstract: No abstract text available
Text: Text was changed to ‘Typical programming time 5 ms for up to 8 bytes”. 5 5 WP = Vcc , 125°C 4.5 V.,5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 - 40 °C . +85 °C 4.5 V.5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 - 40 °C . +85 °C 4.5 V.,5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 - 40 °C . + 85 °C 2.7 V.5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 - 40 °C . + 85 °C 2.7 V.5.5 V SLE 24C02 -D Q67100-H3220 P-DIP-8-4 - 40°C . . +


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PDF 24C01/02 0535b05
1998 - 24C01-D

Abstract: 24C01 24C02 wp 24C01 6 24C01 pin configuration Q67100-H3538 Q67100-H3543 24C01 smd
Text: up to 8 bytes". 5 5 WP = VCC protects the upper half entire memory. 15 15 Figure 11 , 4.5 V.5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 ­ 40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 ­ 40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 ­ 40 °C . + 85 °C 2.7 V.5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 ­ 40 °C . + 85 °C 2.7 V.5.5 V SLE 24C02 -D Q67100-H3220 P-DIP-8-4 ­ 40°C . + 125 °C


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PDF 24C01/02 IED02127 GPD05583 GPS09032 24C01-D 24C01 24C02 wp 24C01 6 24C01 pin configuration Q67100-H3538 Q67100-H3543 24C01 smd
24C01 pin configuration

Abstract: 24c02 eeprom circuit diagram 24C01 MARKING 24C01 24C01 6 Q67100-H3544 Q67100-H3543 Q67100-H3496 Q67100-H3492 24c02 wp
Text: WP = vcc protects upper half entire memory 15 15 Figure 11: second command byte is a CSR and not CSW , .5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 -40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 -40 °C . + 85 °C 4.5 V.5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 -40 °C . + 85 °C 2.7 V.5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 -40 °C . + 85 °C 2.7 V.5.5 V SLE 24C02 -D Q67100-H3220 P-DIP-8-4 — 40°C . + 125 °C 4.5 V.5.5 V SLE 24C02 -S Q67100-H3221 P-DSO-8-3 — 40°C .


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PDF 24C01/02 128/256x8 24C01/02 199AX H-0-10 24C01 pin configuration 24c02 eeprom circuit diagram 24C01 MARKING 24C01 24C01 6 Q67100-H3544 Q67100-H3543 Q67100-H3496 Q67100-H3492 24c02 wp
Not Available

Abstract: No abstract text available
Text: ) Page (in current Version) Subjects (major changes since last revision) 5 5 WP = Vcc , .,5.5 V SLE 24C01-S Q67100-H3492 P-DSO-8-3 - 40°C . . + 125 °C 4.5 V.,5.5 V SLA 24C02 -D Q67100-H3539 P-DIP-8-4 - 4 0 °C . + 85 °C 4.5 V.,5.5 V SLA 24C02 -S Q67100-H3534 P-DSO-8-3 - 4 0 °C . + 85 °C 4.5 V.,5.5 V SLA 24C02 -D-3 Q67100-H3538 P-DIP-8-4 - 4 0 °C . + 85 °C 2.7 V.,5.5 V SLA 24C02 -S-3 Q67100-H3533 P-DSO-8-3 - 4 0 °C . + 85 °C 2.7 V


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PDF 24C01/02 128/256x8
2005 - csi 24C02WI

Abstract: 24C02LI csi 24c02li csi 24c02w 24c02w 24C02WI 24c02l 24c028 CSI24C02WI csi 24c02
Text: kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the , 4 8 7 6 5 VCC WP SCL SDA FUNCTIONAL SYMBOL VCC SCL A2, A1, A0 WP CAT24C02 SDA , , A2 SDA SCL WP VCC VSS Device Address Serial Data Serial Clock Write Protect Power Supply Ground , /O Pin Capacitance Input Capacitance (other pins) WP Input Low Impedance WP Input High Leakage , 4 4.7 0 0.25 1 0.3 4 0.1 5 1 Power-On Reset (POR) The CAT24C02 incorporates Power-On Reset (POR


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PDF CAT24C02 CAT24C02 16-byte csi 24C02WI 24C02LI csi 24c02li csi 24c02w 24c02w 24C02WI 24c02l 24c028 CSI24C02WI csi 24c02
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