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24bit Datasheets Context Search

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2001 - 97Pb3Sn

Abstract: omr 112 smd cod 62Sn-36Pb-2Ag MFI3 DSP56000 DSP56300 DSP56311 DSP56321 62Sn36Pb2Ag
Text: JTAG ID = $0180B01D Device ID (IDR) = $000321 JTAG ID = $0181501D Internal Memory 128 K × 24-bit on-chip SRAM 192 K × 24-bit on-chip SRAM Memory maps Memory map includes five switch options , memory 10 K × 24-bit 12 K × 24-bit SRAM access wait states Accesses as 100 MHz or less , Identification Register (IDR) is a 24-bit , read-only factory-programmed register that identifies DSP56300 family , Internal Memory Size The DSP56311 has a total of 128 K × 24-bit on-chip SRAM compared to a total of 192 K


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PDF DSP56311 DSP56321 DSP56321, DSP56300 DSP56000 EB365/D 97Pb3Sn omr 112 smd cod 62Sn-36Pb-2Ag MFI3 DSP56321 62Sn36Pb2Ag
2001 - 12 bit alu circuit design

Abstract: DSP56000 DSP56300 DSP56311 DSP56321 32 bit barrel shifter circuit diagram dab circuitry MSW-2
Text: Preview DSP56321 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56321, a member of the DSP56300 , shifter, 24-bit addressing, instruction cache, and Direct Memory Access (DMA) controller. The DSP56321 , Control 24-Bit Bootstrap ROM DSP56300 Core 18 Address 10 Control DDB Internal Data , fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit


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PDF DSP56321P/D DSP56321 24-BIT DSP56321, DSP56300 DSP56321 12 bit alu circuit design DSP56000 DSP56311 32 bit barrel shifter circuit diagram dab circuitry MSW-2
1997 - DSP56000 DATASHEET

Abstract: 4 bit barrel shifter circuit diagram free home theater circuit diagram barrel shifter block diagram DSP56000 DSP56300 DSP56303 DSP56307 8 BIT ALU design by cmos 4 bit barrel shifter circuit
Text: DSP56307 Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR Motorola developed the DSP56307, a , instruction engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit , EXTAL XTAL RESET PINIT/NMI YAB XAB PAB DAB Y Data RAM 24 K × 24 24-Bit DSP56300 Core , ) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter , 24-bit or 16-bit arithmetic support under software control Ð Program Control Unit (PCU) with


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PDF DSP56307P/D DSP56307 24-BIT DSP56307, DSP56300 DSP56307 DSP56000 DSP56000 DATASHEET 4 bit barrel shifter circuit diagram free home theater circuit diagram barrel shifter block diagram DSP56303 8 BIT ALU design by cmos 4 bit barrel shifter circuit
1997 - DSP56000 DATASHEET

Abstract: DSP56000 DSP56300 DSP56303 DSP56307 block diagram for barrel shifter AA136
Text: instruction engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit , XTAL RESET PINIT/NMI YAB XAB PAB DAB Y Data RAM 24 K × 24 24-Bit DSP56300 Core , Semiconductor, Inc. 24-BIT DIGITAL SIGNAL PROCESSOR Program Interrupt Controller PLL Program , parallel instruction set Ð Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit , stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support


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PDF DSP56307P/D DSP56307 DSP56307, DSP56300 DSP56307 DSP56000 24-bit DSP56000 DATASHEET DSP56303 block diagram for barrel shifter AA136
4 bit barrel shifter circuit diagram

Abstract: 32 bit barrel shifter circuit diagram design of 18 x 16 barrel shifter design of barrel shifter 18 x 16 ir5b
Text: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR DSP56307 Motorola developed the DSP56307, a , instruction engine (code compatible with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit , Logic Unit (Data ALU) with fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC), 56 , instructions, and 24-bit or 16-bit arithmetic support under software control - Program Control Unit (PCU) with , total - Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: 24 K x 24-bit


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PDF 24-BIT DSP56307 DSP56307, DSP56300 DSP56307 DSP56000 4 bit barrel shifter circuit diagram 32 bit barrel shifter circuit diagram design of 18 x 16 barrel shifter design of barrel shifter 18 x 16 ir5b
18 x 16 barrel shifter

Abstract: design of 18 x 16 barrel shifter block diagram for barrel shifter DSP56300
Text: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56303 is a member of the DSP56300 core family , External Address Bus Switch External Bus Interface 18 ADDRESS 24-Bit DSP56300 Core DDB YDB 13 , pipelined 24 x 24-bit parallel multiplier-accumulator 56-bit parallel barrel shifter 24-bit or 16 , disabled enabled Switch Mode disabled disabled enabled enabled Program RAM Size 4096 x 24-bit 3072 x 24-bit 2048 x 24-bit 1024 x 24-bit Instruction Cache Size 0 1024 x 24-bit 0 1024 x 24-bit X Data RAM Size 2048


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PDF DSP56303P/D DSP56303 24-BIT DSP56303 DSP56300 DSP56000 18 x 16 barrel shifter design of 18 x 16 barrel shifter block diagram for barrel shifter
2001 - Freescale process

Abstract: DSP56L307 EB344 DSP56300 DSP56307 DSP56311
Text: information specific to the DSP56311 Memory 64 K × 24-bit on-chip RAM 128 K × 24-bit on-chip RAM Internal Memory Block Size 256 × 24-bit words 1024 × 24-bit words 3 Voltage The DSP56311 and , Freescale Semiconductor 3 Memory The Device Identification register (IDR) is a 24-bit , read-only , information specific to the DSP56311. 11 Memory The DSP56311 has a total of 128 K × 24-bit on-chip RAM compared to the 64 K × 24-bit on-chip RAM of the DSP56307. In both devices, RAM is partitioned into


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PDF EB344 DSP56307 DSP56311 DSP56311 DSP56307, DSP56300 196-pin Freescale process DSP56L307 EB344
1999 - 32 bit barrel shifter circuit diagram

Abstract: DSP56311 4 bit barrel shifter circuit diagram barrel shifter block diagram DSP56000 DATASHEET DSP56000 motorola DSP56000 DSP56300 24-bit
Text: DSP56311 24-BIT DIGITAL SIGNAL PROCESSOR The Motorola DSP56311, a member of the DSP56300 core family of , with Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, Instruction Cache , 24-Bit DSP56300 Core Bootstrap ROM Clock Generator X Data RAM 48 K × 24 YM_EB , ­ Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel , parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control


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PDF DSP56311P/D DSP56311 24-BIT DSP56311, DSP56300 DSP56311 DSP56000 32 bit barrel shifter circuit diagram 4 bit barrel shifter circuit diagram barrel shifter block diagram DSP56000 DATASHEET DSP56000 motorola
2001 - DSP56000

Abstract: DSP56300 DSP56300FM DSP56311 DSP56311UM DSP56300 finite impulse response
Text: Freescale Semiconductor Product Brief DSP56311PB Rev. 3, 2/2005 DSP56311 24-Bit Digital , Data RAM 48 K × 24 bits 24-Bit DSP56300 Core Bootstrap ROM DDB YDB XDB PDB GDB , code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA , instruction set · Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel , parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control ·


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PDF DSP56311PB DSP56311 24-Bit 24-Bit DSP56300 DSP56000 DSP56300 DSP56300FM DSP56311 DSP56311UM DSP56300 finite impulse response
2001 - DSP56000

Abstract: DSP56300 DSP56311 DSP56321 97Pb3Sn
Text: Internal Memory 128 K × 24-bit on-chip SRAM 192 K × 24-bit on-chip SRAM Memory maps Memory map , default) EFCOP/Core shared 10 K × 24-bit memory 12 K × 24-bit SRAM access wait states , Identification Register Contents for DSP56311 and DSP56321 The device Identification Register (IDR) is a 24-bit , of 128 K × 24-bit on-chip SRAM compared to a total of 192 K × 24-bit on-chip SRAM in the DSP56321 , RAM Size* Instruction Cache (CE) Switch Mode (MS) MSW1 MSW0 32 K × 24-bit 0


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PDF DSP56311 DSP56321 DSP56321, DSP56300 DSP56000 EB365/D DSP56321 97Pb3Sn
2001 - 18 x 16 barrel shifter

Abstract: iir lms DSP56000 DSP56300 DSP56300FM DSP56L307 DSP56L307UM
Text: DSP56L307 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral , 24 bits 24-Bit DSP56300 Core Bootstrap ROM External Address Bus Switch External Bus , (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory , ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel , , and 24-bit or 16-bit arithmetic support under software control · Program control unit (PCU) with


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PDF DSP56L307PB DSP56L307 24-Bit 24-Bit DSP56300 DSP56L307 18 x 16 barrel shifter iir lms DSP56000 DSP56300 DSP56300FM DSP56L307UM
1996 - DSP56300

Abstract: DSP56000 DSP56304 ram expansion module RAM POWER DISTRIBUTION DIAGRAM 9216 ROM
Text: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR Motorola designed the ROM-based DSP56304 to support , Lock Loop (PLL), External Memory Interface (EMI), Data Arithmetic Logic Unit (Data ALU), 24-bit , 24-Bit DSP56300 Core Bootstrap ROM YM_EB ESSI Interface Program RAM 1024 × 24 , with the DSP56000 core ­ Highly parallel instruction set ­ Fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC) ­ 56-bit parallel barrel shifter ­ 24-bit or 16


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PDF DSP56304P/D DSP56304 24-BIT DSP56304 DSP56300 DSP56000 ram expansion module RAM POWER DISTRIBUTION DIAGRAM 9216 ROM
1999 - DSP56311

Abstract: DSP56000 DSP56300 DSP56307 DSP56L307 12000-13FFF
Text: specific to the DSP56311 Memory 64 K × 24-bit on-chip RAM 128 K × 24-bit on-chip RAM Internal Memory Block Size 3 JTAG and Device ID registers information specific to the DSP56307 256 × 24-bit words 1024 × 24-bit words Voltage The DSP56311 and DSP56307 are dual-voltage devices. The , Identification register (IDR) is a 24-bit , read-only factory-programmed register that identifies DSP56300 family , . 11 Memory The DSP56311 has a total of 128 K × 24-bit on-chip RAM compared to the 64 K × 24-bit


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PDF DSP56307 DSP56311 DSP56311 DSP56307, DSP56300 DSP56000 EB344/D DSP56L307 12000-13FFF
design of 18 x 16 barrel shifter

Abstract: 18 x 16 barrel shifter 4 bit barrel shifter block diagram block diagram for barrel shifter
Text: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56302 is a member of the DSP56300 core family , External Address Bus Switch External Bus Interface 18 ADD RESS 24-Bit DSP56300 Core DDB YDB 13 & , DSP56000 core Highly parallel instruction set Fully pipelined 24 x 24-bit parallel multiplier-accumulator 56-bit parallel barrel shifter 24-bit or 16-bit arithmetic support under software control Position , enabled Program RAM Size 20480 x 24-bit 19456 x 24-bit 25576 x 24-bit 24552 x 24-bit Instruction Cache


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PDF DSP56302P/D DSP56302 24-BIT DSP56302 DSP56300 DSP56000 design of 18 x 16 barrel shifter 18 x 16 barrel shifter 4 bit barrel shifter block diagram block diagram for barrel shifter
1996 - 8 BIT ALU design by cmos

Abstract: DSP56000 DSP56300 DSP56303 digital lock using PIC
Text: Conditional ALU instructions ­ · Fully pipelined 24 x 24-bit parallel multiplier-accumulator 24-bit , Switch Mode Program RAM Size Instruction Cache Size disabled disabled 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit disabled enabled 2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit enabled enabled 1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit · X Data RAM


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PDF DSP56303 DSP56300 DSP56000 56-bit 24-bit 16-bit DSP56303 DSP56300 8 BIT ALU design by cmos digital lock using PIC
Not Available

Abstract: No abstract text available
Text: , rev. 1.08, July 1993 Features: • Preloadable 24-bit Up/Down Counter ° Choice of two 20 , €¢ Divide-by-N • 24-Bit Comparitor Register • 4 Control Registers • Readable Status Register • 8 , applications. The 24-bit multi-mode counter, registers and logic enable a micro­ processor to track the , Master Control Register b> Input Control Register Output Control Register L_> 24-bit , (206) 696-2468): : ?[ 24-bit Comparitor (800) 736-0194) LS7166 DIP package Price: $3.90


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PDF 24-bit 20-pin 24-bit
1998 - MOTOROLA DSP563XX architecture

Abstract: CS4128 ssi RS-232 converter DSP563XX architecture CS4218 DSP56000 DSP56002 DSP56300 DSP56307 motorola 16M CMOS DRAM
Text: development. The 24-bit precision of the DSP56307 Digital Signal Processor (DSP) combined with the onboard 64K , Hardware · 24-bit DSP56307 Digital Signal Processor ­ High -Performance DSP56300 core Object , Logic Unit (ALU) · Fully pipelined 24-x 24-bit parallel multiplier-accumulator · 56-bit parallel barrel shifter · Conditional ALU instructions · 24-bit or 16-bit arithmetic support , Switch Mode MSW1 MSW0 16K × 24-bit 0 24K × 24-bit 24K × 24-bit disabled disabled 15K × 24-bit


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PDF DSP56307EVMP/D DSP56307EVM DSP56307EVM DSP56307 DSP56307EVM) MOTOROLA DSP563XX architecture CS4128 ssi RS-232 converter DSP563XX architecture CS4218 DSP56000 DSP56002 DSP56300 motorola 16M CMOS DRAM
1996 - XC56156FE60

Abstract: XC56004FJ50 XC56001AFC27 XC96002RC40 XC56004 XC96002RC33 xc56001 FIR CODE FOR 8051 IN ASSEMBLY LANGUAGE XC56L811BU40 xc56156
Text: offers a complete portfolio of 16- and 24-bit fixed point and 32-bit floating point DSPs. In addition , DSP56000-24-Bit Digital Signal Processors The DSP56000 family of 24-bit , fixed point, general purpose , compatibility with the 24-bit family into the 16-bit DSP56100 and 32-bit DSP96002 products helping to preserve our customer software investment. The DSP56000 family of HCMOS, 24-bit DSP devices consists of the , , control, and audio applications. The DSP56000 family's unique 24-bit architecture has made these products


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PDF DSP56100--16-Bit DSP56800--16-Bit DSP56000--24-Bit DSP56300--24-Bit DSP56600--16-Bit DSP96002--32-Bit DSP56ADC16--The DSP96000 DSP56000 DSP56KCCAJ XC56156FE60 XC56004FJ50 XC56001AFC27 XC96002RC40 XC56004 XC96002RC33 xc56001 FIR CODE FOR 8051 IN ASSEMBLY LANGUAGE XC56L811BU40 xc56156
2010 - MX25L25635E

Abstract: MX25L256 mx25l25635 mxic MX25L25 MXIC serial Flash macronix an053
Text: .2 . 2. Two Address Modes: 24-bit Address Mode and 32-bit Adress Mode , Flash Application in System Reset 1. Introduction MX25L25635E provides 24-bit and 32-bit address , will remain in 32-bit address mode and will not be able to boot by 24-bit addressing. This application note is designed specifically for those systems which can only be booted by 24-bit addressing but , solutions provided in this document, the Flash device can return to 24-bit addressing mode and boot


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PDF MX25L25635E 256Mb MX25L25635E 24-bit 32-bit MX25L256 mx25l25635 mxic MX25L25 MXIC serial Flash macronix an053
1999 - DSP56000 DATASHEET

Abstract: DSP56303UM 4 bit barrel shifter circuit diagram barrel shifter block diagram DSP56000 DSP56300 DSP56303
Text: : 24-BIT DIGITAL SIGNAL PROCESSOR 24-Bit DSP56300 Core Bootstrap ROM External Address Bus , compatible with the DSP56000 core ­ Highly parallel instruction set ­ Fully pipelined 24 x 24-bit parallel multiplier-accumulator ­ 56-bit parallel barrel shifter ­ 24-bit or 16-bit arithmetic , disabled 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit disabled enabled 2048 × 24-bit 0 3072 ×


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PDF DSP56303PB/D DSP56303 DSP56303 DSP56300 DSP56000 Office141 DSP56303P/D DSP56000 DATASHEET DSP56303UM 4 bit barrel shifter circuit diagram barrel shifter block diagram
1996 - DSP56000

Abstract: DSP56300 DSP56303 block diagram for barrel shifter
Text: Advance Information 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56303 is a member of the DSP56300 core family , Timer Program RAM 4096 × 24 or (3072 × 24 and Instruction Cache 1024 × 24) 24-Bit DSP56300 , instruction set ­ Fully pipelined 24 x 24-bit parallel multiplier-accumulator ­ 56-bit parallel barrel shifter ­ 24-bit or 16-bit arithmetic support under software control ­ Position , Size X Data RAM Size Y Data Ram Size disabled 4096 × 24-bit 0 2048 × 24-bit 2048


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PDF DSP56303P/D DSP56303 24-BIT DSP56303 DSP56300 DSP56000 block diagram for barrel shifter
2003 - Not Available

Abstract: No abstract text available
Text: is an LSI monolithic CMOS building block useful in motion control applications. The 24-bit , multiplication Ø Preloadable 24-bit up/down counter Ø Choice of two 20-pin packages: SOIC surface mount or DIP (300mil) Ø X1 or X2 or X4 resolution multiplier Ø Binary or BCD Ø Divide-by-N Ø 24-Bit , used to clock and steer the 24-bit Counter. It can be programmed to generate one clock once per , level on this pin will reset the 24-bit counter. When bit-4 is high, a low level on this pin will


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PDF LS7166 LS7166 24-bit PC7166,
DSP56300 finite impulse response

Abstract: iir filter diagrams real world applications of msp timer peripheral DSP56300
Text: Chapter 1 Overview This manual describes the DSP56311 24-bit digital signal processor (DSP), its , Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, instruction cache, and DMA , pipelined 24 24-bit parallel multiplier-accumulator s Bit field unit, comprising a 56-bit parallel , instructions s Software-controllable 24-bit , 48-bit, or 56-bit arithmetic support s Four 24-bit or , significant product:least significant product (EXT:MSP:LSP). The multiplier executes 24-bit 24-bit parallel


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PDF DSP56311 24-bit DSP56300 DSP56300FM/AD) DSP56311 DSP56311/D DSP56300 finite impulse response iir filter diagrams real world applications of msp timer peripheral
2001 - DSP56321

Abstract: 97Pb3Sn 97Pb DSP56300 DSP56311 EB365 62-SN
Text: 128 K × 24-bit on-chip SRAM 192 K × 24-bit on-chip SRAM Memory maps 9 Memory map includes , default) EFCOP/Core shared memory 10 10 K × 24-bit 12 K × 24-bit SRAM access wait states , DSP56311 and DSP56321 The device Identification Register (IDR) is a 24-bit , read-only factory-programmed , DSP56311 and DSP56321 8 Internal Memory Size The DSP56311 has a total of 128 K × 24-bit on-chip SRAM compared to a total of 192 K × 24-bit on-chip SRAM in the DSP56321. In both devices, SRAM is


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PDF EB365 DSP56311 DSP56321 DSP56321, DSP56300 DSP56321 97Pb3Sn 97Pb EB365 62-SN
2003 - Not Available

Abstract: No abstract text available
Text: is an LSI monolithic CMOS building block useful in motion control applications. The 24-bit , multiplication Ø Preloadable 24-bit up/down counter Ø Choice of two 20-pin packages: SOIC surface mount or DIP (300mil) Ø X1 or X2 or X4 resolution multiplier Ø Binary or BCD Ø Divide-by-N Ø 24-Bit , used to clock and steer the 24-bit Counter. It can be programmed to generate one clock once per , level on this pin will reset the 24-bit counter. When bit-4 is high, a low level on this pin will


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PDF LS7166 LS7166 24-bit PC7166,
Supplyframe Tracking Pixel