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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC1558CGN-3.3#TR Linear Technology LTC1558 - Backup Battery Controller with Programmable Output; Package: SSOP; Pins: 16; Temperature: Commercial
LTC1558CS8-5#TR Linear Technology LTC1558 - Backup Battery Controller with Programmable Output; Package: SO; Pins: 8; Temperature: Commercial
LTC1558CS-5#TRPBF Linear Technology LTC1558 - Backup Battery Controller with Programmable Output; Package: SO; Pins: 16; Temperature: Commercial
LTC1558CS-3.3#TRPBF Linear Technology LTC1558 - Backup Battery Controller with Programmable Output; Package: SO; Pins: 16; Temperature: Commercial
LT1031CMH Linear Technology IC 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 10 V, MBCY3, TO-5, 3 PIN, Voltage Reference
LTC1558CGN-5#TR Linear Technology LTC1558 - Backup Battery Controller with Programmable Output; Package: SSOP; Pins: 16; Temperature: Commercial

24 pin outputs decoder ic Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - AN97011

Abstract:
Text: APPLICATION NOTE Digital Video Decoder /Encoder Module System: ENCMOD03 + I²C Interfacing AN97011 Philips Semiconductors Digital Video Decoder /Encoder Module System: ENCMOD03 + I²C , rights. 2 Philips Semiconductors Digital Video Decoder /Encoder Module System: ENCMOD03 + I²C , Keywords Digital Video Encoder (DENC) SAA7120/21 Digital Video Decoder SAA7111(A), VIP, EVIP I²C Bus , Video Decoder /Encoder Module System: ENCMOD03 + I²C Interfacing Application Note AN97011


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PDF ENCMOD03 AN97011 AN97011 parallel i2C 74Ls05 DB15-VGA BS170 SMD BSS138 APPLICATION FOR LEVEL SHIFTER VGA DB15 BS170 bss138 y6 smd transistor a4h smd evip
1997 - 7803 regulator smd

Abstract:
Text: for one IC and some configurational parts. For interfacing a 26- pin and a 16- pin flat ribbon cable , , power and I²C-bus via 16- pin header. Depending on the assembled IC the data can be in CCIR 656 format , master ( pin CDIR low; JP13 closed) LLC and CREF are outputs . The pins RCV1 and RCV2 can be configured to , tables below. TABLE 6 Configuration of I²C-bus EEPROMs IC type Size Pin 1 Pin 2 Pin 3 Pin 7 A0: "0" , compatible (D1). The control lines are set either as inputs or outputs . The connector has the following pin


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PDF AN96055 ENCMOD02 7803 regulator smd PAL0012 saa7111 4pin xtal vga to cvbs converter video encoder mpeg D2523 TDA8709 AN96055 digital cvbs pattern
1998 - motorola mc1555

Abstract:
Text: ) Pin 18 (VCC = 20 V, VC = 30 V) 4 ns V ns V mA IC MOTOROLA ANALOG IC DEVICE , ) 7 MC33035 PIN FUNCTION DESCRIPTION Pin 1, 2, 24 Symbol Description BT, AT, CT , power source ground. 17 VCC This pin is the positive supply of the control IC . The controller , Bottom Drive Outputs is set by the voltage applied to this pin . The controller is operational over a , . In addition, the MC33035 has a 60°/120° select pin which configures the rotor position decoder for


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PDF MC33035/D MC33035 MC33035 motorola mc1555 home made bidirectional dc motor control circuit brushless motor mc33035 751E 1N5819 induction heating circuit diagram motorola MC1555 datasheet U01A MC33035-D
1996 - wiring diagram dc "speed controller" brushed

Abstract:
Text: Description 1, 2, 24 BT, AT, CT These three open collector Top Drive outputs are designed to drive , Output MOTOROLA ANALOG IC DEVICE DATA MC33035 Reference The on­chip 6.25 V regulator ( Pin 8 , Figures 24 and 25. The three totem pole bottom drive outputs (Pins 19, 20, 21) are particularly suited , Rotor Position Decoder 3 Q1 1 S S N Q2 Fwd/Rev 60°/120° Enable 24 22 7 , Q6 SA Sensor Inputs 60°/120° Select Pin Grounded SB SC Code AT Top Drive Outputs


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PDF MC33035/D MC33035 MC33035 wiring diagram dc "speed controller" brushed current sensing DC motor schematic diagram pwm based bidirectional dc motor speed sensor motor DC schematic diagram MOTOROLA brushless dc controller pwm based bidirectional dc motor speed control datasheet mc1555 schematic diagram brushless motor control MC1555 datasheet brushless dc motor speed control using mc33035
1996 - U01A

Abstract:
Text: ) Pin 18 (VCC = 20 V, VC = 30 V) 4 ns V ns V mA IC MOTOROLA ANALOG IC DEVICE , ) 7 MC33035 PIN FUNCTION DESCRIPTION Pin 1, 2, 24 Symbol Description BT, AT, CT , power source ground. 17 VCC This pin is the positive supply of the control IC . The controller , Bottom Drive Outputs is set by the voltage applied to this pin . The controller is operational over a , . In addition, the MC33035 has a 60°/120° select pin which configures the rotor position decoder for


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PDF MC33035/D MC33035 MC33035 U01A MOC8204 MC33035P MC33035DW BT124 751E 1N5819 1N5352A 1N4744
1995 - Not Available

Abstract:
Text: VOLTAGE (V) 7 MC33035 PIN FUNCTION DESCRIPTION Pin 1, 2, 24 Symbol Description BT, AT , The high state (VOH) of the Bottom Drive Outputs is set by the voltage applied to this pin . The , Outputs Bottom Drive Outputs Fault Output MOTOROLA ANALOG IC DEVICE DATA MC33035 Reference The , , the top drives are turned off and the MOTOROLA ANALOG IC DEVICE DATA bottom drive outputs are , the power supplies. Drive Outputs The three top drive outputs (Pins 1, 2, 24 ) are open collector


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PDF MC33035/D MC33035 MC33035 MC33035/D*
Decoder 8 to 256 single ic

Abstract:
Text: CASI 8 CLR 9 TC 10 11, 14, 18, 21, 24 , 28, 32 and 35 V cc A 15 - A e PIN NO. 1, 2 , the outputs . MSEL 4 and 5 RSELo and RSELi December 4, 1985 7 -7 2 Signetics Lo g ic , one-of-four to four-of-four so that all four RAS decoder outputs , RAS0, RAS-i, RAS 2 and RAS 3, go LOW in , generation, clear input, and selectable terminal count (128 or 256) output · Row Address Decoder - four Active Row Address Select (RAS) outputs during refresh · On-Chip Latches - dual 8-bit address latches


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PDF 2964B 2964B 16-bit 72-BIT LS09190S Decoder 8 to 256 single ic Dynamic Memory Controller
1996 - mc44000

Abstract:
Text: ) Composite Sync ( Pin 13) MOTOROLA ANALOG IC DEVICE DATA 21 MC44011 Figure 31. Horizontal Outputs , Field 2/4 Field Ident Out ( Pin 7) 144 µs 24 MOTOROLA ANALOG IC DEVICE DATA MC44011 , ­44 QFP 44 Pin PLCC and QFP Packages Representative Block Diagram Outputs VCC1 Y1 Gnd1 , /Y R/V Outputs MC44011 Figure 1. MOTOROLA ANALOG IC DEVICE DATA MC44011 , 0 Y2 input ( Pin 29) deselected $81­6 Y1 EN 1 Y1 luma path from PAL/NTSC decoder


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PDF MC44011/D MC44011 MC44011, MC44000 MC44011 yx 805 ic motorola 600 ssd MC44145 MC14577 MC14576 PW15k MC74F161 LM 886 IC chip
1996 - yx 805 ic

Abstract:
Text: ) Composite Sync ( Pin 13) MOTOROLA ANALOG IC DEVICE DATA 21 MC44011 Figure 31. Horizontal Outputs , Field 2/4 Field Ident Out ( Pin 7) 144 µs 24 MOTOROLA ANALOG IC DEVICE DATA MC44011 , ­44 QFP 44 Pin PLCC and QFP Packages Representative Block Diagram Outputs VCC1 Y1 Gnd1 , /Y R/V Outputs MC44011 Figure 1. MOTOROLA ANALOG IC DEVICE DATA MC44011 , 0 Y2 input ( Pin 29) deselected $81­6 Y1 EN 1 Y1 luma path from PAL/NTSC decoder


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PDF MC44011/D MC44011 MC44011, MC44000 MC44011 MC44011/D* yx 805 ic yx 805 color pal transistor pattern generator schematic YX 805 4 pin MC44145 MC44140 MC44011FB MC141625
1995 - 87A6

Abstract:
Text: #1 Horizontal PLL/VCO 14.3 MHz Outputs GND2 Data Bus Vertical Decoder R/V G/Y B , 21 20 23 24 SDL 5 6 To µP B/U G/Y R/V Outputs MC44011 Figure 1 , €“ 2.4 – Vdc – 30 + 30 – – – – Deg PAL/NTSC/S–VHS DECODER Video 1 , €“ – 2.4 3.5 1.3 – – – Vdc PAL/NTSC/S–VHS DECODER S–VHS Mode ($77–6, 7 = , 74 Vertical Sync Pulse Width ( Pin 4, NTSC or PAL) 490 500 510 µs 2.4 – â


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PDF MC44011/D MC44011 MC44011, MC44000 MC44011 MC44011/D* 87A6
1996 - SAA4961

Abstract:
Text: controlled, alignment-free PAL/NTSC/SECAM decoder /sync processor TDA9143 PINNING SYMBOL PIN , voltage on the Uin pin must never exceed 5.5 V. If it does, the IC enters a test mode. Using the , , alignment-free PAL/NTSC/SECAM decoder /sync processor TDA9143 I2C-bus For address 8A, an unconnected pin , mA Input switch Caution: the voltage on pin 25 must never exceed 5.5 V, if it does, the IC enters , pin 3 must never exceed 5.5 V, if it does, the IC enters a test mode RGB INPUTS (PINS 21, 20, AND 19


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PDF TDA9143 TDA9141 TDA9143 SAA4961 TDA4665 emg block diagram SDIP32 TDA9141
Not Available

Abstract:
Text: Indicator Output 1 Indicator Output 4 Indicator Output 3 Select Input 3 Select Input 4 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SN76710 Decoder Output 13/14 Decoder Output 11/12 Decoder Output 9/10 Decoder Output 7/8 Decoder Output 5/6 Decoder Output 3/4 , forces the even pin high. This allows "touch tuning" by connecting any decoder output to either the up or , ) pin assignments SN76701 SN76702 Select Input 1 Select Input 2 Analog Input 3 Analog Input 4 Analog


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PDF SN76701, SN76702. SN76710. SN76711 16-Channel SN76701 SN76702 SN76701. SN76710,
1998 - 2088 rgb matrix

Abstract:
Text: /MHz (@3.0 V) · 100- pin TQFP CD-ROM X13769XJ2V0CD00 06-2 Particular Purpose IC DSP s DSP , ) dual-sided µPD3728 7300 × 3 600/A3 5.60 5.10 6.40 40 (20 × 2) 6 (2-output/color (in phase) ­ 24-pin , · 240- pin QFP (Fine Pitch) CD-ROM X13769XJ2V0CD00 06-13 Particular Purpose IC , 44- pin QFP CD-ROM X13769XJ2V0CD00 06-17 Particular Purpose IC Communication IC s LSI , IC µPB1005 2.7 to 3.3 45 72 to 92 · 36- pin plastic QFN Typical performance. (TA =


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PDF X13769XJ2V0CD00 PD77016 160-pin PD77018A 100-pin 116-pin PD77019 30-pin PC667 2088 rgb matrix STEPPING MOTOR DRIVER 18V TSSOP 30 CMOS phone Camera Module 24-pin 5.1 dts audio amplifier circuits with remote cd-rom signal processing 30-pin upd63725 uPD72002-11 UPD72001-11 upc1237 24PIN CAR AUDIO AMPLIFIER IC
AM25LS2538

Abstract:
Text: Am25LS2538 Am25LS2538 One-of-Eight Decoder with Three-State Outputs and Polarity Control DISTINCTIVE CHARACTERISTICS · · · Three-state decoder outputs Buffered common output polarity control , outputs are in the higft-impedance state. The eight outputs for the decoder /demuitipiexer. CEi, ÖE2 , supply ranges GENERAL DESCRIPTION The Am25LS2538 is a three-line to eight-line decoder / demultiplexer fabricated using advanced Low-Power Schottky technology. The decoder has three buffered select inputs-A, B


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PDF Am25LS2538 can38 Am25LS253a IC000090 03664B
1992 - E16-1

Abstract:
Text: four mutually exclusive active LOW outputs (O0-O3). Each decoder has an active LOW enable (E). When E , DECODER WITH ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES TRUTH TABLE(1) PIN DESCRIPTION , Pin Names A 0 , A1 Enable Input (Active LOW) Outputs (Active LOW) 2605 tbl 04 2605 tbl 05 , . Outputs Open fo = 10MHz 50% Duty Cycle One Output Toggling on Each Decoder NOTES: 1. For , CERDIP Small Outline IC Leadless Chip Carrier CERPACK 139 139A 139C Dual 1-of-4 Decoder Fast


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PDF IDT54/74FCT139/A/C IDT54/74FCT139 IDT54/74FCT139A IDT54/74FCT139C IDT54/74FCT139/A/C IDT54/74FCT139 IDT54/74FCT139A MIL-STD-883, E16-1
HARRIS DIP 24PIN

Abstract:
Text: , +12 V/+15 V power supply voltage range, variable threshold levels, and single ( 24-pin DDIP or square) and com pletely independent dual redundant (36- pin DOIP) packaging configura tions. All models are , Compatibility · Small Size: Single - 24-Pin DDIP o r Square Dual - 36- Pin DDIP Flat Packs · Low Power · High , drawing 5962-86049-02ZC. - Packaging 0 = 24-Pin Square DIP 6 = 24-Pin Square Flat Pack , 000 ILC D A T A D E V IC E C O R PO R A TIO N S_ BUS-63100 MIL-STD-1553 DATA BUS SINGLE AND


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PDF BUS-63100 MIL-STD-1553 BUS-63102 BUS-63105 BUS-63125 BUS-63100 MIL-STD1553A 1553B. 24-pin 36-pin HARRIS DIP 24PIN BUS-631 BUS-63102 MIL-PRF-38534
1994 - transistor a017

Abstract:
Text: holding this pin high. Pulsed high to cancel tones or replay calls. Decoder is switched to `MEM' (memory , power up, a reset pulse is generated from the charging of a capacitor connected to the decoder RESET pin , a logic `1` on the MEM pin . The tone outputs TO1, TO2 are inhibited and the vibrator (VIB) and , ' flag from a radio receiver on the BLI pin . The decoder samples the state of this pin at 256 Hz when the , +70°C. All outputs open circuit. Voltage doubler disabled. VDD2 = VDD1 Parameters SUPPLY CURRENT Decoder


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PDF DS2464 MV6639 MV6639 transistor a017
1994 - SL6609

Abstract:
Text: `ON' by holding this pin high. Pulsed high to cancel tones or replay calls. Decoder is switched to , up, a reset pulse is generated from the charging of a capacitor connected to the decoder RESET pin , pin . The decoder samples the state of this pin at 256 Hz when the receiver is enabled, as shown in , /CANCEL input pin . The low battery detection circuit will be re-armed whenever decoder status is changed , FEBRUARY 1994 ADVANCE INFORMATION DS2464 - 4.9 MV6639 POCSAG DECODER (Supersedes November 1992


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PDF DS2464 MV6639 MV6639 SL6609 POCSAG Receiver m.Sc part 2nd date sheet DO21 D021 D020 D019 CB09a
HCTL-2022

Abstract:
Text: Products > Motion Control Encoder Solutions > Integrated Circuits > Decoder > HCTL-2032 HCTL-2032 Quadrature Decoder IC Description The HCTL-2032 is CMOS ICs that perform the quadrature decoder , counter , Counter Latched Outputs 8-Bit Tristate Interface 8, 16, 24 , or 32-Bit Operating Modes Quadrature , -Bit Binary Up/Down Counter Latched Outputs 8-Bit Tristate Interface 8, 16, 24 , or 32-Bit Operating Modes , , decoder and cascade outputs , index channel support, programmable count modes, and 33 Mhz clock operation


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PDF HCTL-2032 HCTL-2032 HCTL2032 HCTL-2022 Decoder 5 to 32 single ic Quadrature Decoder Interface ICs quadrature encoder 4X quadrature decoder HCTL-2032-SC HCTL-2032-SCT HCTL-20XX-XX hctl 2032 encoder counter
2001 - 1N5819

Abstract:
Text: ) and IC (b) inputs. 24 LL Local Loopback; TTL input; source for LL(a) and LL(b) outputs . 35 , from IC (a) and IC (b) inputs. 24 LL Local Loopback; TTL input; source for LL(a) and LL(b , output; sourced from IC (a) and IC (b) inputs. 24 LL Local Loopback; TTL input; source for LL(a , Indicate; TTL output; sourced from IC (a) and IC (b) inputs. 24 LL Local Loopback; TTL input; source , includes a latch enable pin with the driver and receiver address decoder . Tri-state ability for the driver


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PDF SP502 SP502 RS-232 RS-422A RS-449, RS-485, EIA-530. SP5301 SP5301CN 1N5819 Analog 5.1 decoder IC RS-422A RS-449 RTS-54 SP526CF
1994 - SL6609

Abstract:
Text: `ON' by holding this pin high. Pulsed high to cancel tones or replay calls. Decoder is switched to , up, a reset pulse is generated from the charging of a capacitor connected to the decoder RESET pin , pin . The decoder samples the state of this pin at 256 Hz when the receiver is enabled, as shown in , /CANCEL input pin . The low battery detection circuit will be re-armed whenever decoder status is changed , FEBRUARY 1994 ADVANCE INFORMATION DS2464 - 4.9 MV6639 POCSAG DECODER (Supersedes November 1992


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PDF DS2464 MV6639 MV6639 SL6609 CB09a digital wrist watch circuit lcd wrist watch ic pager in watch -abstract plessey gps receiver
Not Available

Abstract:
Text: Products Product Specification D yn am ic M em ory Controller 2964B 2964B PACKAGE/ PIN , outputs . The RAS decoder Select inputs. Data (latched) at these inputs (normally higherorder addresses , generation, clear input, and selectable terminal count (128 or 256) output • Row Address Decoder — four Active Row Address Select (RAS) outputs during refresh • On-Chip Latches — dual 8-bit address latches and RAS decoder latches • User-Selectable Refresh Modes — burst, distributed or


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PDF 2964B 2964B 16-bit 22-err 8D02160S
1997 - TDA4690

Abstract:
Text: PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE TDA4655 24 SDIL , burstkey pulse which is derived from the sandcastle pulse present at pin 24 . The generated error current , multi-standard decoder demodulated signal. The result is an identification signal (PIDT, pin 15) that is , detector the super sandcastle pulse (SC) present at pin 24 is compared with three internal threshold , load - 330 mW V24 voltage at pin 24 Imax = 10 µA - 15 V voltage at all


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PDF TDA4655 TDA4655 TDA4660/61. TDA4690 tda2579 TDA2579B SDIP24 SO24 TDA4655T
T7280

Abstract:
Text: of the other channels. The T7280 is manufactured by using CMOS technology and is available in a 24-pin , . Pin Diagrams Table 1. Pin Descriptions DIP PLCC 24 26 Symbol PCM PSS Type Nam e/Function PCM In , pulse. Output Enable. A high on this pin enables both DOUT and KOUT outputs . A low on this pin , to decoder . /¿-law Coding. A high on this pin for //-law and a low for A-law coding. Channel Reset (Active-Low). A low on this pin resets the channel. Decoder . A high on this pin enables the decoder ; a low


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PDF T7280 16-channel T7280-PC
1997 - ht6p200

Abstract:
Text: 2 24 HT6P11 Learning Decoder Features · · · · · · · · · · · · · · , information at maximum. The decoder provides 0/2/4 data outputs for various applications. · Learning , turning on the power. In the waiting state, the M0(DO) pin is high and the LEARN(LED) pin outputs a , on the LH/MM(SK) pin The data outputs follow the encoder only during a valid transmission. Latch type Externally pulled-low on the LH/MM(SK) pin The data outputs follow the encoder during a valid


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PDF HT6P11 100ms 24-bit HT6P20) HT6P20A HT6P20D HT6P20C ht6p200 smoke alarm ic 555 burglar alarm ic 555 HT6P11 HT6P20B remote control car circuit diagram m1 series ltm9052 fire alarm using 555 HT6P20B controller remote LEARN ELECTRONIC CAR
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